JP3220961B2 - Manufacturing method of epitaxial semiconductor wafer - Google Patents
Manufacturing method of epitaxial semiconductor waferInfo
- Publication number
- JP3220961B2 JP3220961B2 JP19759792A JP19759792A JP3220961B2 JP 3220961 B2 JP3220961 B2 JP 3220961B2 JP 19759792 A JP19759792 A JP 19759792A JP 19759792 A JP19759792 A JP 19759792A JP 3220961 B2 JP3220961 B2 JP 3220961B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- epitaxial
- semiconductor wafer
- manufacturing
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【0001】[0001]
【産業上の利用分野】この発明は、デバイス・プロセス
中において、特に重金属汚染に対して特性劣化の度合い
が低く、高歩留でのLSI製造を可能にしたエピタキシ
ャル半導体ウエーハの製造方法に係り、重金属汚染に対
して強力なゲッタリング能を有するが、高酸素濃度で酸
素析出物の成長が著しく、従来、使用されることのなか
った比抵抗が1/10Ω・cm以下のボロンドープ基板
を特定の熱処理を施してから気相成長させることによ
り、高品質のシリコンエピタキシャル薄膜を成膜できる
エピタキシャル半導体ウエーハの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an epitaxial semiconductor wafer, which has a low degree of characteristic deterioration particularly in heavy metal contamination during a device process and enables high-yield LSI manufacturing. Although it has a strong gettering ability against heavy metal contamination, the growth of oxygen precipitates is remarkable at high oxygen concentration, and a boron-doped substrate having a resistivity not exceeding 1/10 Ωcm, which has not been conventionally used, is specified. The present invention relates to a method for manufacturing an epitaxial semiconductor wafer capable of forming a high-quality silicon epitaxial thin film by performing a heat treatment and then performing a vapor phase growth.
【0002】[0002]
【従来の技術】半導体シリコンウエーハにエピタキシャ
ル薄膜を成長させるプロセスは、通常、気相成長装置で
行われ、以下の如きプロセスからなる。まず、水素ガス
などの不活性ガス雰囲気内で所定の温度域まで昇温し、
引き続き塩化水素を含むガス等によるエッチングを数分
間行い、表面コンタミネーション除去及びウエーハ表面
の活性化を行った後、シラン系ガスを用いてウエーハ表
面にエピタキシャル薄膜を成長させるものである。2. Description of the Related Art A process for growing an epitaxial thin film on a semiconductor silicon wafer is usually performed in a vapor phase growth apparatus, and comprises the following processes. First, the temperature is raised to a predetermined temperature range in an inert gas atmosphere such as hydrogen gas,
Subsequently, etching with a gas containing hydrogen chloride or the like is performed for several minutes to remove surface contamination and activate the wafer surface, and thereafter, an epitaxial thin film is grown on the wafer surface using a silane-based gas.
【0003】しかし、この塩化水素を含むガス等による
エッチングプロセスでは、表面コンタミネーションの除
去不足、及び結晶引上げ過程ですでに育成された微小欠
陥を完全に消滅させることができず、さらに塩化水素ガ
スの選択エッチング性によりウェーハ表面のピットを増
加させる傾向にある。従って、塩化水素系ガスエッチン
グ後にエピタキシャル薄膜を成長させる際、上記の欠陥
等を起点として薄膜内に積層欠陥、転位などの欠陥を発
生させる。[0003] However, in the etching process using a gas containing hydrogen chloride or the like, insufficient removal of surface contamination and minute defects already grown during the crystal pulling process cannot be completely eliminated. Tends to increase the number of pits on the wafer surface due to the selective etching property. Therefore, when growing an epitaxial thin film after etching with a hydrogen chloride gas, defects such as stacking faults and dislocations are generated in the thin film starting from the above-mentioned defects.
【0004】[0004]
【発明が解決しようとする課題】また、デバイスプロセ
ス工程内での重金属汚染によるデバイス特性の劣化要因
の低減方法としてイントリンシックゲッタリング処理を
用いることがある。一方、ボロン・ドープシリコン基板
のうち、比抵抗1/10Ω・cm以下の基板(以降P+
基板という)は、本来重金属汚染に対して強力なゲッタ
リング能を有することが知られており、D−RAM、パ
ワーMOS等のデバイスに使用されている。In addition, an intrinsic gettering process may be used as a method of reducing a factor for deteriorating device characteristics due to heavy metal contamination in a device process. On the other hand, of the boron-doped silicon substrates, those having a specific resistance of 1/10 Ω · cm or less (hereinafter P +
(Referred to as a substrate) is originally known to have strong gettering ability against heavy metal contamination, and is used for devices such as D-RAM and power MOS.
【0005】しかし、D−RAM、パワーMOS等のデ
バイスに使用されるP+基板の仕様品は、通常、酸素濃
度が13×1017atoms/cm3以下のものが用い
られる。これは、P+基板が他の基板と比較して非常に
酸素析出物が成長しやすいためであり、従って、従来の
エピタキシャルプロセスでは、薄膜成長中にP+基板表
面上に酸素析出物が成長し、それを起点として薄膜内に
積層欠陥、転位等の欠陥を発生させ、高品質エピタキシ
ャル・シリコン薄膜の製造ができないためである。[0005] However, as a specification product of a P + substrate used for a device such as a D-RAM and a power MOS, usually, a product having an oxygen concentration of 13 × 10 17 atoms / cm 3 or less is used. This is because the P + substrate is much more susceptible to growth of oxygen precipitates than other substrates, and therefore, in conventional epitaxial processes, oxygen precipitates grow on the P + substrate surface during thin film growth. However, it causes defects such as stacking faults and dislocations in the thin film starting from the starting point, and it is impossible to manufacture a high quality epitaxial silicon thin film.
【0006】この発明は、高酸素濃度P+基板を用いて
エピタキシャル薄膜の欠陥密度を低減化し、更に重金属
汚染に対して強力なゲッタリング能を有する高品質シリ
コン・エピタキシャル薄膜を成長できるエピタキシャル
半導体ウエーハの製造方法の提供を目的とする。The present invention is directed to an epitaxial semiconductor wafer capable of reducing the defect density of an epitaxial thin film using a high oxygen concentration P + substrate and growing a high quality silicon epitaxial thin film having strong gettering ability against heavy metal contamination. The purpose of the present invention is to provide a manufacturing method.
【0007】[0007]
【課題を解決するための手段】この発明は、高品質シリ
コン・エピタキシャル薄膜を成長できるエピタキシャル
半導体ウエーハの製造方法の提供を目的に種々検討した
結果、気相成長前に高温水素熱処理することにより、半
導体基板表面及びその近傍のエピタキシャル薄膜欠陥の
発生起点を消滅可能であることに着目し、特に、従来使
用されることのなかった高酸素濃度P+基板を用いてエ
ピタキシャル薄膜の欠陥密度を低減化でき、更に重金属
汚染に対して強力なゲッタリング能を有するエピタキシ
ャル半導体ウエーハを提供できることを知見し、この発
明を完成した。SUMMARY OF THE INVENTION The present invention has been studied for the purpose of providing a method of manufacturing an epitaxial semiconductor wafer capable of growing a high-quality silicon epitaxial thin film. Focusing on the fact that the starting point of epitaxial thin film defects at and near the semiconductor substrate surface can be eliminated, in particular, reducing the defect density of epitaxial thin films using a high oxygen concentration P + substrate that has not been used before. The present inventors have found that it is possible to provide an epitaxial semiconductor wafer having strong gettering ability against heavy metal contamination, and completed the present invention.
【0008】すなわちこの発明は、半導体ウエーハの表
面にシリコン薄膜を気相成長させるエピタキシャル半導
体ウエーハの製造方法において、比抵抗1/10Ω・c
m以下のP+基板、特に従来使用対象外の高酸素濃度P+
基板、酸素濃度が13×1017atoms/cm3以上
のP+基板を、水素100%あるいはAr又はHeを含
む水素ガス雰囲気内で1000℃以上で3分間以上保持
する熱処理を施した後、前記のウエーハ表面にシリコン
薄膜を気相成長させることを特徴とするエピタキシャル
半導体ウエーハの製造方法である。That is, the present invention provides a method of manufacturing an epitaxial semiconductor wafer in which a silicon thin film is vapor-phase grown on the surface of a semiconductor wafer.
m or less P + substrate, particularly conventionally used outside the scope of the high oxygen concentration P +
A substrate, a P + substrate having an oxygen concentration of 13 × 10 17 atoms / cm 3 or more, was made to contain 100% hydrogen or Ar or He.
Hold at 1000 ° C or more for 3 minutes or more in a hydrogen gas atmosphere
A method of manufacturing an epitaxial semiconductor wafer, characterized in that a silicon thin film is vapor-phase grown on the surface of the wafer after the heat treatment.
【0009】また、この発明は、上記の構成において1
000℃以上の温度で3分間以上保持する熱処理条件を
特徴とするエピタキシャル半導体ウエーハの製造方法で
ある。Further, the present invention provides the above-described configuration.
This is a method for manufacturing an epitaxial semiconductor wafer, characterized by heat treatment conditions of holding at a temperature of 000 ° C. or more for 3 minutes or more.
【0010】この発明において水素雰囲気での熱処理条
件は、薄膜欠陥密度を0.1個/cm2以下とするには
1000℃以上の高温が必要であり、好ましくは100
0℃〜1200℃である。また、熱処理時間は上記の効
果を得るには少なくとも3分間以上が必要であり、更
に、上記の熱処理温度までの昇温速度やその雰囲気は、
通常のエピタキシャル条件でよい。この発明において熱
処理雰囲気は、水素100%が望ましいが、Ar,He
などの不活性ガスとH2ガスの混合雰囲気でもよい。[0010] heat treatment conditions in hydrogen atmosphere in the present invention, a thin film defect density is 0.1 pieces / cm 2 or less is required a high temperature of at least 1000 ° C., preferably 100
0 ° C to 1200 ° C. In addition, the heat treatment time needs at least 3 minutes or more to obtain the above-mentioned effect, and further, the temperature rising rate up to the heat treatment temperature and its atmosphere are as follows:
Normal epitaxial conditions may be used. In the present invention, the heat treatment atmosphere is desirably 100% hydrogen.
Or a mixed atmosphere of an inert gas and H 2 gas, such as.
【0011】[0011]
【作用】この発明は、半導体シリコンウエーハ上にシリ
コン薄膜を気相成長させるプロセスの前工程として高温
水素アニール処理を導入することにより、半導体基板表
面及びその近傍のエピタキシャル薄膜欠陥の発生起点を
消滅させることを特徴としている。すなわち、シリコン
基板内の微小欠陥を、水素による還元作用により縮小ま
たは消滅させることにより、エピタキシャル薄膜欠陥密
度を0.1個/cm3以下の高品質エピタキシャル薄膜
を形成可能にしたものである。According to the present invention, a high-temperature hydrogen annealing treatment is introduced as a pre-process of a process for vapor-phase growth of a silicon thin film on a semiconductor silicon wafer, thereby eliminating the origin of epitaxial thin film defects at and near the semiconductor substrate surface. It is characterized by: That is, by reducing or eliminating minute defects in the silicon substrate by the reducing action of hydrogen, a high-quality epitaxial thin film having an epitaxial thin film defect density of 0.1 / cm 3 or less can be formed.
【0012】[0012]
【実施例】実施例1 試料には、CZシリコン単結晶ウエーハ、比抵抗1/5
0Ω以下P+基板を使用した。酸素濃度により以下の如
く、3水準に振りわけた。 サンプルA…11〜12×1017atoms/cm3 サンプルB…15〜16×1017atoms/cm3 サンプルC…17×1017atoms/cm3以上 上記サンプルA、B、Cを1150℃×2hrの条件で
酸素、窒素混合ガス雰囲気の熱処理を施した後、選択エ
ッチングを実施し、バルク中の微小欠陥密度を調査し
た。図1にその結果を示す。サンプルB、Cでは微小欠
陥密度が106×107個/cm2に成長しているが、サ
ンプルAでは微小欠陥の発生はみられなかった。一方、
表面の微小欠陥密度は、サンプルB、Cでは102個/
cm2以上であることがわかる。Example 1 A sample was a CZ silicon single crystal wafer, and the specific resistance was 1/5.
A P + substrate of 0Ω or less was used. It was divided into three levels as follows according to the oxygen concentration. Sample A: 11 to 12 × 10 17 atoms / cm 3 Sample B: 15 to 16 × 10 17 atoms / cm 3 Sample C: 17 × 10 17 atoms / cm 3 or more Samples A, B, and C at 1150 ° C. × 2 hr After performing a heat treatment in a mixed gas atmosphere of oxygen and nitrogen under the conditions described above, selective etching was performed to investigate the density of minute defects in the bulk. FIG. 1 shows the results. In Samples B and C, the microdefect density was increased to 10 6 × 10 7 / cm 2 , but in Sample A, no generation of microdefects was observed. on the other hand,
Micro defect density of the surface, the sample B, the C 10 2 pieces /
It can be seen that it is not less than cm 2 .
【0013】従って、高酸素濃度P+基板は、従来のエ
ピタキシャル薄膜プロセスでは基板表面に微小欠陥が成
長し、薄膜形成時にその欠陥を起点としてエピタキシャ
ル薄膜内に欠陥を発生させることが理解できる。Therefore, it can be understood that, in the high oxygen concentration P + substrate, a minute defect grows on the substrate surface in the conventional epitaxial thin film process, and a defect is generated in the epitaxial thin film starting from the defect when the thin film is formed.
【0014】実施例2 実施例1におけるサンプルBを使用し、気相成長装置内
で水素100%の雰囲気中で、処理温度を900℃、1
000℃、1100℃、1200℃の種々の温度とし、
それぞれ10分間の熱処理を行った。その後、引き続い
て塩化水素ガスでウエーハエッチングを行い、さらにト
リクロロシランガスにて気相成長薄膜形成を行った。得
られたエピタキシャルウエーハを選択エッチングし、微
小欠陥密度を測定した。この発明による水素雰囲気中で
の高温熱処理の温度依存性を図2に示す。すなわち、同
一処理時間ではこの発明による水素雰囲気での熱処理温
度が高温であるほど、欠陥抑制効果が高いことがわか
る。Example 2 Using the sample B of Example 1, the treatment temperature was set to 900 ° C. in a 100% hydrogen atmosphere in a vapor phase growth apparatus.
000 ° C, 1100 ° C, various temperatures of 1200 ° C,
Each was heat-treated for 10 minutes. Thereafter, the wafer was subsequently etched with a hydrogen chloride gas, and a vapor phase grown thin film was formed with a trichlorosilane gas. The obtained epitaxial wafer was selectively etched, and the fine defect density was measured. FIG. 2 shows the temperature dependency of the high-temperature heat treatment in a hydrogen atmosphere according to the present invention. In other words, it can be seen that the higher the heat treatment temperature in a hydrogen atmosphere according to the present invention for the same treatment time, the higher the defect suppression effect.
【0015】次に、この発明による水素雰囲気での熱処
理温度を1100℃に固定し、処理時間を種々変化させ
た後、薄膜形成を行い、薄膜内の欠陥密度を測定した。
図3に処理時間と薄膜内の微小欠陥密度の関係で示す如
く、同一処理温度では、処理時間が長いほど欠陥抑制効
果が高いことがわかる。Next, a heat treatment temperature in a hydrogen atmosphere according to the present invention was fixed at 1100 ° C., and after variously changing the treatment time, a thin film was formed, and the defect density in the thin film was measured.
As shown in FIG. 3 as a relationship between the processing time and the density of minute defects in the thin film, it can be seen that, at the same processing temperature, the longer the processing time, the higher the defect suppression effect.
【0016】実施例3 ゲッタリング能力を調査するため、実施例1のサンプル
A及びBをこの発明による水素雰囲気での熱処理する前
に、Ni定量汚染を実施した。なお、定量汚染は、10
10〜1013atoms/cm3標準溶液を用い、スピン
コート汚染にて試料を作製した。その後、水素100%
の雰囲気中で、1100℃×10分間のこの発明による
水素雰囲気での熱処理を施し、引き続きエピタキシャル
薄膜形成を行った。エピタキシャル薄膜形成後の酸素誘
起積層欠陥(OSF)を観察するため、1000℃×1
6時間の酸素雰囲気中で熱処理を行い、選択エッチング
により欠陥密度を測定した。図4に示す如く、サンプル
Bでは1013atoms/cm2のNi汚染でもOSF
の発生は観察できない。一方、サンプルAでは1011a
toms/cm2程度の汚染域からOSFの発生が見ら
れる。Example 3 In order to investigate the gettering ability, the samples A and B of Example 1 were subjected to Ni quantitative contamination before heat treatment in a hydrogen atmosphere according to the present invention. The quantitative contamination was 10
Samples were prepared by spin coating contamination using 10 to 10 13 atoms / cm 3 standard solution. Then 100% hydrogen
Was performed in a hydrogen atmosphere at 1100 ° C. for 10 minutes according to the present invention, and an epitaxial thin film was subsequently formed. 1000 ° C. × 1 to observe oxygen-induced stacking fault (OSF) after epitaxial thin film formation
Heat treatment was performed in an oxygen atmosphere for 6 hours, and the defect density was measured by selective etching. As shown in FIG. 4, in the sample B, even if the Ni contamination was 10 13 atoms / cm 2 , the OSF
No occurrence can be observed. On the other hand, in sample A, 10 11 a
OSF is generated from a contamination area of about toms / cm 2 .
【0017】すなわち、この発明による水素雰囲気中で
の高温熱処理は、1000℃で3分間以上、好ましくは
5分間以上の熱処理により、高酸素濃度P+基板上に低
密度欠陥エピタキシャル薄膜形成を可能にし、かつ、強
力なゲッタリング能力を有する高品質エピタキシャル薄
膜の形成を実現できることがわかる。That is, the high-temperature heat treatment in a hydrogen atmosphere according to the present invention makes it possible to form a low-density defect epitaxial thin film on a high oxygen concentration P + substrate by heat treatment at 1000 ° C. for 3 minutes or more, preferably 5 minutes or more. It can be seen that a high quality epitaxial thin film having strong gettering ability can be formed.
【0018】[0018]
【発明の効果】この発明は、高酸素濃度P+基板をシリ
コン薄膜の気相成長前に水素雰囲気での熱処理、例えば
1000℃以上で3分間以上保持する処理を施すことに
より、ウエーハ基板表面の欠陥を消滅させることができ
るため、その後の気相成長薄膜形成にて薄膜内の欠陥密
度が0.1個/cm2以下と極めて高品質のシリコンエ
ピタキシャル薄膜を成膜できる。従って、重金属汚染に
対して強力なゲッタリング能を有するが、高酸素濃度で
酸素析出物が成長が著しく使用されることのなかった高
酸素濃度P+基板を、D−RAM、POW−MOS等の
デバイスに使用可能となし、かつ極めて高品質のシリコ
ンエピタキシャル薄膜を成膜したエピタキシャル半導体
ウエーハを提供できる。Effects of the Invention The present invention, a high oxygen concentration P + substrate heat treatment in the hydrogen atmosphere prior to the vapor phase growth of the silicon thin film, by performing a process of holding for example 1000 ° C. or more than three minutes, the wafer substrate surface Can be eliminated, and a very high-quality silicon epitaxial thin film having a defect density of 0.1 / cm 2 or less can be formed in the subsequent vapor-phase growth thin film formation. Therefore, a high oxygen concentration P + substrate which has a strong gettering ability against heavy metal contamination but whose growth of oxygen precipitates is not significantly used at a high oxygen concentration is reduced to a D-RAM, POW-MOS or the like. It is possible to provide an epitaxial semiconductor wafer which can be used for the above-mentioned device and has an extremely high quality silicon epitaxial thin film formed thereon.
【図1】酸素濃度と微小欠陥密度との関係を示すグラフ
である。FIG. 1 is a graph showing the relationship between oxygen concentration and minute defect density.
【図2】アニール温度とシリコン薄膜の微小欠陥密度と
の関係を示すグラフである。FIG. 2 is a graph showing a relationship between an annealing temperature and a minute defect density of a silicon thin film.
【図3】アニール時間とシリコン薄膜の微小欠陥密度と
の関係を示すグラフである。FIG. 3 is a graph showing a relationship between an annealing time and a minute defect density of a silicon thin film.
【図4】表面Ni汚染濃度とOSF欠陥密度との関係を
示すグラフである。FIG. 4 is a graph showing a relationship between a surface Ni contamination concentration and an OSF defect density.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/02 H01L 21/205 H01L 21/365 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/02 H01L 21/205 H01L 21/365
Claims (1)
気相成長させるエピタキシャル半導体ウエーハの製造方
法において、酸素濃度が13×10 17 atoms/cm
3 以上で比抵抗が1/10Ω・cm以下のボロンドープ
基板に、水素100%あるいはAr又はHeを含む水素
ガス雰囲気で1000℃以上で3分間以上保持する熱処
理を施した後、前記ウエーハ表面にシリコン薄膜を気相
成長させることを特徴とするエピタキシャル半導体ウエ
ーハの製造方法。1. A method for manufacturing an epitaxial semiconductor wafer, wherein a silicon thin film is vapor-phase grown on a surface of a semiconductor wafer, wherein the oxygen concentration is 13 × 10 17 atoms / cm.
Specific resistance below the boron doping substrate 1 / 10Ω · cm 3 or more, the hydrogen containing 100% hydrogen or Ar or He
A method for manufacturing an epitaxial semiconductor wafer, comprising: performing a heat treatment in a gas atmosphere at 1000 ° C. or more for 3 minutes or more, and then performing a vapor phase growth of a silicon thin film on the surface of the wafer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19759792A JP3220961B2 (en) | 1992-06-30 | 1992-06-30 | Manufacturing method of epitaxial semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19759792A JP3220961B2 (en) | 1992-06-30 | 1992-06-30 | Manufacturing method of epitaxial semiconductor wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0620897A JPH0620897A (en) | 1994-01-28 |
JP3220961B2 true JP3220961B2 (en) | 2001-10-22 |
Family
ID=16377133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19759792A Expired - Lifetime JP3220961B2 (en) | 1992-06-30 | 1992-06-30 | Manufacturing method of epitaxial semiconductor wafer |
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1992
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