JPH03296090A - Display device - Google Patents

Abstract

PURPOSE:To transfer image information again normally without resetting a HOST CPU even if malfunction occurs by providing a means which interrupts the control by a display control means forcibly and restarting the control by the display control means after the interruption. CONSTITUTION:When an external noise appears on a control line PD0-7 and a display unit controller 8 receives image information as display mode change request data by mistake, a horizontal synchronizing(Hsync) signal is set to an L level and an incorrect display mode number is received from a graphic controller 9. Then an input/output identification(IH/OL) signal is expected to rise to an H level and the image information is not written in a display panel 2; and a back light 13 and display drivers 3 and 4 are powered off a specific time later and an interruption(INT) signal is sent to a controller 9. The controller 9 restarts a communication and the control recovers to its normal state. Consequently, even if malfunction occurs, the image information is transferred normally to the display panel 2 without resetting the HOST CPU.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for controlling a display device, and in particular, a method for controlling a display device, in which a scanning signal line and an information signal line are sandwiched between matrix electrodes, and a scanning signal and an information signal are respectively applied. The present invention relates to a control method for displaying video information using a liquid crystal display device that is driven by a computer and has a memory property and whose driving conditions are temperature dependent. .

[Prior Art 1] In recent years, disk displays such as liquid crystal display devices required for personal computers, workstations, etc. have become larger and have higher resolution year by year, while compatibility with conventional devices is also required. For example, in the case of an IBM PC/AT personal computer that is often used for boat fishing, the display mode for the image adapter is CGA, EGA, VGA, 8514/8514/
There are over 10 display modes such as A, each with different resolution and number of colors that can be displayed.

As a product that can display many display modes on one display, NEC's Mul
tiSync n, MultiSync 3D, 4
MultiSync 4 as an example with D, 5D, etc.
The Video Modes (display modes) supported by D and 5D are shown in Table.

On the other hand, display devices with memory properties such as ferroelectric liquid crystal display devices are different from those used in conventional display devices such as CRT, 5TN-LCD (super twist liquid crystal display), and PDP (plasma display). The basic operating principle is different. Therefore, the partial write scanning method that takes advantage of the memory property proposed in U.S. Patent No. 4,655,561 by Kannabe et al. We are attempting to achieve this by a method of realizing ``low frame frequency driven ten-part write scanning'' in order to perform high-resolution display in a display device having this memory capability.

However, using this ferroelectric liquid crystal display (FLC),
In order to meet the above-mentioned demand for supporting various display modes, it is naturally impossible to achieve this using conventional methods due to the new driving principle. A complete set of essential features for users to use this ferroelectric liquid crystal display device connected to a computer to use one of the various display modes from the time the power is turned on, and to change the display mode as necessary. Control methods must be proposed.

Using a ferroelectric liquid crystal display device as an example, we present the overall configuration and its control method to support various display modes, especially for IBM PC/AT machines, and also support a 1280x1024 high-definition mode. .

A ferroelectric liquid crystal display device, which is a typical example of a display device having memory properties, has a temperature dependence of driving conditions as typified by FIG. In this example, 7Hz at 10℃ and 10H at 25℃
z and shows that the frame frequency is 20Hz at 40℃ (1024 scanning lines, 24V drive voltage, when using KMT-408 manufactured by Chisso Japan). From this, if the temperature was 10℃ when the power was turned on. Flicker is caused by the 8-line interlacing in low-frequency drive that was proposed earlier.
can be prevented. However, if the environmental temperature of the display rises after the start of operation, for example due to heating due to backlight lighting or forced use of an external heater, if the environmental temperature reaches 25 degrees Celsius, 4-line interlacing will be required. Flicker can be sufficiently prevented, and the phenomenon of division of the display screen during scroll display, for example, when displaying a moving image screen, which was the only drawback of 8-line interlacing, can be reduced. Further, even at the same temperature, the driving method changes depending on the display mode. For example, Table
The FLC display, which was previously 10Hz in display mode with 1024 scanning lines, now has 480 scanning lines in VGA mode, and the frame frequency is over 20Hz.
Regular (two-line) interlacing can sufficiently prevent flicker and further reduce screen division when displaying moving images. However, in the conventional methods, although there is a method for determining the display mode, there is no method that can change the frame frequency of the display together with the display environment temperature.

Furthermore, since the FLC display is an XY matrix display, the number of pixels cannot be changed depending on the display mode by simply changing the beam frequency. X
-The physical pixel number of a Y matrix display is uniquely determined at the time of production and cannot be changed, so it becomes necessary to convert the logical pixel number required for the display mode into a physical pixel number.

Furthermore, if the input information does not match the colors and the number of gradations that can be displayed on the display side, for example, the display side may display monochrome with 8 gradations, while the input information side may display 2 each of RGB.
If 56 gradations are required, the relationship between the colors of this input information and output information and the number of gradations must be determined in accordance with each display mode.

Furthermore, if the driving conditions for the FLC display are not met, for example, if the environmental temperature has not reached the display operating temperature range, the display side may issue a wait request to the image information generating side to make it wait. Further, after a reset, if it is desired to quickly return to the display mode before the reset, it is necessary to be able to read out various control/driving parameters and sometimes image information before the reset.

Even if individual means are prepared to satisfy the above requirements, from the user's perspective, it is desirable to be able to easily change the settings based on a certain procedure not only when the power is turned on but also during operation. , otherwise you would have to turn off the power and turn it on again or set it every time you want to change the display mode.

In particular, when changing the display mode that has been set, it may not be sufficient to simply set the display mode to a new one. For example, assume that you are currently in VGA mode and some application software requests EGA mode, so you set it back to EGA mode. When you try to return to the display mode after quitting this application software and restoring the display mode, you may not be able to return to the previous image information unless the various FLC display control parameters mentioned before changing the display mode are saved somewhere. Therefore, it is necessary to read out the control or driving parameters of the FLC display and the image data before conversion into image information on the FLC display by certain programming.

In order to manufacture a computer equipped with an FLC display that satisfies the above-mentioned requirements, it is necessary to prepare a ROM (referred to as ROM BIOS) in which the necessary requirements are programmed in advance according to the product. This ROM B
The IOS actually controls the interface for controlling and displaying the computer and the FLC display, allowing the user to control display modes and the like without requiring detailed knowledge of controlling and driving the FLC display.

[Problems to be Solved by the Invention] However, two problems have arisen by controlling and driving the display panel using a ROM BIOS program that controls communications.

One is when the HOST CPU requests a display mode using application software and starts controlling the display panel, but during the control, external noise is superimposed on the control line, or the control line is opened. If a short circuit occurs, the program in the ROM BIOS will not be able to continue. As a result, R.O.
The program in the M BIOS receives the display mode change request from the HOST CPU and performs subsequent control.
For example, it becomes impossible to control the transfer of image information to the display panel. In this state, the HOSTCPU cannot update the image information on the display panel, so it becomes impossible to monitor the state of the CPU. In order to recover, the CPU body is reset, which leads to the destruction of the information processed up to that point.

The second problem is that when the above condition occurs, the display panel is also unable to receive image information, so the same image information remains on the display panel until recovery from this condition. This causes a long-term afterimage phenomenon called "burn-in" to occur on the panel.

An object of the present invention is to provide a display device that solves the above-mentioned problem caused by malfunctions during display panel control on the HOST side or the display panel side.

[Means for Solving the Problems (and Effects)] According to the present invention, the display control means that controls the driving condition control means according to the display mode stored in the display mode storage means is forced to interrupt the display control. means for restarting the display control with a signal from the drive condition control means;
The first problem is solved by providing means that can set the timing of interruption of control in the display control means to an arbitrary time in advance. In addition, the display control means has a means for controlling the power supply of the drive element of the drive condition control means and the power supply of peripheral devices such as a backlight necessary for the display element to be turned off and on after the control is interrupted, thereby solving the second problem. This is to solve the problem.

Particularly, the present invention provides a display panel in which: (a) scanning signal electrodes and information signal electrodes are arranged mutually in a matrix, and a liquid crystal having memory properties and temperature dependence whose characteristics change depending on the environmental temperature is arranged therebetween; (b) scanning. Driving means for applying a scanning signal to the signal electrode and information signal to the information signal electrode; Image information storage means for storing image information to be displayed on the C9 display panel; Display mode for image information to be displayed on the d1 display panel. display mode storage means for storing e9 image information storage means, display control means for sequentially retrieving image information to be displayed from the image information storage means and controlling the drive means according to the display mode stored in the display mode storage means, the means Display control means includes means for forcibly interrupting the control by the display control means, and restarting the control by the display control means after the interruption, Preferably, the display control means is configured to control the control by the display control means. means for forcibly interrupting the display, restarting the control by the display control means after the interruption, and arbitrarily setting the start and end of the interruption, and controlling the ON and OFF of the power after the control by the means is interrupted. have the means to do so.

〔Example〕

Details will be explained below based on examples.

FIG. 1 shows a display panel 2 (1280
ixels), display driver 3.4, display unit controller 8 incorporating the control program of the present invention, and VRAM as image information storage memory.
Graphics controller 9 with l0 and IBMP
Ho5t CPUII and Ho5t showing C/AT
ROM containing the hardware configuration of Bus12 and the overall control monitor program of the present invention
A BIOS 13, a backlight 13 as a rear light source for the display panel 2, an inverter 14 that supplies power thereto, and a driver power supply 15 that supplies power to the display driver 3.4 are shown.

(1) Functions of signal lines The functions of the signal lines provided between the Ho5t CPU II and the graphics controller 9 in FIG. 1 will be described below.

Ho5t Bus: Standard interface hardware bus specified by IBM, called AT Bus for IBM PC/AT machines.

The functions of each signal line provided between the FLC display unit controller 8 and the graphics controller 9 in FIG. 1 will be explained below.

1) PDO~7: Data path, 8-bit bidirectional, data transfer rate 10MH
z78 bit.

2) CLK: Transfer lock, 20MHz.

3) AH/DL: Identification signal between drive information and video information. When driving information, H
i level, Lo level for video information.

4) IHloL: Data path input/output identification signal, Hi when PDO~7 is in input mode from the graphics controller.
level. LO level when in output mode.

5) INT.

Interrupt signal from the display device side to the graphics controller.

6) FLG: Data output permission signal from the display device side to the graphics controller. High level when output is enabled.

7) Hsync: Horizontal synchronization signal 0 Data acceptance permission signal from the display device side to the graphics controller.

8) Vsync: Vertical synchronization signal 0 Synchronization signal for each display screen.

Other control signals include: 9) DR3W: A control line that controls the power supply 0N10FF of the display driver 3.4.

10) BLSW: A line that controls the inverter power supply 14 of the power supply source of the backlight 13 to 0N10FF.

First, the basic operation when display control is performed normally will be explained.

(2) Basic operation The ROM B10513 calls the functions defined in the ROM BIO313 from the video information generation side, that is, the Ho5tCPU11 side, according to a predetermined calling rule, and sometimes passes parameters necessary for realizing the function to the graphics controller 9. On the side, when called in a normal procedure, the GC is executed to implement the requested function.
PIJ (Graphics Control Central Operator) 14
or directly to the display controller 9.

Below, we will explain the specific translation or direct content and operation overview.

The graphics controller 9 transfers drive information and video information to the FLC display unit using bidirectional data buses PDO-7. However, since driving information and video information are transferred through the same transmission path, it is necessary to distinguish between the two types of information, and the signal for this identification is A.
It is H/DL. When the AH/DL signal is at Hi level, P
This indicates that the information on DO-7 is "driving information", and when it is at Lo level, it is "video information".

FLC display unit controller 8 is PDO
Drive information is extracted from the video signal with drive information transferred as 7 to 7, and processing is performed based on the drive information.On the other hand, the video information is transferred to the shift register 6 on the information electrode drive circuit side and based on the lock. Sent.

Furthermore, in this embodiment, since the drive display of the FLC display and the generation of drive information and video information in the graphics controller 9 are performed asynchronously, it is necessary to synchronize the devices when transferring display information. The signals that control this synchronization are Hsync and Vsync.
Vsync is generated in the FLC display unit controller 8 every horizontal scanning period, and Vsync is generated every vertical scanning period during refreshing, and is sent to the graphics controller 9 side. The graphics controller 9 constantly monitors these 5sync signals, and when Vsync is high
Display information when i level and Hsync is LO level (
(drive information + video information), and otherwise waits until the next transfer permission signal arrives after one transfer of display information is completed.

Figure 4 shows F from the graphics controller 9 side.
This is a timing chart of basic communication when sending display information to the controller 8 side of the LC display unit 1, and its operation will be explained.

Graphics controller 9 has Hsync set to L.
o level (and INT=Hi&Vsync=Hi&IH
10L must be Lo), the AH/DL signal is immediately set to Hi level and transfer of display information is started. The controller 8 of the FLC display unit 1 sets Hsync to Hi level during the display information transfer period. After completing a series of processes based on the transferred drive information, the controller 8 of the FLC display 1 returns to Hsync.

When the level is reached and the next display information is received, it is ready to be taken.

In Figure 5, the graphics controller 9 side is FL.
This is a timing chart of basic communication when reading display information from the controller 8 side of the C display unit 1, and its operation will be explained.

First, the graphics controller 9 uses the controller 8 of the FLC display unit 1 as drive information.
The "information read request data" that has been agreed upon in advance with
Set the signal to high to enter data input mode. At this time, data buses PDO~7 are in a high impedance state (Z) when viewed from the graphics controller 9 side.
When the controller 8 of the FLC display unit 1 recognizes the "information read request data", the IH
After confirming that the 10L line is at Hi level, put information on the data bus PDO~7 and then set the FLG signal to Hi level.
level. Graphics controller 9 is F
When it detects that the LG line becomes Hi, it reads the data on the data bus PDO~7 at that time.
Stored in the GCPU 14.

(3) Communication operation when displaying an image When displaying an image on the display, display information is sent from the graphics controller 9 side to the display side, which is the same as the communication shown in FIG. 4 above. At this time,
The driving information is scanning line address information, which is placed at positions AO to A15 in FIG. 4 and transferred to the display controller 8.

Looking at the details in more detail, the scanning line address information is extracted by the controller 8 of the FLC display unit 1, inputted to the scanning line electrode drive circuit side decoder 7 in accordance with the timing of driving the designated scanning line, Selects the specified scan line of the display. On the other hand, the video information is transferred to the information electrode drive circuit side shift register 6, and shifted in units of 8 pixels by a transfer lock (CLK). When the shift register 6 completes the shift by one scanning line in the horizontal direction, the video information for 1280 pixels is transferred to the line memory 5 attached thereto and stored for one horizontal scanning period. After one predetermined horizontal scanning period has passed and the writing operation to the display panel 2 is completed, the controller 8 of the display unit sets Hsync to the Lo level again and receives the display information of the next scanning line.

By repeating these different communication operations, writing operations and partial writing operations on the display panel screen are performed.

(4) Operation when setting display mode - When HostHo5t side dot - Setting and changing the display mode for the display device is basically H
This is based on a request from the o5t side, and basically complies with the timing chart shown in FIG. The details are described below.

■Graphics controller 9 is Ho5tCPU
When there is a display mode change request from the II side, the drive information part (when the AH/DL line is Hi level, that is, the AO-A15 in FIG. ``Display mode change request data'' is placed at the timing of ``Display mode change request data''.

■After the controller 8 of the display unit 1 recognizes the prearranged "display mode change request data", it sets the Hsync line to the LO level.

■The graphics controller 9 then inputs the "display mode number" as drive information to AO-A1 in Figure 6.
At timing 5, the signal is sent to the controller 8 of the display unit 1, and the IH10L signal is set to Hi level, thereby switching the data buses PDo to 7 to the input mode.

■The controller 8 of the display unit 1 receives the "display mode number" and determines the driving conditions of the display panel according to the display mode, the relationship between the number of physical pixels and the number of logical pixels, the color and the number of gradations, etc. or determine the size of the effective display screen and the outer frame of the display screen, and determine the relationship between the color and the number of gradations or both of the outer frame. or
To determine the format and/or timing of information transfer from the image information storage unit to the display device, and to confirm whether communication has been performed normally, the IH10L line is set to Hi level. After confirming that this is the case, the FLG signal is placed on the data buses PDO to PDO7 and set to Hi level.

■After confirming that the FLG line has become Hi level, the graphics controller 9 connects the data bus PDO to 7.
G
Stored in CPU14.

■GCPU 14 receives the received data and the previously transferred data.
Display mode number" and after confirmation, set the IH/○L signal to Lo level.

■Controller 8 of display unit 1 is IH1
After confirming that the 0L line has become Lo level, turn Hsy
Set the nc line to Lo level and wait for the next display information.

■After confirming that the HsynC line has become Lo level, the graphics controller 9 selects the normal scanning line address +
Send the video information, and if there is an error, send the "display mode conversion request data" again and start over from ■.

With the above procedure, it is possible to change the display mode and control the drive of the display panel according to each display mode.

(5) Operation when setting the display mode - When setting from the display side - For example, graphics controller 9 and display unit 1
If the controllers 8 of the display unit 1 are configured with separate power supplies, and the power of the controller 8 side of the display unit 1 is turned on after the graphics controller 9 (host side) is started up, the controller 8 of the display unit l It is not possible to know in what display mode the graphics controller 9 is already operating. In such a case, the controller 8 of the display unit 1
An INT signal is sent to the controller 9 to request the display mode to be set. The graphics controller 9 is an I from the display unit controller 8.
When the NT signal is accepted, display mode change request data is sent to the display unit controller 8.

After that, (4) Operation when display mode is set - Host
The display mode is set using the same procedure as when setting from the side.

It is also possible to issue a read request from the display device to the main device, if necessary. In this case, the display device first sends an INT signal to the graphics controller 9, as in the case of display mode setting. The graphics controller 9 receives INT from the display device side.
When the signal is accepted, display mode change data is sent to the display unit controller 8. After that, temperature information reading processing is performed in the same procedure as when a request is made from the main device side.

Next, regarding the control in the case where external noise enters the communication control line (signal line shown in (1)) or the control line is open or short-circuited during the communication control in the communication procedure described above. explain. FIG. 2 is a flowchart showing the control. The graphics controller control program in Figure 2 is in the BIOS ROM.
Built in 13. Further, the display unit controller control program is contained in a storage element in the display unit controller 8. Further, the numbers 1 to 2 of the handshake communication part in FIG. 2 match the procedure numbers when setting the display mode in (4).

The following explanation is an important point of the present invention.

The operation when setting the display mode (4) will be explained as an example. When changing the display mode in response to a request on HO3TO3, the graphic controller 9 performs (4) ■,
Communication is performed by handshaking with the display controller 8 in the order of ■, ■, etc., and the display panel is controlled. Assume that when the graphics controller 9 is in the state ■, the graphics controller 9 determines that the confirmation result of the display mode number is correct and sends image information (scanning address signal) to the display controller 8. At this time, the display unit controller 8 assumes that an external noise entered the control line PDO-7, which caused the display unit controller 8 to mistakenly receive the image information (scanning address signal) as display mode change request data. , immediately sets the Hsync signal to the "L" level through the path A in FIG. 3, and receives the display mode number from the graphics controller 9. (This display mode number is incorrect) and is waiting for the IH10L signal to go to "H" level. On the other hand, after sending the image information, the graphic controller 9 confirms that the next (sync) signal is at the "L" level, and sends the next image information to the B in Figure 2.
Continue to go around the loop.

If the (7) TgOlJT and TdOUT (7) functions in Fig. 2 are not used (when the time settings of Tg and Td are set to infinite), the display unit controller 8 will be
Waiting until the 10L signal level becomes "H" level, no image information is written to the display panel 1. Here, if a finite time is set as Td=several Looms, the display unit controller 8 switches the backlight 13 to BLSW after a certain number of Looms after the Td waiting time.
After turning off by the signal, display driver 3
．． 4, the DR3W signal sends the ○FFL and INT signals to the graphics controller 9. When the graphics controller 9 recognizes the INT signal (
Communication is restarted using the communication procedure 4), and control is restored to normal.

Further, as another example, a case (4) in which the connection of the ll10L signal line becomes open during communication control will be described. In this state, the display unit controller 8 continues to wait for the IH10L signal to go to the "H" level when the communication procedure (4) is in the state of (2). Since the graphics controller 9 cannot be set to
I'll have to keep waiting for it to reach the high level.

Here, if the time setting is Tg<Td=several 100 ms, the graphics controller 9 will skip the handshake communication after the Tg waiting time and the process will move to loop B, so the display unit controller 8
It is now ready to receive the INT signal. On the other hand, the display unit controller 8 also has a Td waiting time of 1.
After 00m5, display unit 1 is displayed in the same way as above.
The backlight 13 is turned off, the display driver 3.4 is turned off, and the INT signal is sent out. If the IH10L signal line returns to normal, normal driving operation is restored. Meanwhile, display panel 1
The driver power supply and backlight that are applied to the camera are kept in the OFF state.

The Tg and Td time settings described above are realized by software counters in each controller, but this is not possible with the GCPLJ4 or display unit controller 8.
It is also possible to have a hardware counter in addition to each, and to control the set value of that counter. At this time, connect the control line to GCP to notify that the counter value has reached the value for the set time.
All you have to do is input it to U4 and display unit controller 8.

[Effect of the invention] As explained above, the BIO3R stored in advance
The communication control program in the OM 13 and the display unit controller 8 program include means for forcibly interrupting the communication control means, means for arbitrarily changing the timing of interruption, and means for controlling again. As a result, even if a data reception malfunction occurs due to external noise or a malfunction occurs due to an open or short circuit in the communication control line, image information can be transferred normally again without the need to reset the HOST CPU. This eliminates the need to destroy the information of the HOST CPU that was being processed until a malfunction occurred due to the reset operation of the HOST CPU.

Also, until the malfunction is corrected, turn off the power to the display driver 3.4 and the backlight 13.
Since the display panel can be controlled accurately, it is possible to suppress the "burn-in" phenomenon of the display panel.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention. FIG. 2 is a control flowchart of a display unit controller used in the present invention. FIG. 3 is a characteristic diagram showing the temperature dependence of driving conditions (frequency) on temperature in the ferroelectric liquid crystal device used in the present invention. FIG. 4, FIG. 5, and FIG. 6 are timing charts of the communication system used in the present invention. FIG. 7 is a display mode diagram in the case of CRT display.

Claims (4)

[Claims] (1) a. A display panel in which scanning signal electrodes and information signal electrodes are arranged in a matrix, and a liquid crystal having memory properties and temperature dependence whose characteristics change depending on the environmental temperature is arranged between them; b. scanning signal electrodes; driving means for applying a scanning signal to the information signal electrode and applying an information signal to the information signal electrode; c. image information storage means for storing image information to be displayed on the display panel; d. display mode for image information to be displayed on the display panel. display mode storage means for storing; e. display control means for reading image information to be displayed from the image information storage means and controlling the drive means according to the display mode stored in the display mode storage means; A display device comprising: display control means for forcibly interrupting the control by the display control means and restarting the control by the display control means after the interruption. (2) The display control means has means for forcibly interrupting the control by the display control means, restarting the control by the display control means after the interruption, and arbitrarily setting the start and end of the interruption ( 1) Display device. (3) The display device according to claim 1, wherein the display control means includes means for controlling power ON and OFF after interrupting the control by the display control means. (4) The display device according to claim (1), wherein the liquid crystal is a ferroelectric liquid crystal.