JP4992140B2 - Display device driving method, display device driving system, and machine-readable storage medium - Google Patents

Description

  The present invention generally relates to display systems. More particularly, the present invention is a method and system for providing artifact-free transitions between dual display controllers.

  In a normal display system, the display control device obtains an input signal from a processor such as a central processing unit (CPU). The display controller processes the input signal and provides an output signal. The output signal then drives the display device of the display system.

  In a dual display controller system, the two display controllers are usually referred to as first and second display controllers. The first and second display control devices are individually controlled by the processor. The display device can be controlled by one of two display control devices. The control of the display device can be switched between the first and second display control devices. However, the switching of the display device control between the first and second display control devices needs to be synchronized to avoid any artifacts of the display device.

  There are various techniques for synchronizing the first and second display control devices. In the prior art known as 'Genlock', the first and second display controllers move synchronously. In addition, the outputs from the first and second display control devices are coupled to form an image on the display device. However, this output coupling and synchronization requires expensive and complex electronic systems.

  According to another prior art, the synchronization of the first and second display control devices is realized by transferring the display frame of the first display control device to the second display control device. The display frame can be modified by either of these display control devices. These display frame corrections and transfers require continuous processor intervention.

  However, the prior art introduces one or more of the following drawbacks. Since these techniques need to operate in synchronism with both display control devices, continuous intervention of the processor is required. As a result, much power is used by the display system. There are several other prior art techniques that do not require continuous processor intervention, but are complex and expensive.

  In view of the above, there is a need for a method that can synchronize the first and second display control devices to overcome the aforementioned drawbacks. Furthermore, there is a need for a method that requires minimal or no intervention of the processor. There is also a need for a method that can provide an artifact-free transition between the first and second display controllers. In addition, there is a need for a method that does not require expensive hardware and is ideal for use in a cost-sensitive display system. Moreover, there is a need for methods and systems that consume less power.

  It is an object of the present invention to provide a method, system and computer program product for driving a display device by a display system.

  It is another object of the present invention to provide a method, system and computer program product for driving a display device without the continuous intervention of a processor.

  Another object of the present invention is to provide a method, system and computer program product for driving a display device with a display system with low power consumption.

  It is a further object of the present invention to provide a method for control transition between the first and second display control devices such that an artifact-free display is provided on the display device.

  Yet another object of the present invention is to eliminate the need for expensive and dedicated hardware, thereby making it ideal for use in applications where cost and power are considered.

In order to achieve the foregoing object, various embodiments of the present invention provide a first table in a display system.
A display control device or a second display control device provides a method and apparatus for driving a display device. The display system includes a processor, a first display control device, a second display control device, a frame buffer for the first display control device, a frame buffer for the second display control device, and a display device. . The processor sends a plurality of display frames to the first display control device. The first display control device turns a plurality of display frames to the second display control device. The second display control device can refresh the display device with a plurality of input display frames without performing any operation, or can refresh the display device after performing one or more operations.

The first display control device drives the display device when the processor writes a plurality of display frames in the frame buffer of the first display control device. However, if no new frame is written to the frame buffer of the first display controller, the second display controller records a plurality of display frames in the frame buffer of the second display controller. Immediately after recording the display frame, the second display control device changes the video timing of the first display control device to the video timing of the second display control device. The transition of the video timing is performed during the trailing edge of the vertical synchronization (V-Sync) pulse, that is, during the vertical blanking period. Following the video timing transition,
The second display control device drives the display system. The processor and the first display control device are the second
When the display control device drives the display device, it can be switched to the non-functional mode. Note that the above
The video timing is, for example, that the first and second display control devices use a clock to switch to the display device.
This is the timing for generating the display output.

The second display controller continues to drive the display device even if the processor does not write any frames into the frame buffer of the first display controller. The second display control device can be switched to a non-functional state when the display device is refreshed with the same display frame for a predetermined number of times. Each time a frame is written to the frame buffer of the second display controller
Control is switched back from the second display controller to the first display controller at the trailing edge of the V-Sync pulse. In one embodiment of the present invention, the second display controller can be activated from a non-functional mode each time the processor receives input from several input devices.

The second display control device performs all transitions such as control switching between the first and second display control devices at the trailing edge of the V-Sync pulse. This ensures that a complete frame is recorded before switching control resulting in an artifact-free display. Since the transfer and recording of a plurality of display frames and the switching of control are performed automatically, the need for continuous intervention of the processor is eliminated. The processor, the first display controller, and the second display controller can be switched to a low power mode to maximize power savings. Thus, embodiments of the present invention achieve the objective of providing a low power consumption method and system that is not expensive to refresh display devices.

  This application was filed on March 23, 2006, US provisional application serial number US60 / 785065 entitled "Artifact-Free Transition Between Dual Display Controllers" and March 9, 2007. And claims the priority of US Provisional Patent Application No. US60 / 906122 entitled 'Artifact-Free Transition Between Dual Display Controllers', which is incorporated herein by reference for all purposes. Is done.

  This application is also incorporated herein for all purposes by US provisional patent application number US 60/785066, filed March 23, 2006, entitled "Self-Refresh Display Control Device for Portable Control Devices". The

  Various embodiments of the present invention will now be described with reference to the accompanying drawings, which are provided to illustrate the same elements without limiting the invention and like designations.

An embodiment of the present invention provides a first display control device or a second display control device in a display system.
There a method for driving a display device to provide a system and a computer program product, there is a display system computer-related device. The display system includes a processor, a first display control device, a second display control device, a frame buffer of the first display control device, a frame buffer of the second display control device, and a display device. The display device
It can be driven by either the first display control device or the second display control device. When a plurality of identical frames are written in the frame buffer of the first display control device, the control of the display device is switched from the first display control device to the second display control device. Input vertical synchronization (V-Sy
nc) Following the trailing edge of the pulse, the second display control device changes the control of the display device from the first display control device to the second display control device. The display control is switched during a vertical blanking period that prevents display artifacts during transition.

  Alternatively, in another embodiment of the present invention, when a plurality of new frames are written to the frame buffer of the first display controller, display device control is transferred from the second display controller to the first display. Switch to the control device. The switching of the display device control is performed during the vertical blanking period.

  Referring now particularly to the drawings by reference number, FIG. 1 is a schematic diagram of an arrangement 100 in which various embodiments of the present invention may be implemented. Configuration 100 includes several computer-related devices. Further, typical computer-related devices include a processor 102, a first display control device 104, a second display control device 106 and a display device 108. The processor 102 controls the first and second display control devices 104 and 106, respectively. The first display control device 104 can be integrated with the processor 102. Alternatively, the first display controller 104 can function separately from the processor 102. Examples of computer-related devices include, but are not limited to, laptop computers, palmtop computers, desktop computers, calculators, cell phones and personal digital assistants (PDAs). Examples of display device 108 include, but are not limited to, a liquid crystal display (LCD) screen, a cathode ray tube (CRT) monitor, and a plasma screen. The processor 102 may be a normal central processing unit (CPU) in a computer related device. Examples of the first display controller 104 and the second display controller 106 include, but are not limited to, a conventional video graphic array (VGA) or other controller and an application specific integrated controller (ASIC).

  In one embodiment of the present invention, the second display controller 106 preferably allows the use of six interfaces. The first interface is a thin film transistor (TFT) input port and is designed to receive a plurality of display frames from the first display controller 104. The second interface is a double-edge transistor-transistor logic (DETTL) LCD output port that connects directly to a TFT panel matrix driver for multiple integrated circuits (ICs) and supports LCD display output on suitable TFT display devices. To do. The third interface is a serial port of a bidirectional system management bus (SMBUS). SMBUS is at least 100 KHz and is connected to the internal set-up and configuration registers of the second display controller 106. The SMBUS port has the ability to read and write to multiple registers in the internal setup and configuration of the second display controller 106. The fourth interface is a collection of one or more input / output pin interfaces for managing the switching between which the time between the first display controller 104 and the second display controller 106 is determined. The fifth interface is a synchronous dynamic read / write storage (SDRAM) interface port, which communicates with a low power SDRAM for storing one complete display frame. The second display control device 106 performs autonomous refresh of the display device 108 by acquiring a plurality of display frames from the SDRAM. The sixth interface is directly connected to a 14.31818 MHz lens. The crystalline lens is supported by an on-chip oscillator and supplies an independent pixel clock for display refresh regardless of the state of the display input port. An independent pixel clock for display operates at 50 Hz, but is synthesized at 57.27272 MHz. In addition, an independent pixel clock provides interface timing for the attached SDRAM frame buffer.

  In accordance with another embodiment of the present invention, the second display controller 106 includes a seventh interface having a number of pins connected to the processor 102. The plurality of pins activates the second display controller 106 from the non-functional mode when the processor 102 receives input from several input devices.

  In addition, the second display control device 106 has various capabilities. The second display controller 106 allows the use of 'color swizzling' and allows the display device 108 to function as a conventional 24-bit panel. Color swizzling is a method for reducing the number of bits, which represents each pixel without any visual difference in display quality. Further, the second display control device 106 enables the use of an anti-aliasing function. The anti-aliasing function improves the text display on the display device 108. In addition, the second display controller 106 provides black and white mode support for converting pixel-addressable automatic colors to gray scale.

  In addition, the second display control device 106 provides inefficiency for incoming multiple display frames in the passing mode. In the passing mode, the second display control device 106 provides the first display control device 104 with a plurality of display frames without performing any operation. As a result, a single LCD timing controller chip and an automatic fly-by mode are emulated. The automatic fly-by mode prevents unnecessary writes to the SDRAM frame buffer, thereby reducing the overall power consumed by the display system. This minimizes power consumption. Furthermore, the second display controller allows the use of a conventional red / green / blue (RGB) DETTL panel for efficient debugging. The second display controller 106 also includes a self-test function for production line testing. The second display control device 106 can be constructed so as not to operate a plurality of input display frames by operating the passing mode. This feature of the second display controller 106 can be used to test the second display controller 106 during manufacture. The above-described features of the second display control device 106 will be described with reference to FIG.

  FIG. 2 illustrates a schematic diagram of a plurality of system elements in a display system 200 according to one embodiment of the invention. The first display controller 104 includes a frame buffer 202 and several clocks. For simplification of the drawing, the first display control device 104 is shown to include a clock 206. Further, the first display control device includes one or more registers. In addition, the second display controller 106 includes a frame buffer 204 and several clocks. For simplification of the drawing, the second display control device 106 is shown to include a clock 208. Further, the second display control device includes a first pin 210, a second pin 212, a third pin 214, a fourth pin 216, a fifth pin 218, and one or more registers.

  The processor 102 supplies a plurality of display frames to the first display control device 104 and the second display control device 106 in order to refresh the display device 108. The multiple display frames include several display frames for refreshing the display device 108. The display data includes one or more frames displayed by the display device 108. The display frame is data for each pixel of an image displayed on the display device 108. The frame buffer 202 and the frame buffer 204 store a plurality of display frames for refreshing the display device 108. The display device 108 can be driven by one of the first display control device 104 and the second display control device 106. The plurality of pins are used to manage the switching of control of the display device 108 between the display control devices 104 and 106. The processor 102 supplies a plurality of display frames to the first display control device 104. The first display controller 104 refreshes the display device 108 when the processor 102 writes multiple display frames to the frame buffer 202. When the processor 106 does not write to the frame buffer 202, control of the display device 108 is switched to the second display control device 106. When the processor 102 writes to the frame buffer 202 again, control is switched back to the first display controller 104. A shift in control of the display device 108 between the first display control device 104 and the second display control device 106 may cause display artifacts. A method for switching control of the display device 108 without causing any artifact will be described in detail with reference to FIGS.

  FIG. 3 is a flowchart of a method for driving the display device 108 according to an embodiment of the present invention. In step 302, display data is received by the first display controller 104. The first display control device 104 receives display data from the processor 102. Display data is stored in the frame buffer 202.

In step 304, the control of the display device 108 is switched between the first display control device 104 and the second display control device 106. The control of the display device is the first in the blanking period.
It is switched between the display control device 104 and the second display control device 106. The blanking period is a period between the trailing edge of the vertical synchronization (V-Sync) or horizontal synchronization (H-Sync) pulse and the beginning of the next active scan line. A scanning line represents pixel data of one line of an image displayed by the display device 108. The blanking period is the vertical blanking period, and switching is
Occurs at the end of the input vertical sync (V-Sync) pulse.

  In one embodiment, when the first display controller 104 drives the display device 108 and no display data is written to the frame buffer 202, control of the display device 108 is transferred from the first display controller 104 to the second display. The control device 106 is switched to. In another embodiment of the present invention, when the second display controller 106 drives the display device 108 and multiple new display frames are written to the frame buffer 202, the control of the display device 108 is controlled by the second display controller 106. To the first display control device 104. At step 306, the display device 108 is refreshed after the control is switched. A method for switching the control of the display device 108 between the first display control device 104 and the second display control device 106 will be described in more detail with reference to FIGS.

  4A and 4B are a flow diagram of a method for switching control of the display device 108 from the first display control device 104 to the second display control device 106 according to one embodiment of the invention. The first display controller 104 drives the display device 108 when the frame buffer 202 is written sequentially with multiple new display frames. The first display control device 104 that drives the display device 108 includes transmitting a display frame to the second display control device 106. The second display controller 106 records the display frame in the frame buffer 204. Thereafter, the second display controller 106 refreshes the display device 108 by obtaining the display frame from the frame buffer 204. The second display control device 106 can make one or more changes to the display frame, such as changing the frequency of a plurality of display outputs while performing the color swizzling and the color anti-aliasing function. Thereafter, the second display control device 106 refreshes the display device 108.

  In accordance with another embodiment of the present invention, the second display controller 106 can make changes to the display frame and refresh the display 108 without recording the display frame in the frame buffer 204.

In step 402, the first display control device 104 drives the display device 108. Step 4
At 04, it is determined whether multiple new display frames are written to the frame buffer 202. If multiple new display frames are written to the frame buffer 202,
The first display control device 104 continues to drive the display device 108 in step 402. Alternatively, if no new frame is written to the frame buffer 202, then, at step 406, the first pin 210 is set low. At step 408, a new frame is recorded in the frame buffer 204. After that, the second display control device 106 becomes V
-Perform a display load cycle at the end of the Sync pulse. The process of performing a display load cycle includes recording a display frame in the frame buffer 204. Recording the display frame in the frame buffer 204 starts at the trailing edge of the input V-Sync pulse and ends at the trailing edge of the next V-Sync pulse. The trailing edge of the V-Sync pulse indicates the end of the current display frame and the input of a new display frame. The second display controller 106 starts recording pixel data from the first scanning line to the trailing edge of the next V-Sync pulse. The trailing edge of the input V-Sync pulse or the display frame timing of the second display controller 106 is indicated to the processor 102 by the second pin 212. The second pin 202 is kept low from the first output scan line to the trailing edge of the V-Sync pulse.

  The second pin 212 is maintained in a high state during the vertical blanking period. The processor 102 uses the state of the second pin 212 to synchronize the control switching of the display device 108 between the first display controller 104 and the second display controller 106 during the vertical blanking period. After the entire frame is recorded in the frame buffer 204, the second display control device 106 starts control switching from the first display control device 104 to itself.

In step 410, the second display control device 106 shifts some video timings of the first display control device 104 to some video timings of the second display control device 106. In accordance with one embodiment of the present invention, the transition of the video timing of the first display controller 104 to the second display controller 106 is performed near the trailing edge of the V-Sync pulse. After the V-Sync pulse
Near the edge is the time interval from the start of the V-Sync pulse to the end of the subsequent vertical blanking period. In addition, the second display control device 106 starts from the clock 206 to the clock 2
Change to 08. The clock 206 and the clock 208 may have the same frequency. In addition,
The clock 208 may operate asynchronously with the clock 206. In accordance with one embodiment of the present invention, a “first in first out” (FIFO) can be used to change the time of multiple display frames sent by the first display controller 104 to match the video timing of the second display controller 106. is there. In another embodiment of the present invention, the first and second display control devices 104 and 1
The transition of the video timing of 06 is performed during the blanking period of the horizontal synchronization (H-Sync) pulse. According to another embodiment of the present invention, synchronization of multiple display frames can be performed without interruption because it can be performed by using on / off freely phase-locked feedback (PLL).

  In step 412, the second display controller 106 resets some registers of the first display controller 104 and some registers of the second display controller 106. In step 414, the second display controller 106 switches the frame buffer 204 from the write mode to the read mode. In one embodiment of the invention, the switching of the frame buffer 204 from write mode to read mode is performed simultaneously with the video timing transition. Following the transition of the video timing, the second display controller 106 uses a plurality of registers and a clock 208 to generate a display output. The display output includes a display frame, which is obtained from the frame buffer 204 with or without manipulation. The plurality of registers and clock 208 start operation at the beginning of the next active scan line following the transition of control of display device 108.

  In step 416, the control of the display device 108 is switched from the first display control device 104 to the second display control device 106. Thereafter, the second display control device 106 starts refreshing the display device 108 from the beginning of the next active scanning line. The second display control device 106 autonomously refreshes the display device 108 with the display frame in the frame buffer 204. In step 418, the first display controller 104 and the processor 102 are switched to the non-functional mode. In accordance with another embodiment of the present invention, at step 418, the first display controller 104 can switch to the non-functional mode as long as the processor 102 remains in the non-functional mode.

  The second display control device 106 can be switched to the non-functional mode when the second display control device 106 refreshes the display device 108 with the same display frame for a predetermined number of times. The predetermined number of times for refreshing the display device 108 is stored in a plurality of registers of the second display control device 106.

FIG. 5 illustrates the second display control device 106 to the first display control device 1 according to an embodiment of the present invention.
4 illustrates a flow diagram of a method for control switching of display device 108 to 04. Step 502
Thus, the second display control device 106 drives the display device 108. At step 504, it is determined whether multiple new display frames are written to the frame buffer 202. If no new multiple display frame is written to the frame buffer 202, the second display controller continues to drive the display device 108 at step 502. Alternatively, if a new display frame is written to frame buffer 202, then at step 506, the first
Pin 210 is set high. The high state of the first pin 210 indicates that the first display control device 1
04 represents a recording state with high power . The recording process is to load the display frame from the frame buffer 202 and store it in the frame buffer 204 by the second display controller 106.

In step 508, secondary display controller 106 performs a transition of a plurality video timing of the plurality video timing and the first display controller 104 of the secondary display controller 106. Furthermore, the secondary display controller 106 performs transition of clock 208 and the clock 20 6. In one embodiment of the invention, the clock transition is performed near the trailing edge of the input V-Sync pulse. Alternatively,
In another embodiment of the invention, the clock transition occurs during the blanking period of the H-Sync pulse.

If the first display controller 104 is in the low state, the clock 206, the multiple video timings, and the multiple registers of the first display controller 104 are reinitialized by the processor 102.
Furthermore, the processor 102 simultaneously reinitializes the clock 206 with the clock 208. In accordance with another embodiment of the present invention, the multiple video timing, clock 206 and multiple registers of the first display controller 104 can be reinitialized with support for interrupts provided by the third pin 214. The third pin 214 generates a scan line interrupt at the beginning of a preselected scan line
It is possible to make. The second display controller 106 can be programmed to perform several functions depending on the type of scan line interrupt that is generated . Of scan line interrupts generated
The type is presented to the processor 102 by a fourth pin 216. In accordance with another embodiment of the present invention, the second display controller 106 uses several pins to present the type of scan line interrupt that is generated . The second display control device 106, after re-initializing the first display control device 104,
Change control.

  In step 510, the control of the display device 108 is switched to the first display control device 104. Thereafter, the first display control device 104 drives the display device 108 with a plurality of display frames written into the frame buffer 202 by the processor 102. From the next active scan line, the multiple registers and clock 206 of the first display controller 104 generate a display output.

  FIG. 6 is a flowchart of a method for activating the second display controller 106 from a non-functional mode according to an embodiment of the present invention. At step 602, the second display controller 106 remains in the non-functional mode. In step 604, it is determined whether the processor 102 has received input from a plurality of input devices associated with the processor 102. The plurality of input devices may be, for example, a keyboard, a touch pad, a wireless event, a cursor pad, or a mouse. If processor 102 does not receive an input, then at step 602, second display controller 106 remains in the non-functional mode. However, if the processor 102 receives an input, then at step 606, the fifth pin 218 is set to a high state and the second display controller 106 is activated from the non-functional mode. The fifth pin 218 is set to a high state by the processor 102. When the fifth pin 218 is set to the high state and the second display controller 106 is in the functional mode, the second display controller 106 resets the plurality of display timeout registers. The plurality of display time-out registers store the number of times that the display frame can be refreshed by the second display controller 106 and thereafter the second display controller 106 can switch to the non-functional mode. In accordance with another embodiment of the present invention, the second display controller 106 is activated from a non-functional mode by embedded software in the processor 102 each time the processor 102 receives input from a plurality of input devices.

  At step 608, it is determined whether the processor 102 has updated the frame buffer 202 with a new display frame. If the processor 102 does not update the new frame, then at step 614, the second display controller 106 begins to autonomously refresh the display device 108 with the display frame in the frame buffer 204. However, if the processor 102 updates the frame buffer 202 with a new display frame, then the second display controller 106 activates the display device 108 and resets the display blanking registers to display the display. Delete. A plurality of display blanking registers controls the function of the display device 108. When multiple display blanking registers are activated, the second display controller 106 shows a blank display device 108. The normal function of the display device 108 is restored by resetting the plurality of display blanking registers. At step 610, the third pin 214 generates an interrupt that instructs the second display controller 106 to perform a display load cycle. At step 612, the second display controller 106 performs a display load cycle. Thereafter, in step 614, the second display controller autonomously begins to refresh the display device 108. The state of the plurality of system elements of the display system 200 with respect to the method steps and times in which there is an important part in driving the display device 108 will be described in detail with reference to FIGS.

  FIG. 7 is a timeline graph for switching control of the display device 108 from the first display control device 104 to the second display control device 106 according to one embodiment of the present invention. FIG. 7 illustrates a process of switching the control of the display device 108 performed during the vertical blanking period. Further, the figure represents the state of various system elements of display system 200 over time. 7 includes a first display control device 104, a second display control device 106, a frame buffer 204, a clock 206, a first pin 210, and a second pin 212. The display system 200 illustrated in FIG. In FIG. 7, time is represented on the x-axis and the state of multiple system elements is represented on the y-axis.

  FIG. 8 is a timeline graph for switching control of the display device 108 from the second display control device 106 to the first display control device 104 according to one embodiment of the present invention. FIG. 8 illustrates a process of switching the control of the display device 108 performed during the vertical blanking period. Further, FIG. 8 represents the state of various system elements of the display system 200 over time. A plurality of system elements of the display system 200 illustrated in FIG. 8 includes a first display control device 104, a second display control device 106, a clock 206, a first pin 210, a second pin 212, and a third pin 214. In FIG. 8, time is represented on the x-axis and the state of multiple system elements is represented on the y-axis.

  FIG. 9 is a timeline graph for activating the second display controller 106 from the non-functional mode, according to one embodiment of the invention. FIG. 9 represents the state of various elements of the display system 200 over time. The plurality of system elements of the display system 200 include a first display controller 104, a second display controller 106, a frame buffer 202, a frame buffer 204, a third pin 214 and a fifth pin 218. In FIG. 9, time is represented on the x-axis and the state of multiple system elements is represented on the y-axis.

  As an example, the plurality of display control devices may be implemented by the same kind of a plurality of application specific integrated circuits (ASICs), a plurality of programmable controllers (PLCs), and a plurality of portable devices. In view of the above description, industrial-based implementation items of the present invention (second display controller 106) according to one embodiment are included here. These items include various hardware implementation items, which include various processor, IC, pin and register construction level items. The description will be understood by one of ordinary skill in the art and will assist in practicing the invention without undue experimentation.

Register definition of the second display controller 106 Register Index Default ID and revision of the second display controller 106 DC01H
Display mode of second display controller 106 1 0012H
Horizontal resolution 2 0458H (1200 decimal)
Total number of horizontal characters 3 04E8H (1256 decimal)
Horizontal synchronization 4 1808H (24, 8 decimal)
Vertical resolution 5 0340H (900 decimal)
Number of vertical display lines 6 0390H (912 decimal)
Vertical synchronization 7 0403H (4, 3 decimal)
Display timeout 8 FFFFH
Scan line interrupt 9 0000H
Backlight brightness 10 XXXFH
Spare 11-127

User I / O Pin Definition of Second Display Controller 106 ASIC Pinout-1M (512K × 16) SDRAM Configuration of Second Display Controller 106 Geode (TM) Display Interface Pin Group Geode (TM) Pixel Clock GFDOTCLK 1
Geode (TM) red data GFRDAT0-5 6
Geode (TM) Green Data GFGDAT0-6 7
Geode (TM) Blue Data GFBDAT0-5 6
Geode (TM) VSync GFVSYNC 1
Geode (TM) HSync GFHSYNC 1
Geode (TM) FP_LDE GFP_LDE 1

512K × 16 SDRAM interface pin group FBRAM data FBD0-15 16
FBRAM address FBDA0-10 11
FB column address strobe FBCAS / 1
FB row address strobe FBRAS / 1
FB data mask FBDM0-1 2
FBRAM chip select FBCS / 1
RBRAM writing operation FBWE / 1
FBRAM clock FBCLK 1
FBRAM clock operation FBCLKE 1

Second display control device 106 self-refreshing crystal display XTAL in DCONXI 1
Display XTAL out DCONXO 1

System interface pin group System reset RESET 1
EC power on request ECPWRRQST 1
Interrupt output of second display controller 106 DCONIRG / 1
Display load command request of second display controller 106 DCONLOAD 1
Status pin DCONSTAT 2 of the second display controller 106
Blanking state of the second display controller 106 DCONBLNK 1
Register I / O • SMB clock DCONSMBCLK 1 of the second display controller 106
Register I / O / SMB data of the second display controller 106 DCONSMBDATA 1

DETTL / Panel interface pin group Panel pixel data 0 DO00-DO01 3
Panel pixel data 1 DO10-DO11 3
Panel pixel data 2 DO20-DO21 3
Source dot clock SCLK 1
Data interface polarity control REV1-2 2
Graphic output operation (gate driver operation) GOE 1
-INV 1
-CPV 1
-STV 1
-FSTH 1
-BSTH 1
-TP 1
LCD backlight operation BACKLIGHT 1
Display backlight control (PWM) DBC 1
Driver polarity signal 1 POL1 1
LCD VDD operation VDDEN 1
Run-in / Test mode AGMODE 1
Color / monochrome panel bias ・ Select COLMODE 1
General user I / O 94

  The minimum duty cycle for ECPWRRQST active is less than 100 ns (this pin does not need to be debounced or filtered).

  Various embodiments of the present invention comprise a display system, which includes a display device, a processor, a first display control device, a second display control device, and a plurality of clocks of a first and second display control device, a plurality of frames, Contains a buffer. Further, the second display control device includes several pins.

Various embodiments of the present invention ensure that an artifact-free display is provided in the display system. The display is provided to the display device after transition between the first display control device and the second display control device in the display system. The transition takes place near the trailing edge of the vertical sync (V-Sync) pulse, ie during the vertical blanking period, thereby ensuring an artifact-free display.

  The second display control device can autonomously refresh the display device regardless of the processor and the first display control device. The autonomous refresh of the display eliminates the need for continuous processor intervention.

  The first and second display controllers and the display device can be turned off during extended non-functions, resulting in considerable savings in power consumption by the display system.

  The various embodiments of the present invention do not require dedicated and expensive hardware, and thus provide an ideal system for use of electronic devices in applications that consider power and cost.

  While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the invention as set forth in the claims.

It is a schematic diagram of the structure which implements various embodiment of this invention. 1 is a schematic diagram of system elements in a display system, according to one embodiment of the invention. FIG. 3 is a flowchart of a method for driving a display device according to an embodiment of the present invention; 4 is a flowchart of a method for switching control of a display device from a first display control device to a second display control device, according to an embodiment of the present invention. 4 is a flowchart of a method for switching control of a display device from a first display control device to a second display control device, according to an embodiment of the present invention. 3 is a flow diagram of a method for switching control of a display device from a second display control device to a first display control device, according to an embodiment of the present invention. 4 is a flowchart for activating a second display control device from a non-functional mode according to an embodiment of the present invention. 4 is a timeline graph for switching the display device control from the first display control device to the second display control device according to an embodiment of the present invention. 6 is a timeline graph for switching the display device control from the second display control device to the first display control device according to an embodiment of the present invention; 6 is a timeline graph for activating a second display control device from a non-functional mode according to an embodiment of the present invention.

Explanation of symbols

102 processor 104 first display control device 106 second display control device 108 display device 202,204 frame buffer 210 first pin 212 second pin 214 third pin 216 fourth pin 218 fifth pin

Claims (22)

In a display system comprising a display device, a first display control device, a second display control device, and a processor, a method for driving the display device by the first display control device or the second display control device. There,
Receiving display data from the processor at the first display controller;
Transmitting display data of the first display control device to the second display control device;
At the trailing edge of the V-sync pulse that is input vertical synchronization, the first display controller and the second
Switching control of the display device to and from the display control device;
Refreshing the display device with the second display control device at a clock separate from the processor and the first display control device. 2. The display device driving device according to claim 1, further comprising the step of setting a first pin of the second display control device to a low state when no new frame is written to the frame buffer of the first display control device. Method. The step of setting the first pin to the low state includes the step of performing a display load cycle, the step of performing the display load cycle in the frame buffer of the second display controller. 3. The method for driving a display device according to claim 2, comprising storing a frame transmitted from the controller, and storing the frame is started at a trailing edge of the input V-sync pulse. The step of switching control of the display device comprises one or more new frames being the first.
Setting the first pin of the second display control device to a high state when written to the frame buffer of the display control device, the high state of the first pin being a high state of the first display control device. The display device driving method according to claim 1, wherein the recording state is expressed by electric power. The step of switching the control of the display device comprises: video timing for generating display output on one or more display devices of the first display control device; and one or more display devices of the second display control device. The display device driving method according to claim 1, further comprising a step of performing transition between the first display control device and the second display control device with respect to video timing for generating a display output. The step of performing the transition includes synchronously reinitializing the one or more video timings of the first display control device and the second display control device, wherein the one or more video timings are 6. The method for driving a display device according to claim 5, wherein re-initialization is performed synchronously during a blanking period. The step of switching the control of the display device further includes the step of switching the frame buffer of the second display control device from the writing mode to the reading mode when switching the control from the first display control device to the second display control device. The method for driving a display device according to claim 5. The step of switching control of the display device further includes the step of transmitting frame timing from the second display control device to the processor when switching control from the first display control device to the second display control device;
The communicating step comprises:
Setting the second pin of the second display controller to a low state at a predetermined time before the V-sync pulse;
Setting the second pin high during a blanking period, which is the period between the trailing edge of the V-sync pulse and the beginning of a new active scan line,
6. The processor uses the state of the second pin to synchronize control switching of the display device between the first display control device and the second display control device during a blanking period. The method for driving a display device as described. 6. The step of switching control of the display device further includes driving the second display control device into a non-functional mode based on the value of one or more registers of the second display control device. The method for driving a display device as described. Refreshing the display device includes activating the second display control device from a non-functional mode when the second display control device receives input from one or more input devices. The method for driving a display device according to claim 1, wherein the method is started by the processor. Refreshing the display device comprises:
Setting the fifth pin of the second display control device from a low state to a high state when the processor receives input from one or more input devices;
The method for driving a display device according to claim 1, further comprising: starting the second display control device from a non-functional mode. 2. The refreshing of the display device includes initiating one or more video outputs when one or more new multiple frames are written to the frame buffer of the first display controller. Display device driving method. 2. The step of refreshing the display device includes driving the display device by the second display controller when no new frames are written to the frame buffer of the first display controller. Display device driving method. A display system including a display device, a first display control device, a second display control device, and a processor, wherein the first display control device or the second display control device drives the display device. There,
Means for receiving display data from the processor at the first display controller;
Means for transmitting display data of the first display control device to the second display control device;
Means for switching control of the display device between the first display control device and the second display control device at the trailing edge of the V-sync pulse that is input vertical synchronization;
And a means for refreshing the display device by the second display control device at a clock separate from the processor and the first display control device. Machine-readable storage comprising one or more machine-executable instructions for programming a processor in a display system including a display device, a first display controller, a second display controller, and a processor to perform the method A medium,
The method
Receiving display data from the processor at the first display controller in the display system;
Transmitting display data of the first display control device to the second display control device in the display system;
Switching control of the display device between the first display controller and the second display controller in the display system at the trailing edge of the V-sync pulse that is input vertical synchronization;
A machine-readable storage medium comprising: refreshing the display device by the second display control device at a clock separate from the processor and the first display control device. A display system including a display device, a first display control device, a second display control device, and a processor, wherein the first display control device or the second display control device drives the display device. There,
Receiving display data from the processor at the first display controller;
Receiving display data from the first display control device at the second display control device;
At the trailing edge of the V-sync pulse that is input vertical synchronization, the first display controller and the second
Switch control of the display device to and from the display control device,
A display device driving system for refreshing the display device by the second display control device at a clock separate from the processor and the first display control device. 17. The display device driving system according to claim 16, wherein the system stores a frame in a frame buffer of the second display control device at a trailing edge of a V-sync pulse that is an input vertical synchronization. The system includes: video timing for generating display output on one or more display devices of the first display control device; and video for generating display output on one or more display devices of the second display control device. The display device drive system according to claim 16, wherein a transition is made between the first display control device and the second display control device with respect to timing. The system synchronizes and reinitializes the one or more video timings of the first display control device and the second display control device, the one or more video timings during a blanking period. 19. The display device drive system according to claim 18, wherein the display device drive system is reinitialized in synchronization with the display device. The system activates the second display controller from a non-functional mode, and the second display controller is activated by the processor when the processor receives input from one or more input devices. Item 17. A display device driving system according to Item 16. 17. The first display controller starts one or more video outputs when one or more new multiple frames are written to the frame buffer of the first display controller.
The display device driving system according to claim . 17. The display device driving system according to claim 16, wherein the second display control device includes driving the display device when no new frame is written to the frame buffer of the first display control device.

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