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JPH03273620A - Heat treating method of semiconductor wafer - Google Patents

Heat treating method of semiconductor wafer

Info

Publication number
JPH03273620A
JPH03273620A JP191891A JP191891A JPH03273620A JP H03273620 A JPH03273620 A JP H03273620A JP 191891 A JP191891 A JP 191891A JP 191891 A JP191891 A JP 191891A JP H03273620 A JPH03273620 A JP H03273620A
Authority
JP
Japan
Prior art keywords
jig
wafer
furnace
holding
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP191891A
Other languages
Japanese (ja)
Inventor
Norimasa Miyamoto
宮本 憲昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP191891A priority Critical patent/JPH03273620A/en
Publication of JPH03273620A publication Critical patent/JPH03273620A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve space efficiency and to prevent the entrainment of contamination sources when a jig is inserted into a furnace by engaging a plurality of holding jigs with grooves, holding semiconductor wafers at a plurality of places at the peripheral part, inserting the jig in the reverse direction with respect to the introducing direction of gas into a furnace tube, and performing heat treatment such as impurity diffusion. CONSTITUTION:Many semiconductor wafers 11 are aligned in a holding jig 12 comprising a pair of upper and lower holding members 12A and 12B at an approximately equal interval. A cylindrical part having the inner diameter corresponding to the outer diameter of the wafer when they are overlapped is formed of total of six rod-shaped parts 12X at every three pieces. A groove having the width corresponding to the thickness of the wafer is cut at a part which is engaged with the wafer 11 in each rod-shaped part 12X. Many wafers 11 in the wafer holding jig 12 are inserted into a vertical diffusing furnace (heat treating furnace) 13 by rotating the jig 12 and holding the jig with a jig holder 16. The furnace 13 is composed of a quartz pipes which are extending in the vertical direction in the approximately horizontal state. In diffusing, gas 15 is introduced into the furnace 13, and the wafers 11 are heated to specified temperature with a heater 14. Meanwhile, the wafer holding jig 12 is held under the non-contact state with the inner wall of the furnace by using the jig holder 16. The jig holder 16 is vertically moved and rotated by utilizing the non-contact state.

Description

【発明の詳細な説明】[Detailed description of the invention]

[0001] [0001]

【産業上の利用分野】[Industrial application field]

この発明は半導体ウェハに不純物拡散等の加熱処理を施
す方法に関する。 [0002]
The present invention relates to a method of subjecting a semiconductor wafer to heat treatment such as impurity diffusion. [0002]

【従来の技術】[Conventional technology]

従来、半導体ウェハにアクセプタ不純物あるいはドナー
不純物などを拡散するにあたっては、図5に示すように
石英又はシリコン製の治具2に多数のウェハ1を直立さ
せて並列的に保持し、図6に示すような横型拡散炉3に
挿入するのが一般的であり、拡散炉3は、ヒータ4を有
すると共に、ウェハ挿入用開口部とは反対側端から不純
物を含むキャリアガス(02,H2,N2等)5を流入
させるようになっているのが普通であった。その横型拡
散炉は、例えば特開昭49−104570号に開示され
ている。 [0003]
Conventionally, when diffusing acceptor impurities or donor impurities into semiconductor wafers, a large number of wafers 1 are held upright and parallel in a jig 2 made of quartz or silicon as shown in FIG. The wafer is generally inserted into a horizontal diffusion furnace 3, which has a heater 4 and a carrier gas (02, H2, N2, etc.) containing impurities from the end opposite to the wafer insertion opening. ) 5 was normally allowed to flow in. The horizontal diffusion furnace is disclosed, for example, in Japanese Patent Application Laid-open No. 104570/1983. [0003]

【発明が解決しようとする課題】[Problem to be solved by the invention]

しかし、このような従来技術によれば、ウェハを炉内に
挿入するときに、炉体内壁とウェハ治具とが接触し異物
が発生しがちである。又、炉内の温度分布が不均一性で
あることと相俟ってガスの流速分布の不均一性あるいは
乱流の発生などによってウェハ内での又はウェハ間での
素子特性に相当のばらつきが生ずる欠点がある。 [0004] すなわち、ウェハを炉体内に保持するときに、ウェハ治
具が炉体内壁と接触するので、この接触面からの熱伝達
によってウェハ治具およびウェハの温度分布に差が生じ
たり、炉体内に導入された反応ガス密度が重力の影響で
炉体内の上下で差が生じ、一枚のウェハ内でバラツキが
生じたりする等の問題がある。 [0005] 又、ウェハを一枚ずつ治具に立てかげる必要があり自動
化に不向きである。又、装置の占有スペースがかなり大
きいという欠点もある。 [0006] 本発明の目的は上記した欠点を除去した新規な半導体ウ
ェハに対する熱処理方法を提供することにある。そして
、特に装置の複雑化を避けると共に炉管内への汚染源の
巻き込みを解消させる熱処理方法を提供するものである
。 [0007]
However, according to such conventional techniques, when a wafer is inserted into a furnace, the inner wall of the furnace body and the wafer jig tend to come into contact with each other, resulting in the generation of foreign matter. Additionally, in combination with the non-uniform temperature distribution in the furnace, non-uniform gas flow velocity distribution or turbulence can cause considerable variation in device characteristics within a wafer or between wafers. There are drawbacks that arise. [0004] That is, when the wafer is held in the furnace, the wafer jig comes into contact with the wall of the furnace, so heat transfer from this contact surface causes a difference in temperature distribution between the wafer jig and the wafer, and the furnace There is a problem in that the density of the reactant gas introduced into the body differs between the upper and lower parts of the furnace body due to the influence of gravity, and variations occur within a single wafer. [0005] Furthermore, it is necessary to stand up the wafers one by one on a jig, which is not suitable for automation. Another disadvantage is that the device occupies a considerable amount of space. [0006] An object of the present invention is to provide a novel method for heat treatment of semiconductor wafers that eliminates the above-described drawbacks. In particular, it is an object of the present invention to provide a heat treatment method that avoids complicating the apparatus and eliminates the entrainment of contamination sources into the furnace tube. [0007]

【課題を解決するための手段】[Means to solve the problem]

本発明の特徴とするところは、円筒状の空間がほぼ鉛直
方向に沿って存在する炉管内で複数の半導体ウェハを熱
処理するにあたり、その炉管は長手方向一端が前記複数
の半導体ウェハの挿入が可能な開口端を成し、その一端
に対し長手方向反対側の他端はガス導入口を有する閉鎖
端を成す円筒状のものが使用され、該複数の半導体ウェ
ハを、その長手方向に所定間隔を保って半導体ウェハが
係合される所定の幅の溝がそれぞれ設けられた複数の棒
状部材とそれら棒状部材を所定間隔を保つようにその棒
状部材両端を支持する部材とからなる半導体ウェハ保持
治具に対し、それぞれを上記溝に係合させることにより
長手方向に所定間隔を保つてかつそれら半導体ウェハが
互いに対向するようにその半導体ウェハの周縁部の複数
箇所において係合保持させ、前記鉛直方向に沿って存在
する炉管の開口端より上記治具を炉管内に挿入せしめ、
その治具を炉管内壁に接触させることなく、かつ前記炉
管のガス導入口より炉管内にガスを導入させ加熱処理す
ることにある[0008]
The present invention is characterized in that when a plurality of semiconductor wafers are heat-treated in a furnace tube in which a cylindrical space exists along a substantially vertical direction, one longitudinal end of the furnace tube is inserted into the plurality of semiconductor wafers. A cylindrical type is used, which has an open end and a closed end having a gas inlet at the other end on the opposite side in the longitudinal direction, and the plurality of semiconductor wafers are spaced at predetermined intervals in the longitudinal direction. A semiconductor wafer holding jig comprising a plurality of rod-like members each having a groove of a predetermined width into which a semiconductor wafer is engaged while maintaining the distance between the rod-like members and a member supporting both ends of the rod-like members so as to maintain a predetermined distance between the rod-like members. The tools are engaged with the grooves at a plurality of locations on the peripheral edge of the semiconductor wafer so that a predetermined interval is maintained in the longitudinal direction and the semiconductor wafers face each other, and Insert the jig into the furnace tube from the open end of the furnace tube along the
Heat treatment is performed by introducing gas into the furnace tube from the gas inlet of the furnace tube without bringing the jig into contact with the inner wall of the furnace tube.[0008]

【作用】[Effect]

このような構成とすることにより炉の内壁とウェハ(ウ
ェハ治具)とを非接触にすることができ、異物の発生を
低減できる。又、ウェハはほぼ水平に保持されるので治
具から治具への一括移送がしやすく自動化に対応でき、
またウェハの大口径化にも対応できる。また、省スペー
ス、省エネルギーも達成でき、熱変形にも強い。 [0009] そして特に、ウェハ挿入とは反対方向からのガス導入と
しているために、装置すなわち炉管の構造は複雑になら
ず、そして半導体ウェハ挿入時の炉管内金体への汚染源
の巻き込みを反対側からのガス流入によって阻止するこ
とが可能となる[0010]
With such a configuration, the inner wall of the furnace and the wafer (wafer jig) can be made non-contact, and the generation of foreign matter can be reduced. In addition, since the wafers are held almost horizontally, it is easy to transfer them all at once from one jig to another, making it compatible with automation.
It can also accommodate larger diameter wafers. It also saves space and energy, and is resistant to thermal deformation. [0009] In particular, since the gas is introduced from the opposite direction to the direction in which the wafer is inserted, the structure of the apparatus, that is, the furnace tube, is not complicated, and the entanglement of contamination sources into the metal body in the furnace tube when the semiconductor wafer is inserted is avoided. This can be prevented by gas inflow from the side [0010]

【実施例】【Example】

図1は本発明の実施例による拡散処理方法を示すための
全体構成を示す断面図である。そして、図2はこの発明
の実施例で用いられるウェハ保持治具を示すものである
。 [0011] まず、図2において、多数の半導体ウェハ11はほぼ等
間隔で上下の一対の保持部材12A、12Bからなる保
持治具12内に配列される。保持部材12A。 12Bは互いに同様な構成で、図示の如く重ね合わせた
際にウェハ外径に相当する内径をもった円筒状部を各々
3本づつで計6本の棒状部12Xにより形成するように
なっている。そして、各棒状部12Xのウェハ11に係
合すべき部分にはウェハ厚さに相当する幅の溝が切られ
ており、後述のようにウェハ11を水平に保持してもウ
ェハが落下しないようになっている。 [0012] ウェハ保持治具12内に図2に示すように保持された多
数のウェハ11は、図1に示すように治具12を90°
回転させて治具ホルダ16に保持させることによりほぼ
水平の状態で縦方向に延在してなる石英管によって構成
された縦形拡散炉(熱処理炉)13内に挿入される。拡
散炉13はヒータ14を有すると共に、ウェハ挿入とは
反対側の下方から不純物を含むキャリアガス15を導入
するようになっている。 [0013] 拡散処理にあたっては、ガス15を炉13内に導入する
と共にヒータ14でウェハ11を所定の温度に加熱する
。一方、ウェハ保持治具12を治具ホルダ16を用いて
炉の内壁と非接触の状態で保持する。この実施例ではこ
の非接触を利用して治具ホルダ16を、さらに矢印UL
に示す如く上下動させ且つ矢印Rに示す如く回転させる
ことによりウェハ11に上下動及び回転運動を与えるよ
うにする。このようにすると、ウェハ11に対してヒー
タ14の熱とガス15中の不純物を均一に作用させるこ
とができるので、ウェハ内及びウェハ間の素子特性ばら
つきを大幅に減らすことができる。 [0014] 図3及び図4は、図1の処理バッチにおいて各ウェハ毎
に多数の拡散型トランジスタを形成した場合に、1ウエ
ハ内での又は複数ウェハ間でのトランジスタの電流増幅
率hFEのばらつきを従来法による場合と対比して示し
たものである。図3によれば、1つのウェハ11内にお
けるY方向に沿うhFEのばらつきは破線Aに示す従来
法による場合よりも実線Bで示すこの発明による場合の
方がはるかに小さいことが明らかである。また、図4に
よれば、同一処理バッチ内におけるウェハ11間のhF
Eのばらつきも破線Aに示す従来の場合よりも実線Bに
示すこの発明による場合の方が充分小さいことが明らか
である。 [0015]
FIG. 1 is a sectional view showing the overall configuration of a diffusion treatment method according to an embodiment of the present invention. FIG. 2 shows a wafer holding jig used in an embodiment of the invention. [0011] First, in FIG. 2, a large number of semiconductor wafers 11 are arranged at approximately equal intervals in a holding jig 12 consisting of a pair of upper and lower holding members 12A and 12B. Holding member 12A. 12B have the same configuration as each other, and as shown in the figure, when stacked together, three cylindrical portions each having an inner diameter corresponding to the outer diameter of the wafer are formed by a total of six rod-shaped portions 12X. . A groove with a width corresponding to the wafer thickness is cut in the portion of each rod-like portion 12X that should engage the wafer 11, so that the wafer does not fall even when the wafer 11 is held horizontally as described later. It has become. [0012] A large number of wafers 11 held in the wafer holding jig 12 as shown in FIG.
By rotating it and holding it in a jig holder 16, it is inserted in a substantially horizontal state into a vertical diffusion furnace (heat treatment furnace) 13 made up of a quartz tube extending vertically. The diffusion furnace 13 has a heater 14, and a carrier gas 15 containing impurities is introduced from below on the opposite side from where the wafer is inserted. [0013] In the diffusion process, gas 15 is introduced into furnace 13, and wafer 11 is heated to a predetermined temperature by heater 14. On the other hand, the wafer holding jig 12 is held using a jig holder 16 without contacting the inner wall of the furnace. In this embodiment, by utilizing this non-contact, the jig holder 16 is
By moving the wafer 11 up and down as shown in FIG. 2 and rotating it as shown by arrow R, the wafer 11 is given vertical movement and rotational motion. In this way, the heat from the heater 14 and the impurities in the gas 15 can be uniformly applied to the wafer 11, so variations in device characteristics within a wafer and between wafers can be significantly reduced. [0014] FIGS. 3 and 4 show variations in current amplification factor hFE of transistors within one wafer or between multiple wafers when a large number of diffused transistors are formed for each wafer in the processing batch of FIG. 1. This is shown in comparison with the case using the conventional method. According to FIG. 3, it is clear that the variation in hFE along the Y direction within one wafer 11 is much smaller in the case of the present invention shown by the solid line B than in the case of the conventional method shown by the broken line A. Furthermore, according to FIG. 4, hF between wafers 11 within the same processing batch
It is clear that the variation in E is also sufficiently smaller in the case according to the present invention shown by the solid line B than in the conventional case shown by the broken line A. [0015]

【発明の効果】【Effect of the invention】

(1)本発明によれば、円筒状の空間がほぼ鉛直方向に
そって存在する炉管内での複数の半導体ウェハの熱処理
であるために、すなわち縦方向の空間を利用するために
、従来の横形拡散炉に較べてスペース効率がよく、省ス
ペース化を図ることができる。 [0016] (2)本発明によれば、半導体ウェハ保持治具に対して
、複数の半導体ウェハのそれぞれをその半導体ウェハの
周縁部の複数箇所において接触保持させるものであるた
め、その半導体ウェハ保持治具自体は軽量なものとする
ことができ、大量のウェハチャージが可能となる。 [0017] (3)上述の如く半導体ウェハ保持治具自体は軽量なも
のとすることができるがため、図1に示す如くその半導
体ウェハ保持治具を炉管内においてその炉管内壁に接触
させることなく治具ホルダ16で半導体ウェハ保持治具
の長手方向一端部側のみを支えて加熱処理ができる。す
なわち、半導体ウェハ保持治具の片持ち支持ができる。 [0018] (4)半導体ウェハ保持治具を片持ち支持であれば、当
然両持ち支持に較べて異物発生は少なくなる効果がある
。すなわち、図1に示す如く半導体ウェハ保持治具の長
手方向の他端部側は浮かしておくために、炉管内での接
触摩擦部分がなくなり、このため、異物発生は少なくな
る。 [0019] (5)本発明によれば、半導体ウェハ保持治具の長手方
向に沿って所定間隔を保づて配置させ、その治具を鉛直
方向に沿って存在する炉管内にその内壁に接触させるこ
となく維持せしめるものであるため、炉体の径を小さく
でき、つまり、ヒータから炉体中心までの距離が短くで
きるためにウェハ内の温度不均一は小さくなり、均一加
熱化に近づく。 [00203 (6)本発明によれば、ウェハはほぼ水平に対向保持さ
れているためにガスの流れがウェハ面に直接あたらず、
ガスの濃度、量のばらつきによる影響は小さい。このた
め、ロフト間ばらつきも小さい。 [0021] (7)本発明によれば、実施例の如く複数の半導体ウェ
ハをほぼ水平に、かつそのウェハを水平面内で回転させ
るようにしているために、ガスの乱流をソフトに生じさ
せるものとなり、各ウェハ間、ウェハ内に均一にガスが
ゆきとどく。 [0022] (8)本発明によれば、実施例の如く複数の半導体ウェ
ハをほぼ水平に、カリそのウェハを水平面内で回転させ
るようにしているために、ウェハ回転手段の回転に負担
をかけず均一な回転が可能となる。 [0023] (9)図1に示すように半導体ウェハ保持治具の支持側
とは反対方向からのガスの流入のため、ガス流入口付近
でのガスの乱れを誘発する要因が減り、より一層各つニ
ハ間、ウェハ内へのガス均一化を図ることができる。 [0024] 以上のように、この発明によれば、炉構造ないし使用治
具類を特別複雑化させることなく、ウェハ内及びウェハ
間での素子特性ばらつきを大幅に低減することができ、
各種半導体装置を高歩留で製作できる効果は犬である。
(1) According to the present invention, a plurality of semiconductor wafers are heat-treated in a furnace tube in which a cylindrical space exists along a substantially vertical direction. It is more space efficient than a horizontal diffusion furnace and can save space. [0016] (2) According to the present invention, since each of a plurality of semiconductor wafers is held in contact with the semiconductor wafer holding jig at a plurality of locations on the peripheral edge of the semiconductor wafer, the semiconductor wafer holding jig is The jig itself can be made lightweight, and a large amount of wafers can be charged. [0017] (3) As mentioned above, the semiconductor wafer holding jig itself can be made lightweight, so the semiconductor wafer holding jig can be brought into contact with the inner wall of the furnace tube within the furnace tube as shown in FIG. Instead, heat treatment can be performed by supporting only one longitudinal end of the semiconductor wafer holding jig with the jig holder 16. That is, the semiconductor wafer holding jig can be supported in a cantilever manner. [0018] (4) If the semiconductor wafer holding jig is supported on a cantilever, it is natural that the generation of foreign matter is reduced compared to when it is supported on both sides. That is, as shown in FIG. 1, since the other longitudinal end of the semiconductor wafer holding jig is floated, there is no contact friction within the furnace tube, and therefore the generation of foreign matter is reduced. [0019] (5) According to the present invention, semiconductor wafer holding jigs are arranged at predetermined intervals along the longitudinal direction, and the jigs are placed in a furnace tube existing along the vertical direction and in contact with the inner wall thereof. Since the temperature can be maintained without heating, the diameter of the furnace body can be reduced, that is, the distance from the heater to the center of the furnace body can be shortened, so that temperature non-uniformity within the wafer is reduced, and heating becomes closer to uniformity. [00203 (6) According to the present invention, since the wafers are held substantially horizontally facing each other, the gas flow does not directly hit the wafer surface;
The influence of variations in gas concentration and amount is small. Therefore, the variation between lofts is also small. [0021] (7) According to the present invention, since the plurality of semiconductor wafers are placed almost horizontally as in the embodiment and the wafers are rotated within the horizontal plane, gas turbulence is softly generated. This allows the gas to spread uniformly between and within each wafer. [0022] (8) According to the present invention, since the plurality of semiconductor wafers are rotated almost horizontally in the horizontal plane as in the embodiment, no burden is placed on the rotation of the wafer rotation means. Uniform rotation is possible. [0023] (9) As shown in FIG. 1, since the gas flows in from the direction opposite to the support side of the semiconductor wafer holding jig, the factors that induce gas disturbance near the gas inlet are reduced, and the Uniform gas distribution between each wafer and within the wafer can be achieved. [0024] As described above, according to the present invention, variations in device characteristics within a wafer and between wafers can be significantly reduced without complicating the furnace structure or the jigs used.
The effect of being able to manufacture various semiconductor devices at high yields is the key.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】 本発明の実施例による拡散方法を示す炉体の断面図であ
る。
FIG. 1 is a sectional view of a furnace body showing a diffusion method according to an embodiment of the present invention.

【図2】 本発明の実施例で用いられるウェハ保持治具を示す斜視
図である。
FIG. 2 is a perspective view showing a wafer holding jig used in an embodiment of the present invention.

【図3】 本発明の効果を従来技術による場合と対比したウェハ所
定方向における電流増幅率のばらつきを示すグラフであ
る。
FIG. 3 is a graph showing variations in current amplification factors in a predetermined direction of a wafer, comparing the effects of the present invention with those of the prior art.

【図4】 本発明の効果を従来技術による場合と対比した同一処理
バッチ内のウェハ位置における電流増幅率のばらつきを
示すグラフである。
FIG. 4 is a graph showing variations in current amplification factors at wafer positions within the same processing batch, comparing the effects of the present invention with those of the prior art.

【図5】 従来技術におけるウェハの保持状態を示す側面図である
FIG. 5 is a side view showing a state in which a wafer is held in a conventional technique.

【図6】 従来技術による拡散法に用いられる炉体全体の断面図で
ある。
FIG. 6 is a sectional view of the entire furnace body used in the diffusion method according to the prior art.

【符号の説明】[Explanation of symbols]

11 半導体ウェハ 12 ウェハ保持治具 13 縦型拡散炉 16 治具ホルダ 11 Semiconductor wafer 12 Wafer holding jig 13 Vertical diffusion furnace 16 Jig holder

【書類者】[Document person]

図面 drawing

【図1】[Figure 1]

【図2】[Figure 2]

【図3】[Figure 3]

【図4】 つ1−1.幻Y°方句[Figure 4] 1-1. phantom Y° direction

【図5】[Figure 5]

【図6】[Figure 6]

Claims (2)

【特許請求の範囲】[Claims] 1.円筒状の空間がほぼ鉛直方向に沿って存在する炉管
内であって、その炉管内にガスを導入させながら複数の
半導体ウエハを熱処理するにあたり、該複数の半導体ウ
エハを、長手方向に所定間隔を保って半導体ウエハが係
合される所定の幅の溝がそれぞれ設けられた複数の棒状
部材とそれら棒状部材を所定間隔を保つようにその棒状
部材両端を支持する部材とからなる半導体ウエハ保持治
具に対し、それぞれを上記溝に係合させることによりそ
の半導体ウエハの周縁部の複数箇所において係合保持さ
せ、かつ治具の長手方向に沿って所定間隔を保って配置
させ、上記治具をその鉛直方向に沿って存在する炉管内
に、その炉管内へのガスの導入方向とは反対の方向より
挿入せしめ、上記治具をその炉管内壁に接触させること
なくその治具の長手方向一端部側のみで支え加熱処理す
ることを特徴とする半導体ウエハの熱処理方法。
1. In a furnace tube in which a cylindrical space exists along a substantially vertical direction, when a plurality of semiconductor wafers are heat-treated while introducing gas into the furnace tube, the plurality of semiconductor wafers are placed at a predetermined interval in the longitudinal direction. A semiconductor wafer holding jig comprising a plurality of rod-shaped members each provided with a groove of a predetermined width into which a semiconductor wafer is engaged, and a member that supports both ends of the rod-shaped members so as to maintain a predetermined distance between the rod-shaped members. In contrast, by engaging each of the grooves with the grooves, the semiconductor wafer is engaged and held at multiple locations on the periphery of the semiconductor wafer, and the jig is arranged at predetermined intervals along the longitudinal direction of the jig. The jig is inserted into a furnace tube existing along the vertical direction from a direction opposite to the direction in which gas is introduced into the furnace tube, and one longitudinal end of the jig is inserted without contacting the inner wall of the furnace tube. A method for heat treatment of semiconductor wafers, characterized in that the heat treatment is performed while supporting only on the sides.
2.加熱処理時に上記ウエハ保持治具を回転させること
を特徴とする特許請求の範囲第1項記載の半導体ウエハ
の熱処理方法。
2. 2. The method of heat treating a semiconductor wafer according to claim 1, wherein the wafer holding jig is rotated during the heat treatment.
JP191891A 1991-01-11 1991-01-11 Heat treating method of semiconductor wafer Pending JPH03273620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP191891A JPH03273620A (en) 1991-01-11 1991-01-11 Heat treating method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP191891A JPH03273620A (en) 1991-01-11 1991-01-11 Heat treating method of semiconductor wafer

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP15986778A Division JPS5588323A (en) 1978-12-27 1978-12-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03273620A true JPH03273620A (en) 1991-12-04

Family

ID=11514971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP191891A Pending JPH03273620A (en) 1991-01-11 1991-01-11 Heat treating method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH03273620A (en)

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