JPH03234063A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03234063A JPH03234063A JP2030277A JP3027790A JPH03234063A JP H03234063 A JPH03234063 A JP H03234063A JP 2030277 A JP2030277 A JP 2030277A JP 3027790 A JP3027790 A JP 3027790A JP H03234063 A JPH03234063 A JP H03234063A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- terminals
- ground
- terminal
- type field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000005669 field effect Effects 0.000 claims description 5
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 abstract description 14
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 abstract description 6
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 abstract description 6
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract 2
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 9
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 9
- 230000006378 damage Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101100496114 Caenorhabditis elegans clc-2 gene Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は絶縁ゲート型電界効果トランジスタ（以下、Ｍ
ＯＳ型トランジスタと呼ぶ）の組合せからなる半導体集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an insulated gate field effect transistor (hereinafter referred to as M
The present invention relates to a semiconductor integrated circuit consisting of a combination of OS type transistors.
従来の技術
一般的に、ＭＯＳ型トランジスタの組合せからなる半導
体集積回路の場合は、そのＭＯＳ型トランジスタにおけ
るゲートや接合部が静電気のサージ電圧によって破壊さ
れやすいという傾向がある。2. Description of the Related Art In general, in the case of a semiconductor integrated circuit consisting of a combination of MOS transistors, the gates and junctions of the MOS transistors tend to be easily destroyed by electrostatic surge voltage.
そのため、このような半導体集積回路の従来例では、そ
の回ｎにおける入出力端子に抵抗やダイオードを接続し
て静電気に対する保護回路を構成するのが通例である。Therefore, in conventional examples of such semiconductor integrated circuits, it is customary to connect a resistor or a diode to the input/output terminal at the time n to form a protection circuit against static electricity.
この場合の保護回路には、発生した急峻な静電気電圧波
形を緩和したり、静電気電圧が一定レベルに達すると所
定の電流経路を形成してサージ電流を電源端子や接地端
子に流し込み電気的ストレスを緩和するなどの働きがあ
る。In this case, the protection circuit is designed to alleviate the steep electrostatic voltage waveform that occurs, and to form a predetermined current path when the electrostatic voltage reaches a certain level to flow the surge current into the power supply terminal or ground terminal to reduce electrical stress. It has a relaxing effect.
発明が解決しようとする課題
しかしながら、上述した従来の静電気対策では、単一電
源を共有する複数の独立した電源端子およびこれらの電
源端子に１対１に対応付けられる複数の接地端子を必要
とする半導体集積回路の場合、例えば１つの電源端子に
接続されている回路系での入出力端子に上述した保護回
路を構成してもこれと異なる別の電源端子に接続されて
いる回路系の入出力端子との間にはサージ電圧印加時に
電流経路が形成されず、これらの間で静電破壊が生じる
という問題点があった。Problems to be Solved by the Invention However, the above-mentioned conventional static electricity countermeasures require a plurality of independent power terminals that share a single power source and a plurality of ground terminals that correspond one-to-one to these power terminals. In the case of semiconductor integrated circuits, for example, even if the above-mentioned protection circuit is configured on the input/output terminal of a circuit system connected to one power supply terminal, the input/output of a circuit system connected to a different power supply terminal may be configured. There is a problem in that a current path is not formed between the terminal and the terminal when a surge voltage is applied, and electrostatic damage occurs between them.
したがって、本発明の目的は、単一電源を共用する複数
の独立した電源端子および複数の独立した接地端子を持
つ場合でも静電破壊を防止することのできる半導体集積
回路を提供することである。Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can prevent electrostatic damage even when it has a plurality of independent power supply terminals and a plurality of independent ground terminals that share a single power supply.
課題３解決するための手段
本発明は、絶縁ゲート型電界効果トランジスタの組合せ
からなる複数の回路ブロックと、単一電源を共有する複
数の独立した電源端子と、これらの電源端子に１対１に
対応付けられる複数の独立した接地端子とを有し、各回
路クロックごとにそれぞれ対応する電源端子と接地端子
とが接続された半導体集積回路において、
各回路ブロックに対応する互いに異なるすべての電源端
子間および接地端子間を、静電気電圧印加時にオン動作
するエンハンスメント型電界効果フィールドトランジス
タを介して接続したことを特徴とする半導体集積回路で
ある。Means for Solving Problem 3 The present invention provides a plurality of circuit blocks consisting of a combination of insulated gate field effect transistors, a plurality of independent power supply terminals that share a single power supply, and a one-to-one connection between these power supply terminals. In a semiconductor integrated circuit that has a plurality of associated independent ground terminals, and in which the corresponding power supply terminal and ground terminal are connected for each circuit clock, all different power supply terminals corresponding to each circuit block are connected. and a ground terminal are connected via an enhancement type field effect field transistor that turns on when an electrostatic voltage is applied.
作 用
本発明に従えば、互いに異なる電源端子間および互いに
異なる接地端子間のすべてがエンハンスメント型フィー
ルドトランジスタで接続されているので、発生した静電
気電圧がエンハンスメント型フィールドトランジスタの
ターンオン電圧に達すると、すべての電源端子相互間お
よびすべての接地端子相互間に電流経路が形成されａｔ
気破壊が防止される。According to the present invention, all different power supply terminals and different ground terminals are connected by enhancement type field transistors, so when the generated electrostatic voltage reaches the turn-on voltage of the enhancement type field transistor, all A current path is formed between the power supply terminals of at
Qi destruction is prevented.
実施例
図面は本発明の一実施例である半導体集積回路の概略的
な構成を示す回路図である。Embodiment The drawing is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit that is an embodiment of the present invention.
この半導体集積回路はそれぞれＭＯＳ型トランジスタの
組合せからなる複数の回路ブロックＣｌＣ２，Ｃ３・・
・と、単一の電源ＶＤＤに共通に接続される複数の独立
した電源端子ＶＤＤ １ 、ＶＤＤ２、ＶＤＤ３・・・
と、これらの電源端子に対応付けられる複数の独立した
接地端子０ＮＤＩ、ＧＮＤ２、ＧＮＤ３・・・とを含み
、各回路ブロックｃ１゜Ｃ２・・・はそれぞれ対応する
電源端子ＶＤＤ１．ＶＤＤ２．ＶＤＤ３・・・と接地端
子ＧＮＤＩ、ＧＮＤ２、ＧＮＤ３・・・とに接続されて
いる。This semiconductor integrated circuit includes a plurality of circuit blocks ClC2, C3, . . . each consisting of a combination of MOS transistors.
・A plurality of independent power supply terminals VDD 1 , VDD2, VDD3 . . . are commonly connected to a single power supply VDD.
and a plurality of independent ground terminals 0NDI, GND2, GND3, . . . associated with these power supply terminals, and each circuit block c1, C2, . VDD2. It is connected to VDD3... and ground terminals GNDI, GND2, GND3...
また、すべての電源端子間、つまり図面では電源端子Ｖ
ＤＤＩ、ＶＤ０２間、電源端子ＶＤＤ２゜ＶＤＤ３間お
よび電源端子ＶＤＤ３．ＶＤＤＩ間のすべてが、互いに
並列に接続された２つのＮチャンネルエンハンスメント
型フィールドトランジスタ（以下、Ｎ型フィールドトラ
ンジスタと呼ぶ）Ｎｌ、Ｎ２を介してそれぞれ結線され
ている。すなわち、２つのＮ型フィールドトランジスタ
Ｎｌ。Also, between all power supply terminals, that is, power supply terminal V in the drawing.
DDI and VD02, between power supply terminals VDD2 and VDD3, and between power supply terminals VDD3. Everything between VDDI and N2 is connected via two N-channel enhancement type field transistors (hereinafter referred to as N-type field transistors) N1 and N2, which are connected in parallel to each other. That is, two N-type field transistors Nl.
Ｎ２のそれぞれにおいてはゲート電極とソース電極とが
接続されており、例えば電源端子ＶＤＤＩ。In each of N2, a gate electrode and a source electrode are connected, for example, to a power supply terminal VDDI.
ＶＤＤ２間では、一方のＮ型フィールドトランジスタＮ
１についてはそのソース電極側が電源端子ＶＤＤＩに、
ドレインを極側が電源端子ＶＤＤ２に接続され、他方の
Ｎ型フィールドトランジスタＮ２についてはそのソース
を極側が電源端子ＶＤＤ２に、ドレイン電極側が電源端
子ＶＤＤＩに接続されている。つまり、電源端子ＶＤＤ
Ｉ、ＶＤＤ２間で、２つのＮ型フィールドトランジスタ
Ｎ１、Ｎ２は極性を互いに逆向きにして並列に接続され
ている。この接続構成はそのほかのすべての電源端子間
においても同様である。Between VDD2, one N-type field transistor N
Regarding 1, the source electrode side is connected to the power supply terminal VDDI,
The drain is connected to the power supply terminal VDD2 on the pole side, and the source of the other N-type field transistor N2 is connected to the power supply terminal VDD2 on the pole side, and the drain electrode side is connected to the power supply terminal VDDI. In other words, the power supply terminal VDD
Between I and VDD2, two N-type field transistors N1 and N2 are connected in parallel with opposite polarities. This connection configuration is the same between all other power supply terminals.
これとは別に、すべての接地端子間、つまり図面では接
地端子ＧＮＤＩ、ＧＮＤ２間、接地端子ＧＮＤ２．ＧＮ
Ｄ３問および接地端子ＧＮＤ３゜ＧＮＤ １間のすべて
が、互いに並列に接続された２つのＰチャンネルエンハ
ンスメント型フィールドトランジスタ（以下、Ｐ型フィ
ールドトランジスタと呼ぶ）ＰＩ、Ｐ２を介してそれぞ
れ結線されている。すなわち、２つのＰ型フィールドト
ランジスタＰＬ、Ｐ２のそれぞれにおいてはゲート電極
とソース電極とが接続されており、例えば接地端子ＧＮ
ＤＩ、ＧＮＤ２間では、一方のＰ型フィールドトランジ
スタＰ１についてはそのソース電極側が接地端子ＧＮＤ
１に、ドレイン！極側が接地端子ＧＮＤ２に接続され
、他方のＰ型フィールドトランジスタＰ２についてはそ
のソース電極側が接地端子ＧＮＤ２に、ドレイン電極側
が接地端子ＧＮＤ １に接続されている。つまり、接地
端子ＧＮＤＩ、ＧＮＤ２間で、２つのＰ型フィールドト
ランジスタＰＬ、Ｐ２は極性を互いに逆向きにして並列
に接続されている。この接続構成はそのほかのすべての
接地端子間においても同様である。Apart from this, between all the ground terminals, that is, between the ground terminals GNDI and GND2 in the drawing, and between the ground terminals GND2. GN
Everything between D3 and ground terminals GND3 and GND1 is connected via two P-channel enhancement type field transistors (hereinafter referred to as P-type field transistors) PI and P2 that are connected in parallel to each other. That is, in each of the two P-type field transistors PL and P2, the gate electrode and the source electrode are connected, for example, the ground terminal GN.
Between DI and GND2, the source electrode side of one P-type field transistor P1 is connected to the ground terminal GND.
First, drain! The pole side is connected to the ground terminal GND2, and the source electrode side of the other P-type field transistor P2 is connected to the ground terminal GND2, and the drain electrode side is connected to the ground terminal GND1. That is, between the ground terminals GNDI and GND2, the two P-type field transistors PL and P2 are connected in parallel with opposite polarities. This connection configuration is the same between all other ground terminals.
上記半導体ｔＡ積回路において、例えばその１つの回路
ブロックＣ１側においてその電源端子ＶＤＤ１および入
出力端子ＩＮ、ＯＵＴに静電気によるサージ電圧が印加
され、その初期過程で電源端％ＶＤＤ１に対して隣の電
源端子ＶＤＤ２側の電位がプラス側に上昇するとき、そ
の上昇電圧が電源端子ＶＤＤＩ、ＶＤＤ２間に接続され
ているＮ型フィールドトランジスタＮＩのターンオン電
圧に達すると、このＮ型フィールドトランジスタＮ１が
オンとなって電源端子ＶＤＤＩと電源端子■ＤＤ２とを
結ぶ電流経路が形成される。In the above semiconductor tA product circuit, for example, on the side of one circuit block C1, a surge voltage due to static electricity is applied to the power supply terminal VDD1 and the input/output terminals IN and OUT, and in the initial process, the power supply terminal % VDD1 is applied to the adjacent power supply. When the potential on the terminal VDD2 side rises to the positive side, when the rising voltage reaches the turn-on voltage of the N-type field transistor NI connected between the power supply terminals VDDI and VDD2, this N-type field transistor N1 is turned on. A current path connecting the power supply terminal VDDI and the power supply terminal DD2 is formed.
逆に、電源端子ＶＤＤ２側の電位が電源端子ＶＤＤ１に
対してマイナス側に降下する場合には、その降下電圧が
電源端子ＶＤＤＩ、ＶＤＤ２間に接続されているもう１
つのＮ型フィールドトランジスタＮ２のターンオン電圧
に達した時点で、このＮ型フィールドトランジスタＮ２
がオンとなって同様に電源端子ＶＤＤＩ、ＶＤＤ２間に
電流経路が形成される。Conversely, when the potential on the power supply terminal VDD2 side drops to the negative side with respect to the power supply terminal VDD1, the dropped voltage is applied to the other terminal connected between the power supply terminals VDDI and VDD2.
When the turn-on voltage of one N-type field transistor N2 is reached, this N-type field transistor N2
is turned on, and a current path is similarly formed between the power supply terminals VDDI and VDD2.
また、例えばその１つの回路ブロックＣ１側においてそ
の接地端子ＧＮＤＩおよび入出力端子ＩＮ、ＯＵＴに静
電気によるサージ電圧が印加され、その初期過程で接地
端子ＧＮＤ １に対して隣の接地端子ＧＮＤ２側の電位
がプラス側に上昇するとき、その上昇電圧が接地端子Ｇ
Ｎ Ｄ １ 、 Ｇ Ｎ Ｄ ２間に接続されている
Ｐ型フィールドトランジスタＰＩのターンオン電圧に達
すると、このＰ型フィールドトランジスタＰ１がオンと
なって電源端子ＧＮＤ １と電源端子ＧＮＤ２とを結ぶ
電流経路が形成される。Also, for example, on the side of one circuit block C1, a surge voltage due to static electricity is applied to the ground terminal GNDI and the input/output terminals IN and OUT, and in the initial process, the potential of the adjacent ground terminal GND2 side with respect to the ground terminal GND 1 is applied. rises to the positive side, the rising voltage is connected to the ground terminal G
When the turn-on voltage of the P-type field transistor PI connected between N D 1 and G ND 2 is reached, this P-type field transistor P 1 is turned on and a current path connecting the power terminal GND 1 and the power terminal GND 2 is established. is formed.
逆に、接地端子ＧＮＤ２側の電位が接地端子ＧＮＤＩに
対してマイナス側に降下する場合には、その降下電圧が
接地端子ＧＮＤ’１．ＧＮＤ２間にｔＩ続されているも
う１つのＰ型フィールドトランジスタＰ２のターンオン
電圧に達した時点で、このＰ型フィールドトランジスタ
Ｐ２がオンとなりって同様に接地端子ＧＮＤＩ、ＧＮＤ
２間に電流経路が形成される。Conversely, when the potential on the ground terminal GND2 side drops to the negative side with respect to the ground terminal GNDI, the dropped voltage is applied to the ground terminal GND'1. When the turn-on voltage of another P-type field transistor P2 connected between GND2 and GND2 is reached, this P-type field transistor P2 turns on and similarly connects the ground terminals GNDI and GND.
A current path is formed between the two.
発明の効果
以上のように、本発明の半導体集積回路によれば、各回
路ブロックに対応する互いに異なる電源端子間および互
いに異なる接地端子間のすべてがエンハンスメント型フ
ィールドトランジスタで接続されているので、発生した
静電気電圧がエンハンスメント型フィールドトランジス
タのターンオン電圧に達すると、すべての電源端子相互
間およびすべての接地端子相互間に電流経路が形成され
半導体集積回路を静電気破壊から保護することができる
。Effects of the Invention As described above, according to the semiconductor integrated circuit of the present invention, all the different power supply terminals and the different ground terminals corresponding to each circuit block are connected by enhancement type field transistors, so that When the electrostatic voltage reaches the turn-on voltage of the enhancement type field transistor, current paths are formed between all the power supply terminals and between all the ground terminals, thereby protecting the semiconductor integrated circuit from electrostatic damage.
図面は本発明の一実施例である半導体集積回路の概略的
な構成を示す回路図である。
ＶＤＤＩ〜ＶＤＤＢ・・・電源端子、ＧＮＤ １〜ＧＮ
Ｄ３・・・接地端子、Ｃ１〜Ｃ３・・・回路ブロック、
Ｎｌ、Ｎ２・・・Ｎ型フィールドトランジスタ、ＰＩ。
Ｐ２〜Ｐ型フィールドトランジスタThe drawing is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit which is an embodiment of the present invention. VDDI~VDDB...power supply terminal, GND 1~GN
D3...ground terminal, C1-C3...circuit block,
Nl, N2...N-type field transistor, PI. P2 ~ P type field transistor
Claims (1)
数の回路ブロックと、単一電源を共有する複数の独立し
た電源端子と、これらの電源端子に１対１に対応付けら
れる複数の独立した接地端子とを有し、各回路クロック
ごとにそれぞれ対応する電源端子と接地端子とが接続さ
れた半導体集積回路において、 各回路ブロックに対応する互いに異なるすべての電源端
子間および接地端子間を、静電気電圧印加時にオン動作
するエンハンスメント型電界効果フィールドトランジス
タを介して接続したことを特徴とする半導体集積回路。[Claims] A plurality of circuit blocks each consisting of a combination of insulated gate field effect transistors, a plurality of independent power supply terminals sharing a single power supply, and a plurality of circuit blocks each having a one-to-one correspondence with these power supply terminals. In a semiconductor integrated circuit that has an independent ground terminal and a corresponding power supply terminal and ground terminal are connected for each circuit clock, all different power supply terminals and ground terminals corresponding to each circuit block are connected. , a semiconductor integrated circuit characterized in that the semiconductor integrated circuit is connected through an enhancement type field effect field transistor that turns on when an electrostatic voltage is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2030277A JP2598147B2 (en) | 1990-02-09 | 1990-02-09 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2030277A JP2598147B2 (en) | 1990-02-09 | 1990-02-09 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03234063A true JPH03234063A (en) | 1991-10-18 |
| JP2598147B2 JP2598147B2 (en) | 1997-04-09 |
Family
ID=12299220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2030277A Expired - Fee Related JP2598147B2 (en) | 1990-02-09 | 1990-02-09 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2598147B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10224205A (en) * | 1996-11-04 | 1998-08-21 | Samsung Electron Co Ltd | Data output circuit of semiconductor device |
| KR100250018B1 (en) * | 1995-08-31 | 2000-03-15 | 다카노 야스아키 | Semiconductor devices |
| JP2007324345A (en) * | 2006-05-31 | 2007-12-13 | Nec Electronics Corp | Semiconductor device provided with protection circuit |
| US7821096B2 (en) | 2006-04-27 | 2010-10-26 | Panasonic Corporation | Semiconductor integrated circuit and system LSI including the same |
| JP2023501326A (en) * | 2019-11-05 | 2023-01-18 | フォームファクター， インコーポレイテッド | Probe system and method for probing a device under test |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02111063A (en) * | 1988-10-20 | 1990-04-24 | Nec Corp | Semiconductor integrated circuit device |
-
1990
- 1990-02-09 JP JP2030277A patent/JP2598147B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02111063A (en) * | 1988-10-20 | 1990-04-24 | Nec Corp | Semiconductor integrated circuit device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100250018B1 (en) * | 1995-08-31 | 2000-03-15 | 다카노 야스아키 | Semiconductor devices |
| JPH10224205A (en) * | 1996-11-04 | 1998-08-21 | Samsung Electron Co Ltd | Data output circuit of semiconductor device |
| US7821096B2 (en) | 2006-04-27 | 2010-10-26 | Panasonic Corporation | Semiconductor integrated circuit and system LSI including the same |
| US8102024B2 (en) | 2006-04-27 | 2012-01-24 | Panasonic Corporation | Semiconductor integrated circuit and system LSI including the same |
| JP2007324345A (en) * | 2006-05-31 | 2007-12-13 | Nec Electronics Corp | Semiconductor device provided with protection circuit |
| JP2023501326A (en) * | 2019-11-05 | 2023-01-18 | フォームファクター， インコーポレイテッド | Probe system and method for probing a device under test |
| EP4055394A4 (en) * | 2019-11-05 | 2023-12-13 | FormFactor, Inc. | Probe systems and methods for testing a device under test |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2598147B2 (en) | 1997-04-09 |
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