JP2598147B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to an insulated gate field effect transistor (hereinafter, referred to as an insulated gate field effect transistor).
A MOS integrated transistor).

2. Description of the Related Art Generally, in the case of a semiconductor integrated circuit including a combination of MOS transistors, a gate and a junction of the MOS transistor tend to be easily damaged by a surge voltage of static electricity.

Therefore, in the conventional example of such a semiconductor integrated circuit,
Usually, a resistor or a diode is connected to the input / output terminal of the circuit to form a protection circuit against static electricity. In the protection circuit in this case, a steep generated electrostatic voltage waveform is relieved, or when the electrostatic voltage reaches a certain level, a predetermined current path is formed to supply a surge current to a power supply terminal or a ground terminal to reduce electric stress. It has the function of relaxing.

However, the above-described conventional countermeasures against static electricity require a plurality of independent power terminals sharing a single power supply and a plurality of ground terminals associated with these power terminals on a one-to-one basis. In the case of a semiconductor integrated circuit, for example, even if the above-described protection circuit is configured as an input / output terminal of a circuit connected to one power supply terminal, the input / output of a circuit connected to another power supply terminal different from this. There is a problem that a current path is not formed between the terminal and the terminal when a surge voltage is applied, and electrostatic breakdown occurs between the terminals.

Accordingly, an object of the present invention is to provide a semiconductor integrated circuit which can prevent electrostatic breakdown even when having a plurality of independent power terminals and a plurality of independent ground terminals sharing a single power supply.

Means for Solving the Problems The present invention provides a plurality of circuit blocks composed of a combination of insulated gate field effect transistors, a plurality of independent power terminals sharing a single power source, and a one-to-one connection between these power terminals.
In a semiconductor integrated circuit having a plurality of independent ground terminals associated with each other and connected to a corresponding power terminal and a ground terminal for each circuit block, all different power terminals corresponding to each circuit block are provided. And a ground terminal connected via an enhancement type field effect field transistor which is turned on when an electrostatic voltage is applied.

Further, the present invention has three or more circuit blocks, a plurality of independent power terminals sharing a single power supply, and a plurality of independent ground terminals associated with these power terminals on a one-to-one basis. The circuit block is composed of a combination of insulated gate field effect transistors. In a semiconductor integrated circuit in which a power terminal and a ground terminal corresponding to each circuit block are connected, all the different power terminals corresponding to each circuit block are provided. Are sequentially connected via an enhancement-type field-effect field transistor that is turned on when an electrostatic voltage is applied so that a closed loop is formed. A closed loop is formed via the enhancement type field effect field transistor that turns on when a voltage is applied. A semiconductor integrated circuit characterized by being connected so as to be formed.

According to the present invention, since all the different power terminals and the different ground terminals are connected by the enhancement field transistor, when the generated electrostatic voltage reaches the turn-on voltage of the enhancement field transistor, A current path is formed between the power supply terminals and between all the ground terminals to prevent electrostatic breakdown.

The threshold, which is the turn-on voltage of the enhancement-type field-effect field transistor used in the present invention, is relatively high, for example, about 30 V, so that each circuit block composed of a combination of insulated-gate field-effect transistors is supplied from a single power supply. In the normal operation state where power is supplied via the power terminal and the ground terminal,
The enhancement-type field-effect field transistor is shut off and conducts for the first time when static electricity is applied as described above, so that there is no problem in the operation state of the circuit block.

According to the invention, three or more circuit blocks are provided, and the power supply terminals are sequentially connected via the above-mentioned enhancement type field effect field transistor so as to form a closed loop. Is connected to the other two power supply terminals, and such a connection state is the same with respect to the ground terminal. Therefore, when a high voltage due to static electricity is applied, the enhancement-type field effect field transistor becomes conductive. As a result, the high voltage is dispersed as widely as possible, whereby the dielectric breakdown of the insulated gate field effect transistor provided in the circuit block can be reliably prevented.

Embodiment FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

This semiconductor integrated circuit includes a plurality of circuit blocks C1, C2, C3,... Each composed of a combination of MOS transistors, and a plurality of independent power supply terminals V commonly connected to a single power supply VDD.
DD1, VDD2, VDD3 ... and a plurality of independent ground terminals GND1, GND2, GND3 ... associated with these power terminals,
Each of the circuit blocks C1, C2,.
1, VDD2, VDD3,... And ground terminals GND1, GND2, GND3,.

Also, between all the power terminals, that is, the power terminals in the drawing
Between VDD1 and VDD2, between power supply terminals VDD2 and VDD3, and between power supply terminals VDD
3. Everything between VDD1 is two N connected in parallel with each other
They are connected via channel enhancement type field transistors (hereinafter referred to as N-type field transistors) N1 and N2, respectively. That is, in each of the two N-type field transistors N1 and N2, the gate electrode and the source electrode are connected. For example, between the power supply terminals VDD1 and VDD2, one of the N-type field transistors N1 has its source electrode connected to the power supply. Terminal VDD1
The drain electrode side is connected to the power supply terminal VDD2, the source electrode side of the other N-type field transistor N2 is connected to the power supply terminal VDD2, and the drain electrode side is connected to the power supply terminal VDD1. That is, the two N-type field transistors N1 and N2 are connected in parallel with the polarities opposite to each other between the power supply terminals VDD1 and VDD2. This connection configuration is the same between all other power supply terminals.

Separately, two P-channel enhancement types are connected in parallel between all ground terminals, that is, between the ground terminals GND1 and GND2, between the ground terminals GND2 and GND3, and between the ground terminals GND3 and GND1. Field transistor (hereinafter referred to as P-type field transistor)
They are connected via P1 and P2, respectively. That is, 2
In each of the two P-type field transistors P1 and P2, the gate electrode and the source electrode are connected. For example, between the ground terminals GND1 and GND2, the source electrode side of one P-type field transistor P1 is connected to the ground terminal.
The drain electrode side is connected to ground terminal GND2, and the other P-type field transistor P2 has its source electrode side connected to ground terminal GND2 and its drain electrode side connected to ground terminal GND2.
Connected to GND1. That is, the two P-type field transistors P1 and P2 are connected in parallel with the polarities opposite to each other between the ground terminals GND1 and GND2. This connection configuration is the same between all other ground terminals.

In the semiconductor integrated circuit, for example, a surge voltage due to static electricity is applied to the power supply terminal VDD1 and the input / output terminals IN and OUT on the one circuit block C1 side, and the power supply terminal VDD2 adjacent to the power supply terminal VDD1 in an initial process. When the potential on the positive side rises to the positive side, the rising voltage
When the turn-on voltage of the N-type field transistor NI connected between VDD1 and VDD2 is reached, this N-type field transistor N1 is turned on, and a current path connecting the power supply terminal VDD1 and the power supply terminal VDD2 is formed.

Conversely, if the potential of the power supply terminal VDD2 drops to the minus side with respect to the power supply terminal VDD1, the voltage drop turns on another N-type field transistor N2 connected between the power supply terminals VDD1 and VDD2. When the voltage is reached,
When the N-type field transistor N2 is turned on, a current path is similarly formed between the power supply terminals VDD1 and VDD2.

Further, for example, a surge voltage due to static electricity is applied to the ground terminal GND1 and the input / output terminals IN and OUT on the one circuit block C1 side, and the potential of the adjacent ground terminal GND2 side with respect to the ground terminal GND1 in the initial process. When the voltage rises to the positive side, when the rising voltage reaches the turn-on voltage of the P-type field transistor PI connected between the ground terminals GND1 and GND2, the P-type field transistor P1 turns on and the power supply terminal GND1 and the power supply A current path connecting the terminal GND2 is formed.

Conversely, when the potential of the ground terminal GND2 drops to the minus side with respect to the ground terminal GND1, the drop voltage turns on another P-type field transistor P2 connected between the ground terminals GND1 and GND2. When the voltage is reached,
When the P-type field transistor P2 is turned on, a current path is similarly formed between the ground terminals GND1 and GND2.

As described above, according to the semiconductor integrated circuit of the present invention, since all the different power supply terminals and the different ground terminals corresponding to each circuit block are connected by the enhancement type field transistor, the When the generated electrostatic voltage reaches the turn-on voltage of the enhancement type field transistor, a current path is formed between all power supply terminals and between all ground terminals, so that the semiconductor integrated circuit can be protected from electrostatic breakdown.

In particular, in accordance with the present invention, the turn-on voltage of the enhancement field effect field transistor is relatively high, for example, about 30 V, and therefore supplies power from a single power supply to the circuit block via the power supply terminal and the ground terminal. In a normal operation state, the enhancement-type field effect field transistor does not conduct, and does not hinder the operation of the circuit block.

Further, according to the present invention, three or more circuit blocks are provided, and the power supply terminals are sequentially connected so as to form a closed loop via the enhancement type field effect field transistor. Similarly, the ground terminal is also sequentially enhanced. Are connected so as to form a closed loop via the field-effect field transistor, so that a high voltage due to static electricity is applied and the enhancement-type field-effect field transistor conducts, so that the high voltage is dispersed as widely as possible. That is, the dielectric breakdown of the insulated gate field effect transistor of the circuit block can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to one embodiment of the present invention. VDD1 to VDD3: Power supply terminal, GND1 to GND3: Ground terminal, C1
... C3 ... circuit block, N1, N2 ... N-type field transistor, P1, P2-P-type field transistor

Claims (2)

(57) [Claims] 1. A plurality of circuit blocks each comprising a combination of insulated gate field effect transistors; a plurality of independent power terminals sharing a single power source;
In a semiconductor integrated circuit having a plurality of independent ground terminals associated with each other and connected to a corresponding power terminal and a ground terminal for each circuit block, all different power terminals corresponding to each circuit block are provided. A semiconductor integrated circuit, wherein the semiconductor device and the ground terminal are connected via an enhancement type field effect field transistor which is turned on when an electrostatic voltage is applied. 2. A power supply system comprising: three or more circuit blocks; a plurality of independent power supply terminals sharing a single power supply;
Each circuit block includes a combination of insulated gate field effect transistors, and a corresponding power terminal and ground terminal are connected to each circuit block. In a semiconductor integrated circuit, all the different power supply terminals corresponding to each circuit block are sequentially connected via an enhancement type field effect field transistor which is turned on when an electrostatic voltage is applied so as to form a closed loop, A semiconductor integrated circuit, wherein all different ground terminals corresponding to each circuit block are sequentially connected via an enhancement type field effect field transistor which is turned on when an electrostatic voltage is applied so as to form a closed loop. circuit.