JP2002246555A - Redundant logic circuit having device charged model esd breakdown protecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device charged model ESD breakdown protecting redundant logic circuit wherein a redundant logic transistor can be surely protected to electrostatic discharge of a device charged model. SOLUTION: In the case that an electronic device which mounts the device charged model ESD breakdown protecting redundant logic circuit is subjected to electrostatic discharge of the device charged model, a diode 13 is inserted between a gate and a source of a P-type MOS transistor 11, and a diode 14 is inserted between a gate and a source of an N-type MOS transistor 12. Consequently, potentials of the gate terminals and the source terminals of the respective transistors are charged to the same potential instantaneously, and constitution for preventing electrostatic breakdown which is to be caused by the potential difference between the gate and the source is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device charging model ESD destruction protection circuit for protecting a circuit unit against electrostatic discharge of a device charging model, and a redundant logic circuit for various electrostatic discharges. To a device charging model ESD destruction protection circuit that protects the device.

[0002]

2. Description of the Related Art In various circuit units constituting an electronic device, a redundant logic circuit is often formed in the circuit unit so that the logic circuit can be changed. Conventionally, the input gate of the redundant logic circuit has been connected to the GND potential via a resistor as shown in FIG.

[0003]

However, in the redundant logic circuit having the above-described configuration, when the circuit unit is subjected to the device charging model electrostatic discharge, the input gate is connected to the GND potential via the resistor as shown in FIG. When the source is connected and the distance from the inter-power supply protection element is large, a difference occurs between the time when the source potential of the P-type MOS transistor changes and the time when the gate potential changes due to electrostatic discharge. A voltage was generated between the transistors, causing a phenomenon that the P-type MOS transistor was electrostatically damaged. The circuit configuration of the present invention solves the above problems.

[0004]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a redundant logic circuit with a device charging model ESD destruction protection circuit according to the present invention will be described in detail with reference to the drawings. The present invention is not limited by these embodiments.

In the embodiment shown in FIG. 1, between the gate and source of the P-type MOS transistor 11 and between the N-type MOS transistor 12
The diode 13 and the diode 14 are inserted between the gate and the source, respectively, so that when the electrostatic discharge of the device charging model is performed to the GND and VDD terminals, the potentials of the gate terminal and the source terminal of each transistor are instantaneously set to the same potential. , The structure prevents electrostatic breakdown due to a potential difference between the gate and the source. Although the logic circuit is an inverter circuit in the configuration shown in FIG. 1, the same effect can be obtained by using a similar configuration in a NOR circuit and a NAND circuit.

In the embodiment shown in FIG. 3, between the gate and source of the P-type MOS transistor 31 and the N-type MOS transistor 32
By inserting a resistor 33 and a resistor 34 between the gate and source of each transistor, the potentials of the gate terminal and the source terminal of each transistor instantaneously become equal when the electrostatic discharge of the device charging model is carried out to the GND and VDD terminals. Since it is charged to a potential, the configuration is such that electrostatic breakdown due to a potential difference between the gate and the source is prevented. Although the logic circuit is an inverter circuit in the configuration shown in FIG. 3, the same effect can be obtained in a NOR circuit and a NAND circuit by adopting a similar configuration.

In the embodiment shown in FIG. 4, between the gate and the drain of the P-type MOS transistor 41 and between the N-type MOS transistor 4
By connecting them between the gate and the drain of each device, the potentials of the gate terminal and the source terminal of each transistor are instantaneously charged to the same potential when the electrostatic discharge of the device charging model is performed on the GND and VDD terminals. Therefore, the configuration is such that electrostatic breakdown due to the potential difference between the gate and the source is prevented. FIG.
In the configuration shown in (1), the logic circuit is an inverter circuit, but the same effect can be obtained by adopting a similar configuration in a NOR circuit and a NAND circuit.

In the embodiment shown in FIG. 5, it is possible to flow a relatively large current in a configuration in which an N-type MOS transistor 54 is diode-connected between VDD and GND so as to correspond to each logic circuit on a one-to-one basis. By adding a protection element having the same function as the power supply protection element, GND and
Since the potential of the gate terminal and the source terminal of each transistor is instantaneously charged to the same potential when the device is electrostatically discharged in the device charging model at the VDD terminal, a configuration that prevents electrostatic breakdown due to the potential difference between the gate and source Becomes

[0009]

As described above, according to the present invention,
In a device charging model ESD destruction protection circuit for protecting a circuit unit constituting an electronic device from electrostatic breakdown due to electrostatic discharge of a device charging model of the electronic device, a gate terminal of a transistor of a logic circuit and The potential of the source terminal is instantaneously set to the same potential by the resistor and the diode, thereby preventing a potential difference between the gate and the source from being generated, thereby protecting the device from electrostatic breakdown.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram for explaining the principle configuration of a device charging model ESD destruction protection redundant logic circuit of the present invention, and is a diagram of a redundant logic circuit with a device charging model ESD destruction protection circuit according to an embodiment.

FIG. 2 is a diagram of a conventional redundant logic circuit.

FIG. 3 is a redundant logic circuit diagram with another device charging model ESD destruction protection circuit according to the embodiment of the present invention.

FIG. 4 is a redundant logic circuit diagram with another device charging model ESD destruction protection circuit according to the embodiment of the present invention.

FIG. 5 is a redundant logic circuit diagram with another device charging model ESD destruction protection circuit according to the embodiment of the present invention.

[Explanation of symbols]

11, 21, 31, 41, 51 P-type MOS transistor 12, 22, 32, 42, 52, 54 N-type MOS transistor 13, 14 Diode 23, 33, 34, 53 Resistance

Claims (7)

[Claims] 1. An electronic device comprising a redundant logic circuit in a circuit unit, and a device charging model of the electronic device having a device charging model ESD destruction protection circuit for protecting the redundant logic circuit from destruction against electrostatic discharge. In the redundant logic circuit configuration, at the time of the device charging model electrostatic discharge, the gate terminal of the P-type MOS transistor in the redundant logic circuit is connected to the anode terminal of the diode 1, the source terminal is connected to the cathode terminal of the diode 1, and the source terminal is Connected to the VDD potential, the gate terminal of the N-type MOS transistor is connected to the anode terminal of the diode 2, the source terminal is connected to the cathode terminal of the diode 2, the source terminal is connected to the GND potential, The configuration is such that the drain terminal is connected to the drain terminal of the N-type MOS transistor. Charged Device Model ESD damage protection circuit with a redundant logic circuit for protecting the transistor from the electrostatic breakdown by 2. The method according to claim 2, wherein said gate terminal and said source terminal of said P-type MOS transistor in said redundant logic circuit are connected to a resistor.
And the source terminal is connected to the VDD potential,
The gate terminal and the source terminal of the N-type MOS transistor are connected via a resistor 2, the source terminal is connected to GND potential, and the drain terminal of the P-type MOS transistor is connected to the drain terminal of the N-type MOS transistor. 2. A redundant logic circuit with a device charging model ESD destruction protection circuit according to claim 1, wherein the device is protected from electrostatic destruction by adopting a configuration. 3. The redundant logic circuit connects the gate terminal and the drain terminal of the P-type MOS transistor, the source terminal is connected to the VDD potential, and connects the gate terminal and the drain terminal of the N-type MOS transistor to each other. Connected and the source terminal is connected to GND potential to protect the transistor from electrostatic destruction. Device charging model Redundant logic circuit with ESD destruction protection circuit 4. The device charging model according to claim 1, wherein said redundant logic circuit is an inverter circuit.
Redundant logic circuit with ESD protection circuit 5. The device charging model ESD according to claim 1, wherein said redundant logic circuit is a NOR circuit.
Redundant logic circuit with destruction protection circuit 6. The device charging model ESD according to claim 1, wherein said redundant logic circuit is a NAND circuit.
Redundant logic circuit with destruction protection circuit 7. The redundant logic circuit according to claim 1, wherein a protection element having a function equivalent to a power supply protection element is added between a VDD terminal and a GND terminal for each of the redundant logic circuits. Redundant logic circuit with ESD protection circuit for device charging model