JPH03224237A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the limit of transistor occupation area reduction for securing mask alignment margine, reduce the occupied area, and increase the performance, by making it possible to determine the base contact width on the basis of the width of a side wall. CONSTITUTION:A first silicon nitride film 105, a first polycrystalline film 106, and a second silicon nitride film 107 are deposited on the upper layer of a P<-> type semiconductor substrate 101. The films 106 and 107 as the upper layers out of them are anisotropically etched and eliminated regarding to the region for forming an element isolation oxide film. After a side wall CVD oxide film 108 is formed on the side surfaces of the films 106, 107, the film 105 is anisotropically etched by using a two-layered film of the films 106, 107 and the film 108 as masks, and successively the films 104, 108 are eliminated. As the result, a pattern of the film 105 is obtained, which pattern is larger than a pattern of the two-layered film of the films 106, 107 by the width of the film 108. Thereby the consideration of mask alignment margine is unnecessitated, the transistor occupation area can be reduced by that amount, and the transistor performance can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a bipolar semiconductor device that is highly integrated and capable of high-speed operation.

(Prior Art) A conventional method for manufacturing a bipolar semiconductor device will be described with reference to FIG.

First, as shown in FIG. 2(A), a P-type semiconductor substrate 2 is
After forming an N-type buried diffusion layer 202 on the semiconductor substrate 01 and forming an N-type epitaxial layer 203 on the semiconductor substrate by epitaxial technology, a pad oxide film 204 is formed, and a silicon nitride film 205 is formed on its upper surface.

Next, a resist pattern (not shown) is formed on the silicon nitride film 205 using a known photolithography technique, and using this as a mask, the silicon nitride film 205 and the pad oxide film 204 are etched. 204 and silicon nitride film 205 as a mask, the N-type epitaxial layer 203 is selectively etched.
As shown in FIG. 2(B), trenches 206 are formed at positions where element isolation oxide films are to be formed later. By forming this groove 206, the N-type epitaxial layer 11203 has the first groove shown in the figure.
An island region 203a and a second island region (not shown) are formed.

Next, as shown in FIG. 2(c), thermal oxidation is performed to form the groove 20.
6 is a thick element isolation oxide film 207 made of silicon oxide film.
form.

Next, after removing the silicon nitride film 205, which is an oxidation-resistant mask, a resist mask (not shown) is formed and phosphorus is ion-implanted only into the second island region (not shown). By performing heat treatment in a neutral atmosphere, the second island region is made into an N9 type region for reducing collector resistance.

Next, after removing the pad oxide film 204, the entire surface is
A first polycrystalline silicon film 208 is formed as shown in FIG.

Further thermal oxidation is performed to form a polycrystalline silicon oxide film 209 on the surface of the first polycrystalline silicon film 208. Subsequently, boron ions are implanted into the first polycrystalline silicon H2O3, and then the resist pattern 210 is formed into polycrystalline silicon oxide WA20 using a known photolithography technique.
Form on 9.

Then, the polycrystalline silicon oxide film 209 is etched by anisotropic etching using the resist pattern 210 as a mask, and then the first polycrystalline silicon film 208 is etched, as shown in FIG. 2(E). Then, an opening 211 for forming an active base and an emitter is formed on the first island region 203a. After that, the resist pattern 210 is removed.

Next, the first island region 203a exposed by the opening formation
After oxidizing the surface thinly, a CVD oxide film 212 is formed on the entire surface as shown in FIG. 2(F). At this time, the first
First island region 203a in contact with polycrystalline silicon film 208
A highly doped inactive base region 213 is formed at the side end portion of the first polycrystalline silicon film 208 by diffusion of boron from the first polycrystalline silicon film 208 .

Next, by etching the CVD oxide film 212 by anisotropic etching, the first polycrystalline silicon film 208 in the opening 211 is etched, as shown in FIG.
CVD is applied to the side surfaces and the side surfaces of the polycrystalline silicon oxide film 209.
A sidewall 212a of the oxide film 212 is formed. Thereafter, boron ions are implanted into the first island region 203a through the opening 211 narrowed by the sidewall 212a, and heat treatment is performed in a non-oxidizing atmosphere to form the active base region 214 as shown in the figure. is formed within the first island region 203a.

Next, the active base region 214 within the first island region 203a
After removing the thin oxide film above and on the second island battle area (not shown), a second polycrystalline silicon film 215 is formed on the entire surface, and then arsenic is ion-implanted into the second polycrystalline silicon film 215. By patterning the second polycrystalline silicon film 215 using well-known photolithography and etching, the second polycrystalline silicon film 215 is formed into the opening 211 and its surrounding area, as shown in FIG. 2(H). The remaining second polycrystalline silicon film 215 is left as an emitter electrode on the N-type region (second island region) of the collector resistance reduction layer (not shown) as a collector electrode. After that, the surface of the remaining second polycrystalline silicon film 215 is thinly oxidized. By heat treatment in a non-oxidizing atmosphere, the second polycrystalline silicon 11215
Arsenic is diffused into the active base region 214 to form an emitter region 216 within the active base region 214.
With the above steps, the device is completed.

(Problems to be Solved by the Invention) However, in the conventional manufacturing method as described above, the first island region 203a inside the HIN region of the element formed in advance is ), since the polycrystalline silicon oxide film 209 and the first polycrystalline silicon film 20B have to be selectively etched by photolithography, it is necessary to ensure a margin for mask alignment in the first island region 203a. Island area 203 with a fraction of 1
a becomes larger. As a result, there is a limit to the reduction of the area occupied by the transistor, especially the junction capacitance C between the base and collector.
? . There was a problem in that it was difficult to reduce the amount.

The present invention solves the problem that there is a limit to reducing the area occupied by transistors due to the securing of mask alignment margins as described above, and provides a method for manufacturing a bipolar semiconductor device that can further reduce the area occupied by transistors and improve performance. The purpose is to

(Means for Solving the Problems) The present invention is capable of forming an inactive base region, an active base region, and an emitter region in a self-aligned manner after first performing a photolithography process once. be. Further, a three-layer film is formed on the semiconductor substrate, and the base contact width is determined by the width of a sidewall formed after patterning the upper two-layer film. In detail, the manufacturing method is as follows.

First, a first oxidation-resistant film is formed on the surface of a semiconductor substrate.

After the three-layer film of the first polycrystalline semiconductor layer and the second oxidation-resistant film is laminated, the upper two-layer film is patterned and left only on a predetermined region. After that, a first insulating film is deposited on the entire surface and then etched back to form a sidewall on the side surface of the two-layer film. After that, the first oxidation-resistant film is patterned using the two-layer film and the sidewall as a mask, and then the sidewall is removed. Thereafter, a groove having an undercut is formed under the first oxidation-resistant film in the exposed portion of the semiconductor substrate not covered with the remaining three-layer film, and the first polycrystalline semiconductor layer is side-etched. Then, a third oxidation-resistant film is selectively formed on the sidewalls of the trench and the sidewalls of the first polycrystalline semiconductor layer.
Next, by selectively oxidizing the semiconductor substrate using the first to third oxidation-resistant films as masks, an element isolation oxide film is formed in the trench. Thereafter, the entire second and third oxidation-resistant films and the first oxidation-resistant film in the portions not covered with the first polycrystalline semiconductor layer are removed. The first polycrystalline semiconductor layer and the first oxidation-resistant film on the island region of the semiconductor substrate surrounded by the film are used as masks to expose a part of the island region. forming a crystalline semiconductor layer in contact with and extending from the exposed portion of the island region; and removing the first polycrystalline semiconductor layer on the island region; A second conductivity type impurity is introduced into the crystalline semiconductor layer, and the second conductivity type impurity is introduced from the second polycrystalline semiconductor layer.
An inactive base region of a second conductivity type is formed in a part of the island region of the first conductivity type by diffusion of conductivity type impurities, and a second insulating film is formed on the surface of the second polycrystalline semiconductor layer. .

Next, after removing the first oxidation-resistant film on the island region, a third layer is formed on the end side surface of the second polycrystalline semiconductor layer and the end side surface of the second insulating film exposed in the removed portion. A side wall is formed using an insulating film. Then, a second conductivity type impurity is introduced into the island region through the removed portion narrowed by the sidewall to form an active base region extending to the inactive base region. Furthermore, a third polycrystalline semiconductor layer doped with a first conductivity type impurity is formed in the narrowed removed portion on the island region, and the first conductivity type impurity is diffused from the third polycrystalline semiconductor layer. , forming an emitter region of a first conductivity type within the active base region of the second conductivity type.

(Function) In the above invention, a photolithography process is required when patterning the upper two layers of the three layers formed on the surface of the semiconductor substrate. is advanced and inert base area with self-line,
All active base and emitter regions are formed. After patterning the upper two-layer film, a sidewall is added thereto, and the first oxidation-resistant film is patterned using the sidewalls as a mask. The base contact width (
A contact width between the second polycrystalline semiconductor layer and the island region is determined by the width of the sidewall. Therefore, in the present invention, there is no need to take mask alignment margin into consideration during the process.

(Example) An example of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1(A), a P-type semiconductor substrate 1 is
After forming an N-type buried diffusion layer 102 at 01, an N-type epitaxial layer 103 is formed on the semiconductor substrate, and the surface of this N-type epitaxial layer 103 is thermally oxidized to form a first pad oxide film 104 at 200. After forming the first silicon nitride film 105 to a thickness of approximately 2000 nm,
The first polycrystalline silicon film 106 is deposited by about 3,000 people, and the second silicon nitride film 107 is deposited thereon by about 4,000 people.

Next, as shown in FIG. 1(B), the second silicon nitride film 107 and the first polycrystalline silicon 111106 in a region where an element isolation oxide film is to be formed are etched by photolithography and RIE (reactive ion etching). are removed by sequential anisotropic etching.

Next, apply LP (low pressure) CVD or plasma CV to the entire surface.
For example, a CVD oxide film of 2,000 to 5,000 layers is deposited using D. Thereafter, the CVD oxide film is etched back, and a sidewall CVD oxide film 1 is formed on the side surfaces of the first polycrystalline silicon film 106 and the second silicon nitride film 107.
08 is formed. The cross-sectional view of the process at that time is shown in Figure 1(c).
Shown below.

Next, the two-layer film of the second silicon nitride film 107 and the first polycrystalline silicon film 106 and the sidewall CVD oxide film 1
08 as a mask, perform RIE as shown in Figure 1 (D).
The first silicon nitride film 105 is anisotropically etched using a method, and then the first pad oxide film 104 and sidewall CVD oxide film 108 in the same area are removed by wet etching.

As a result, the sidewall C
The first silicon nitride film 1 is larger by the width of the VD oxide film 10B.
A pattern 05 is obtained, and the positions of the side edges of both sides are shifted by the width of the sidewall CVD oxide film 108. Note that when the first silicon nitride film 105 is etched, the second silicon nitride film 107 is also etched at the same time, and since it is thick, it remains although it becomes thinner.

Next, as shown in FIG. 1(E), the N-type epitaxial layer 103 is etched from the portion where the first silicon nitride film 105 and the first pad oxide film 104 have been removed using a wet etching method, CF, or a series of gases. Grooves 109 are formed by plasma etching.

At this time, the groove 109 has a structure having an undercut portion under the first pad oxidation 111104 by side etching. Further, at this time, the first polycrystalline silicon film 106 is also side-etched in the same manner. Therefore, groove 1
09 (which can also be said to be the upper end of the side surfaces of the first and second island regions 103a and 103b of the epitaxial layer 103 surrounded by the groove 109) and the side surface of the first polycrystalline silicon film 106 are This results in a deviation by the width of the sidewall CVD oxide film 10B shown in FIG. 1(c). An enlarged cross-sectional view of this misaligned portion (particularly the circled area in FIG. 1(E)) is shown in FIG. 1(F). , the upper end of the side surface of the groove 109 (first and second island regions 103a).

103b) and the first polycrystalline silicon film 106
represents the difference in the side positions of
' is the width of the base contact. That is, the base contact width is determined by the width of the sidewall CVD oxide film 10B.

Also, by forming two side inches of the N-type epitaxial layer 103, a first silicon nitride film [105] and a first pad oxide film 1 are formed.
04 and the ends of the second silicon nitride film 107 become "eaves".

Next, after removing the first padded oxide film 104 under the "eaves", the inner wall of the trench 109 is thermally oxidized as shown in FIG.
~2000 people thick. At this time, the side walls of the first polycrystalline silicon film 106 are also thermally oxidized, and a polycrystalline silicon oxide film 111 is formed.

Thereafter, a third silicon nitride film 112 is deposited over the entire surface, for example, by 500 to 2000 people, using the LPCVD method or the plasma CVD method. At this time, these CVD methods have very good step coverage of the formed film, so the method shown in Figure 1 (G
) as shown in the first silicon nitride 1N! 205 and second silicon nitride! The third silicon nitride film 112 can cover the portions that are in the shadow of the "eaves" 11107.

After that, the third silicon nitride film 112 is formed by RIE method.
The etching is performed at the point when the third silicon nitride film 112 is etched, that is, at the point when the second pad oxide film 110 is exposed at the bottom of the groove 109, as shown in FIG. 1(H). make it stop. Then, as shown in FIG. 1(H), the first polycrystalline silicon r
l! ! A second silicon nitride film 107 remains on 106,
Also, on the side surface of the groove 109, 1 m of third silicon nitride! 11
2 will remain. Furthermore, the first polycrystalline silicon! 11
06 side and 1st. Second silicon nitride film 105.1
The third silicon nitride 11112 also remains in the "eaves" portion of 07. Such selective etching of the third silicon nitride film 112 is performed by etching the first and second silicon nitride films 105.10.
Using the "eaves" portion of No. 7 as a mask, it can be carried out on a self-aligned line without using a mask alignment process that impedes high integration.

After that, the first silicon nitride film 105. A thermal oxidation process is performed using the second silicon nitride film 107 and the third silicon nitride film 112 as masks, and an element isolation oxide film 113 is formed in the groove portion as shown in FIG. 1 (summer). At this time, the oxide film is
Growing below the third silicon nitride film 112, and the third silicon nitride! The lA 112 is lifted upward, and at the same time, the cross-sectional shape of the oxide film becomes nearly vertical. Therefore, the first layer which is the epitaxial layer portion surrounded by the element isolation oxide film 113. Second island area 103a, 103
b, there is no intrusion of the oxide film such as a bird's beak, and no steps such as a bird's head are formed.
12 is formed, so the first polycrystalline silicon! ! l
1106 is not oxidized, therefore the first. The positions of the side edges of the second island regions 103a and 103b and the side surfaces of the first polycrystalline silicon film 106 are not affected by the thermal oxidation treatment for forming the element isolation oxide film 113 and do not change.

Next, as shown in FIG. 1 (J), the third silicon nitride!
1112 and second silicon nitride! 11107 and the L-th silicon nitride film 105 except under the first polycrystalline silicon film 106, and then remove the first polycrystalline silicon film 106.
The polycrystalline silicon oxide film 111 on the side surfaces is removed.

Next, the first polycrystalline silicon film 106 and the first silicon nitride film 105 on the second island MfItIoSb are removed by photolithography. Next, as shown in FIG. 10[), a second island region 103b is formed using the resist pattern 114 as a mask.
Phosphorus is ion-implanted, for example, in an amount of about 1×1oI4CI-''.

Next, after removing the resist pattern 114, heat treatment is performed in a non-oxidizing atmosphere as shown in FIG.
Deep collector region 11 for reducing collector resistance reaching
5.

Next, the first polycrystalline silicon I on the first island region 103a
M! 106 and the first pad oxide film 104 on the portions not covered with the first silicon nitride film 105 and the first pad oxide film 104 on the deep collector region 115.
As shown in FIG. 1(M), the sidewall CVD oxide film 1 of FIG. 1(c) is removed in the first island region 103a.
After exposing the surface by a width of 0B, a second polycrystalline silicon film 116 of, for example, 3000 to 5000 times is deposited on the entire surface.
Furthermore, as shown in the figure, the island area 10 is
A dummy resist pattern 124 for planarization is formed so as to surround the convex portion on 3a. Subsequently, after applying resist again and flattening the resist surface, the second polycrystalline silicon 111 of the convex portion on the island region 103a is etched under conditions such that the etching rate of the resist and the polycrystalline silicon are equal.
116 and the first polycrystalline silicon film 106 are etched by anisotropic etching until the first silicon nitride film 105 is exposed, and then the remaining resist is removed.

Through this process, the first polycrystalline silicon film 111106 is completely removed as shown in FIG. the first island region 1 in contact with
03a will remain as if extending.

Next, after the surface of the second polycrystalline silicon film 116 is thinly oxidized, boron ions are implanted into the second' polycrystalline silicon film 116 at a dose of, for example, 1 to 5.times.10 IScl. Subsequently, as shown in FIG. 1(0), the second polycrystalline silicon film 116 other than the base extraction electrode region is removed by photolithography.

Next, heat treatment is performed to form a second polycrystalline silicon film 116 in the first island region 103a, as shown in FIG. 1(0).
An inactive base region 119 is formed by diffusion of boron from
A polycrystalline silicon oxide film 117 is formed on the surface of 16.

At this time, the surface of the deep collector region 115 is also oxidized and a deep collector oxide film 118 is also formed. Next, as shown in FIG. After removing all of the first silicon nitride film 105, a fourth silicon nitride film 120 is deposited on the entire surface by LPCVD.

Next, as shown in FIG. 1(P), the fourth
The silicon nitride film 120 is etched, and the second polycrystalline silicon film 116 and polycrystalline silicon oxide 11117 are etched.
A sidewall silicon nitride film 120a is formed on the side surface of the substrate. This sidewall silicon nitride film 120a narrows the opening in the portion where the first silicon nitride film 105 on the first island region 103a is removed. Then, boron ions of approximately 0.5 to 1X10"C11-" are implanted into the first island region 103a through the narrowed opening and the first padded oxide film 104.
By performing annealing at a temperature of 900 to 950°C,
As shown in FIG. 1(P), an active base region 121 is formed in the first island region 103a so as to extend to the inactive base region 119.

Next, the first pad oxide film 10 on the active base region 121 is
After removing 4 and deep collector oxide M11B, a third polycrystalline silicon film 122 of, for example, 3,000 to 5,000 layers is deposited on the entire surface as shown in FIG. 1(Q).

Subsequently, after oxidizing the surface of the third polycrystalline silicon film 122 by approximately 200 layers, this third polycrystalline silicon film 11112
2, arsenic ions are implanted to the extent of 1 to 2XIQ cm-. Thereafter, a third polycrystalline silicon film 122 is formed by photolithography.
As shown in FIG. 1(R), the third polycrystalline silicon film 122 is left on the deep collector region 115 as a collector electrode, and the first polycrystalline silicon film 122 on the first island region 103a is etched as an emitter electrode. The silicon nitride film is left in the removed portion and its surrounding area, and then heat treatment is performed to diffuse arsenic from the remaining third polycrystalline silicon film 122 on the first island region 103a, resulting in the formation of the silicon nitride film shown in FIG. 1(R).
As shown in FIG.
The element is completed with 0 or more formed in 1.

(Effects of the Invention) As explained in detail above, according to the manufacturing method of the present invention, in the three-layer film initially formed on the surface of the semiconductor substrate,
Although a photolithography process is required when patterning the upper two-layer film, the subsequent process is performed using the Selfa line, and the inactive base region, active base region, and emitter region are all formed using the Selfa line. Furthermore, the base contact width can be determined by the width of the sidewall formed after patterning the upper two-layer film. therefore,
There is no need to take any mask alignment allowance into consideration during the process, and the transistor exclusive area (island area area) can be reduced by the mask alignment allowance. By reducing the area, it is possible to improve the performance of the transistor, such as by reducing the base-collector junction capacitance.

Note that, in practice, as shown in the examples, in order to form a deep collector region or to remove unnecessary portions of the second polycrystalline semiconductor layer (second polycrystalline silicon film 116), Alternatively, a photolithography process is required to form the third polycrystalline semiconductor layer (third polycrystalline silicon film 122) in the opening portion, but these photolithography processes are limited to the area of the island region. The inactive base region, the active base region, and the emitter region can be formed with self-aligned lines without any influence and independently of these photolithography steps.

Further, according to the manufacturing method of the present invention, the third oxidation-resistant film is formed on the side surface of the side-etched groove of the semiconductor substrate using the first oxidation-resistant film as a mask, and the elements are isolated by selective oxidation. Since an oxide film is formed, there is an advantage that a good element isolation oxide film can be formed without invasion of the oxide film such as bird's beaks or steps such as bird's heads.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a bipolar semiconductor device according to the present invention, and FIG. 2 is a process sectional view showing a conventional manufacturing method. 101... P- type semiconductor substrate, 103... N- type epitaxial layer, 105... first silicon nitride film, 1
06... First polycrystalline silicon film, 107... Second silicon nitride film, 108... Side wall CVD oxide film, 109... Groove, 112... Third silicon nitride film, 113... - Element isolation oxide film, 116... second polycrystalline silicon film, 11'7... polycrystalline silicon oxide film,
119...Inactive base region, 120a...Side wall silicon nitride film, 121...Active base region, 122...Third polycrystalline silicon film, 3...Ivy region. ! ψ N = \

Claims (1)

Scope of Claims: (a) After laminating three layers of a first oxidation-resistant film, a first polycrystalline semiconductor layer, and a second oxidation-resistant film on the surface of a semiconductor substrate, two of the upper layers are stacked. (b) After that, after depositing a first insulating film on the entire surface, etching back is performed to form sidewalls on the sides of the two-layer film. (c) After that, patterning the first oxidation-resistant film using the two-layer film and the sidewall as a mask, and then removing the sidewall; and (d) Then, patterning the first oxidation-resistant film with the remaining three-layer film as a mask. A groove having an undercut is formed under the first oxidation-resistant film in an exposed portion of the semiconductor substrate that is not covered, and the first polycrystalline semiconductor layer is side-etched to form a first polycrystalline semiconductor layer. (e) selectively forming a third oxidation-resistant film on the side walls of the trench and the side surfaces of the first polycrystalline semiconductor layer; (f) recessing the side surfaces of the semiconductor layer; (g) forming an element isolation oxide film in the trench by selectively oxidizing the semiconductor substrate using the first to third oxidation-resistant films as masks;
and (h) removing the entire third oxidation resistant film and the portions of the first oxidation resistant film not covered with the first polycrystalline semiconductor layer; and (h) removing the element isolation oxide film. (i) exposing a part of the island region using the first polycrystalline semiconductor layer and the first oxidation-resistant film on the surrounded island region of the semiconductor substrate as a mask; forming a crystalline semiconductor layer in contact with and extending from the exposed portion of the island region, and removing the first polycrystalline semiconductor layer on the island region; (j) the step of removing the first polycrystalline semiconductor layer on the island region; Impurities of a second conductivity type are introduced into the polycrystalline semiconductor layers of 12 polycrystalline semiconductor layers, and by diffusion of the impurities of the second conductivity type from the 12 polycrystalline semiconductor layers, a part of the island region of the first conductivity type is made to have a second conductivity. (k) removing the first oxidation-resistant film on the island region; (l) forming a sidewall of a third insulating film on the end side surface of the second polycrystalline semiconductor layer and the end side surface of the second insulating film exposed in the removed portion; (l) the sidewall; (m) introducing a second conductivity type impurity into the island region through the narrowed removed portion to form an active base region extending into the inactive base region; A third polycrystalline semiconductor layer doped with a first conductivity type impurity is formed in the removed portion, and the first conductivity type emitter region is formed by diffusion of the first conductivity type impurity from the third polycrystalline semiconductor layer. A method of manufacturing a bipolar semiconductor device, comprising the step of forming the active base region in the second conductivity type active base region.