JPH01181465A - Manufacture of ultra-high speed semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] S is considered to be a powerful technology for manufacturing ultra-high-speed semiconductor devices.
Regarding the manufacturing method of semiconductor devices that eliminates the disadvantages of ST or ESPER, we aim to eliminate the disadvantages of the SST process and ESPER process and enjoy only the advantages of both, that is, with a small number of steps and easily. For the purpose of manufacturing ultra-high-speed semiconductor devices, a silicon carbide film, an insulating film, and an element region lead-out wiring layer made of polycrystalline silicon are sequentially formed on a silicon semiconductor substrate (or silicon semiconductor layer). Next, a step of forming an insulating film 1ii1 region on the element region lead-out wiring layer and then forming an insulating film on the entire surface, and then forming an opening reaching the silicon carbide film from the surface and passing through the opening. a step of forming a conductive film connecting the silicon carbide film and the element region lead-out wiring layer, and then an element lead-out wiring layer connecting the silicon carbide film and a part of the element region lead-out wiring layer through the opening. Next, there is a step of sequentially forming a polycrystalline silicon layer that serves as an insulating film and a substrate, and an insulating film that can withstand silicon etching solution. The method is configured to include a step of exposing the film.

[Industrial application field]

The present invention is based on SST (super self-aligning technology), which is considered to be a powerful technology for manufacturing ultra-high-speed semiconductor devices.
ned technology) or ESPER (
emitter base seIf-align
with polysilicon 5lec
The present invention relates to a method for manufacturing a semiconductor device that eliminates drawbacks such as trades a, nd registers).

[Conventional technology]

FIG. 14 shows a cutaway side view of essential parts of an ultrahigh-speed bipolar semiconductor device manufactured by a standard SST process.

In the figure, 20 is an n-type silicon semiconductor substrate, 21 is a field insulating film made of silicon dioxide (SiOz),
22 is an insulating film made of silicon dioxide that covers the active region;
23 is an insulating film made of silicon nitride (S i 3N4), 24 is a p-type polycrystalline silicon base lead-out wiring layer,
25 is an insulating film made of silicon dioxide, 26 is an insulating film made of silicon dioxide, 27 is a p-type polycrystalline silicon contact layer for electrically connecting between the semiconductor substrate 20 and the base wiring layer 24, and 28 is a p-type polycrystalline silicon contact layer. 29 is an insulating film made of silicon dioxide, 30 is an n-type polycrystalline silicon film, 31 is an n-type polycrystalline silicon emitter electrode, 32 is a p-type external base region, and 33 is an n-type emitter region. It shows.

When manufacturing this semiconductor device, it is necessary to form an opening that penetrates the base lead-out wiring layer 24 in the area where the internal base region 28 and emitter region 33 are planned to be formed. Since there is an insulating film 23 made of silicon nitride that is not etched, the etching can be automatically stopped and the reproducibility is very good. Further, the relationship between the internal base region 28 and the external base region 32 is determined by the side etching of the insulating film 23 that is performed after the opening is bored and the internal base region 28 is formed.
Since there is no misalignment and it is formed in a self-aligned manner, it is suitable for forming a fine base that is effective for increasing the speed of semiconductor devices.

FIG. 15 shows a cutaway side view of essential parts of an ultrahigh-speed bipolar semiconductor device manufactured by the standard ESPER process.

In the figure, 51 is an n-type silicon semiconductor substrate, 52 is a field insulating film made of silicon dioxide, 53 is a p-type polycrystalline silicon base lead wiring layer, 54 is an insulating film made of silicon dioxide, and 55 is made of silicon dioxide. 56 is a p-type internal base region, 57 is an insulating film made of silicon dioxide, 58 is an n-type polycrystalline silicon film, 5
Reference numeral 9 indicates an n-type polycrystalline silicon emitter electrode, 60 an n-type emitter region, and 61 a p-type external base region.

When manufacturing this semiconductor device, the base lead-out wiring layer 5
There is no insulating film made of silicon nitride or insulating film made of silicon dioxide on the base of 3.
There is no need for etching or the formation of a polycrystalline silicon contact layer for conductive connection between the semiconductor substrate 51 and the base lead-out wiring layer 53, and the number of steps is considerably reduced compared to the SST process explained with reference to FIG. do.

[Problem to be solved by the invention] When relying on the SST process explained with reference to FIG.
An insulating film 23 made of silicon nitride and an insulating film 22 made of silicon dioxide are formed on the base of the base lead-out wiring layer 24 , and their sides are etched to form a conductive connection between the semiconductor substrate 20 and the base lead-out wiring layer 24 . It is necessary to form a polycrystalline silicon contact layer 27, etc., and the number of steps involved is considerably increased compared to manufacturing a normal bipolar semiconductor device.

In the case of using the ESPER process described with reference to FIG. 15, when forming an opening penetrating the base lead wiring layer 53 in the portion where the internal base region 56 and the emitter region 60 are planned to be formed, an insulating layer made of silicon nitride is used as the base. Since there is no film, there is a risk that even the semiconductor substrate 51 will be etched, which is difficult to control, and the relative relationship between the internal base region 56 and the external base region 61 is
Since it is not determined by a self-alignment method like the ST process, alignment margin is required for its formation, and therefore, the base cannot be miniaturized.
It cannot be expected to reduce the parasitic junction capacitance between the base and the collector, which is disadvantageous for increasing speed.

The present invention seeks to eliminate the shortcomings in the SST process and the ESPER process, allowing only the advantages of both to be enjoyed.

[Means to solve the problem]

In the method for manufacturing an ultra-high-speed semiconductor device according to the present invention,
A silicon carbide film (e.g., silicon carbide film 2), an insulating film (e.g., insulating film 3), and an element region lead-out wiring layer (e.g., lead-out wiring layer 4) made of polycrystalline silicon are formed on a silicon semiconductor substrate (e.g., silicon semi-dead substrate 1). Next, a step of forming an insulating isolation region (for example, an insulating isolation region 5) on the element region lead-out wiring layer and then forming an insulating film (for example, an insulating film 6) on the entire surface; A conductive film (for example, polycrystalline silicon film 7) that forms an opening (for example, opening 3A) reaching the silicon carbide film from the top and connects the silicon carbide film and the element region lead-out wiring layer through the opening.
a step of forming an element region lead-out wiring layer (for example, lead-out wiring layer 9) that connects the silicon carbide film and a part of the element region lead-out wiring layer through the opening; A step of sequentially forming an insulating film (for example, an insulating film 10), a polycrystalline silicon layer (for example, a polycrystalline silicon layer 11) serving as a substrate, and an insulating film (for example, an insulating film 12) that can withstand silicon etching solution; , a step of completely removing the silicon semiconductor substrate to expose the silicon carbide film.

[Effect]

By adopting the above-mentioned means, it is possible to easily manufacture a high-speed and highly integrated semiconductor device with a fewer number of steps than manufacturing with the SST process and with a process that is significantly more stable than the ESPER process. Can be done.

[Embodiment] FIGS. 1 to 11 show cutaway side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. do.

Refer to FIG. 1 (1) By applying the M-pressure vapor phase epitaxial growth method, a layer with a thickness of, for example, 1.
A silicon carbide (S i C) film 2 having a thickness of approximately 500 people is formed.This silicon carbide film 2 is preferably a β silicon carbide film.

See Figure 2 (2) Chemical vapor deposition
p.

By applying the CVD method, an insulating film 3 made of silicon dioxide is formed to a thickness of, for example, about 2,000 mm, and by applying the same CVD method, it is formed to a thickness of, for example, about 3,000 mm. ] A lead wiring layer 4 such as an emitter and a base made of polycrystalline silicon is formed.

(By applying the 31CVD method, a thickness of, for example, 1500 mm, which serves as an oxidation-resistant mask when performing the selective oxidation method
Insulating film made of silicon nitride (not shown)
Then, by applying a normal photolithography technique, the insulating film made of silicon nitride is selectively etched to expose a part of the surface of the lead-out wiring layer 4 in the area where the insulating isolation region is to be formed. An insulating isolation region 5 made of silicon dioxide is formed by forming an opening and applying a thermal oxidation method.

(4) After removing the insulating film made of silicon nitride used as an oxidation-resistant mask, a resist process of photolithography is applied to form an opening in the area where the base region is to be formed. Boron ions are implanted by forming an ion implantation mask (not shown) having an ion implantation mask and applying an ion implantation method. In this case, the implantation energy is, for example, about 40 (KeV), and the dose is, for example, 5
It may be about 10I5 ((J-'')).

Next, after removing the ion implantation mask, an ion implantation mask (not shown) having an opening in the area where the emitter region is to be formed is formed in the same manner as described above, and by applying the ion implantation method, phosphorus ions are added. Type in the information. In this case, the implantation energy is, for example, 70 (KaV
), and the dose amount is, for example, 5×lO 5 (
cm-”) may be used.

Then, by applying the CVD method, a thickness of, for example, 3
000 (person) insulating film 6 made of silicon dioxide
form.

See Figure 3 (5) Resist process and reactive ion etching (reac) in normal photolithography technology.
By applying a tive ion etching (RIE) method, the insulating film 6, the lead wiring layer 4, and the insulating film 3 are selectively etched to form an opening 3A in a portion where the collector region is to be formed.

Note that this etching automatically stops at the surface of silicon carbide film 2.

See Figure 4 (by applying the 61CVD method, the thickness, for example, 30
A polycrystalline silicon film 7 having a thickness of approximately 0.00 (person) is formed.

Refer to FIG. 5 (7) By performing anisotropic etching of the polycrystalline silicon film 7 using the RIE method, the polycrystalline silicon film 7 is left only on the inner wall of the opening 3A.

(8) In a humid oxidizing atmosphere, the temperature is set to 1000 (').
C) heat treatment for about 60 [minutes],
The thickness covering the polycrystalline silicon film 7 is, for example, 2000 (people)
An insulating film 8 made of silicon dioxide is formed. At this time, the exposed silicon carbide film 2 is also slightly oxidized to produce an extremely thin insulating film.

See FIG. 7 (9) The thin insulating film covering the silicon carbide film 2 is removed by applying a dipping method using hydronic acid as an etchant.

α [By applying photolithography technology,
After selectively etching the insulating film 6 and forming an opening in the area where the emitter region is to be formed, by applying the CVD method, an emitter lead-out wiring layer made of polycrystalline silicon with a thickness of, for example, about 3,000 mm is formed. form 9.

Next, phosphorus ions are implanted by applying an ion implantation method, and then heat treatment is performed for activation to convert the lead wiring layer 9 to n-type. In this case, the implantation energy is, for example, about 70 (KeV), the dose is, for example, about 5 x 1015 (Cm-''), the heat treatment temperature is, for example, about 900 ('C), and the heat treatment time is, for example, It may be about 30 [minutes].

Next, patterning of the lead wiring N9 is performed by applying photolithography technology.

Refer to Figure 8. By applying the CVD method, the thickness, for example, 20
Insulating film 10 made of silicon dioxide of about 00 (person)
form.

Next, by applying the same CVD method, a polycrystalline silicon layer 11 with a thickness of, for example, about 600 [μm] is formed. Since this polycrystalline silicon layer 11 plays the role of a substrate, the same A certain thickness is required.

Next, by applying the same CVD method, an insulating film 12 made of silicon nitride is formed to a thickness of, for example, about 2000 (layers).

See Figure 9 Silicon etching solution, e.g. HF+N03
The substrate 1 is removed by applying a dipping method using a mixed solution as an etchant. At this time, silicon carbide film 2 and insulating film 12 serve as protection against the etchant. still,
The figure shows the state inverted after the substrate 1 has been removed.

Referring to FIG. 10, a contact layer 13 made of polycrystalline silicon containing n-type impurities is formed to a thickness of, for example, about 500 [layers] by applying the CVD method.

Next, resist and photolithography technology
By applying the process and RIE method, the contact layer 13 made of polycrystalline silicon and the silicon carbide film 2 are patterned to form a mesa shape.

Refer to FIG. 11 α4) By applying the CVD method, an insulating film 14 made of silicon dioxide is formed to a thickness of, for example, about 2000 μm.

Then, the temperature is eg 1000C and the time is eg 30C.
Perform heat treatment for [minutes].

Next, the insulating film 14 and the insulating film 4 are selectively etched by applying a normal photolithography technique to form an electrode contact window.

Next, by applying a vacuum evaporation method and photolithography technology, an aluminum film is formed and patterned to form an emitter electrode 15 and a base electrode 1.
6. Form the collector electrode 17.

The features of the embodiment described above are listed below.

(a) In step (5), the insulating film 6, the lead-out wiring layer 4,
When selectively etching the insulating film 3 to form the opening 3A in the portion where the collector region is to be formed, the silicon carbide film 2 plays the role of an etching stopper, making it possible to perform stable processing with good reproducibility. can.

(bl) Based on the difference in oxidation rate between polycrystalline silicon and silicon carbide, only the surface of silicon carbide film 20 can be selectively exposed, reducing the number of steps and reducing both the base area and emitter area. As a result, the emitter-base or base-collector parasitic capacitance can be reduced, and higher speeds of the device can be expected.

(C) Using the silicon carbide film 2 as an etching stopper, the entire semiconductor substrate 1 is removed, and 5OI (silicon
On 1 nsulator) structure, we have realized a structure in which a silicon carbide film, which electrically functions in the same way as a silicon layer, exists on an insulating substrate.
Normally, all parasitic capacitance that exists between the silicon semiconductor substrate and the silicon semiconductor substrate is eliminated, which is effective in increasing speed.

(dl Structure initially formed on silicon carbide film 2,
For example, the base lead-out wiring layer 4, the insulation isolation region 5, the emitter lead-out wiring layer 9, etc. are ultimately buried under the silicon carbide film 2, and surface flatness is very important. , problems such as disconnection do not occur even if multilayer wiring is applied.

(Q) After the semiconductor substrate 1 is removed, the polycrystalline silicon layer 11 plays the role of a substrate and passes through the process.Usually, when a polycrystalline silicon layer is used as a substrate, it is slower than an epitaxially grown silicon substrate. It cracks easily and bends easily during heat treatment.

However, in the process of the above embodiment, the semiconductor substrate 1
Since most of the heat treatment is completed while the semiconductor substrate 1 is still present, the above-mentioned problems can be avoided, and since the formation of minute openings is also performed while the semiconductor substrate 1 is still present,
The problem of difficulty in positioning due to warping does not occur.

(f) Buried layers, isolation between elements, which were absolutely necessary in conventional bipolar semiconductor devices using conventional technology.
Since there is no need for the process of forming a collector diffusion layer, etc.
The number of steps is significantly reduced.

(Illusion) As mentioned above, since isolation between elements is not required, it is advantageous for high integration.

By the way, the present invention relates to a static induction transistor (Stati
c 1induction transition
r:5IT), and will be explained next.

Figures 12 and 13 are enlarged cut-away side views of essential parts for explaining SIT, and the same symbols as those used in Figures 1 to 11 indicate the same parts or have the same meanings. shall be taken as a thing.

In the figure, 18 is a p-type source region, 19 is an n++ gate region, 20 is an n+-type drain region e is an electron, and DL is a depletion layer.

In this embodiment, the collector electrode 17 operates as a drain electrode, and although not shown, the emitter electrode 15
The base electrode 16 functions as a source electrode, and the base electrode 16 functions as a gate electrode, and the thickness of silicon carbide film 2 is set to be less than or equal to the mean free path of electrons e.

FIG. 12 shows the case where SIT is on, and as mentioned above, in this example, since the thickness of silicon carbide film 2 is less than the mean free path of electrons, electron e The light travels from the source region 18 to the drain region 20 with almost no scattering, producing a so-called parisistic effect.

FIG. 13 shows a case where the SIT is turned off, and a depletion layer DL has expanded in the n″″ type silicon carbide film 2, and there are no electrons traveling from the source region 18 to the drain region 20.

Similarly to the bipolar semiconductor device described with reference to FIGS. 1 to 11, the SIT described here is easy to manufacture and can enjoy advantages such as a small number of steps. , which is super fast.

〔Effect of the invention〕

In the method for manufacturing an ultra-high-speed semiconductor device according to the present invention,
A silicon carbide film, an insulating film, and an element region lead wiring layer made of polycrystalline silicon are sequentially formed on a silicon semiconductor substrate, an insulating isolation region is formed in the element region lead wiring layer, and then an insulating film is formed on the entire surface. , forming an opening reaching the silicon carbide film from the surface, forming a conductive film connecting the silicon carbide film and the element region lead-out wiring layer through the opening, and connecting the silicon carbide film and the element region through the opening; An element lead-out wiring layer is formed to connect a part of the lead-out wiring layer, and a polycrystalline silicon layer that serves as an insulating film and a substrate, and an insulating film that is resistant to silicon etching solution are formed in order, and the entire silicon semiconductor substrate is completely removed. It is removed to expose the silicon carbide film.

By employing the above structure, it is possible to easily manufacture a high-speed and highly integrated semiconductor device with a fewer number of steps than manufacturing with the SST process and with a process that is much more stable than the ESPER process. Can be done.

[Brief explanation of the drawing]

1 to 11 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIGS. 12 and 13 are side views for explaining another embodiment of the present invention. 14 and 15 are cross-sectional side views of essential parts of a semiconductor device at key points in the process.
Each figure shows a cutaway side view of a main part of a semiconductor device for explaining a conventional example. In the figure, l is a silicon semiconductor substrate, 2 is a silicon carbide film, 3 is an insulating film, 3A is an opening, 4 is a polycrystalline silicon lead wiring layer, 5 is an isolation region, 6 is an insulating film, and 7 is a polycrystalline silicon layer. a crystalline silicon film, 8 an insulating film, 9 a polycrystalline silicon lead wiring layer, 10 an insulating film, 11 a polycrystalline silicon layer,
12 is an insulating film, 13 is a contact layer, 14 is an insulating film,
15 is an emitter electrode, 16 is a base electrode, and 17 is a collector electrode. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Fig. 3 Fig. 4 Fig. 7 Copper 8 Fig. 11 Scabbard 12 Fig. 13 Cut side view of main parts of conventional example Figure 14

Claims (1)

[Scope of Claims] A step of sequentially forming a silicon carbide film, an insulating film, and an element region lead-out wiring layer made of polycrystalline silicon on a silicon semiconductor substrate (or silicon semiconductor layer); forming an insulating isolation region on the surface and then forming an insulating film on the entire surface, and then forming an opening reaching the silicon carbide film from the surface and connecting the silicon carbide film and the element region lead-out wiring layer through the opening. a step of forming a conductive film that connects the silicon carbide film and a part of the device region lead-out wiring layer through the opening; The method includes the steps of sequentially forming a polycrystalline silicon layer and an insulating film that can withstand silicon etching solution, and then removing all of the silicon semiconductor substrate to expose the silicon carbide film. A method for manufacturing an ultra-high-speed semiconductor device characterized by: