JPH03184146A - Parity check method - Google Patents

Abstract

PURPOSE:To omit a parity-only memory and to attain the reduction of the cost for a parity check method by providing both data and parity areas to a memory part where the data are written and read out and applying a parity check to the memory space. CONSTITUTION:A memory part 3 includes a data area 6 and a parity area 7. When data are written in a the area 6, these data are divided every four bits and a parity is calculated every four bits. Then the prescribed bit data obtained every four bits of the prescribed parity data of the area 7 are rewritten with four calculated parities. At the same time, when data are read out of the area 6, the parity data corresponding to the reading data of the area 6 are read out. The prescribed bit data obtained every four bits from the parity data are compared with the parities calculated based on the data obtained every four bits of the prescribed data. Thus the data parity check is performed. In such a constitution, no parity-only memory is required and an area where no memory is used can be used as a parity area.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parity check method that obtains parity based on data and performs a parity check using this parity and data. The present invention relates to a parity checking method that performs processing in a memory space of .

[Conventional example] Conventionally, when writing or reading data in a computer, etc., a parity bit is added to the most significant bit of the data, but this parity bit always makes the total number of "1"s in the data an even or odd number. Data is checked using this even or odd number.

Therefore, as shown in FIG.
When data is written to the memory section (for example, RAM) 3 via the data bus 2 at the PUI.

A parity generation/checking circuit 4 generates parity in which the total number of "1"s in the data is an even or odd number, and this parity is stored in a parity RAM (DRAM) 5. Then, when data transfer is performed on the CPUI,
In other words, when the data in the memory section 3 is read out via the data bus 2, the value obtained based on the data in the parity generation/checking circuit 4 is compared with the value read out from the parity RAM 5, and if they do not match, the value is compared. An error is generated and an interrupt signal is output to the CPUI.

As a result, the interrupt can be used to stop data transfer using the CPUI.

[Problem to be solved by the invention] However, in the above parity circuit.

In addition to the memory section 3, a new parity RAM section 5 is required, which means that at least one memory must be added, resulting in an increase in cost.

Furthermore, recent memory elements 1, such as DRAMs, have a tendency to increase in capacity, and it has become difficult to obtain small capacity DRAMs. Therefore, even in the case of a small system, a large-capacity DRAM is used for the memory section 3 and the parity DRAM 5, which not only does not effectively utilize the DRAM, but also causes uneconomical aspects.

The present invention was made in view of the above problems, and its purpose is to provide a parity check method that reduces costs and makes effective use of memory.

Means for Solving Problem C] In order to achieve the above object, the present invention provides a parity checking method for writing data into a memory, reading data from the memory, and checking the parity of this data. providing a data area and a parity area, and when writing data to the data area, rewriting predetermined bit data of parity data corresponding to a predetermined address of the parity area with parity calculated based on the data to be written; When reading the data in the data area, the parity data corresponding to the read data is read out, and the predetermined bit data of this parity data is compared with the parity calculated based on the data to perform a parity check on the data. The main points are as follows.

Furthermore, when writing the above data, parity is calculated for each 4-bit unit of the above data, the parity data is read out, and the bit data at predetermined bit intervals of this parity data is rewritten with the four parities calculated above. This is what I did.

[Operation] With the above method, parity is generated based on the data when writing the data into the memory. Then, data is written into the data area of the memory, and 1-bit data of predetermined parity data in a parity area provided in the same space as the memory of the data area is rewritten with the generated parity.

Also, when reading data from the data area.

Parity is generated based on that data. and,
Parity data corresponding to the data is read out, and predetermined 1-bit data of this parity data is compared with the generated parity. The result of this comparison generates an error and interrupts the CPU.

[Example] Hereinafter, an example of the present invention will be described based on FIGS. 1 to 5. In FIG. 1, the same parts and corresponding parts as in FIG. 6 are denoted by the same reference numerals, and redundant explanation will be omitted.

In FIG. 1, the memory section 3 is provided with a data area 6 for writing and reading data, and a parity area 7 for writing parity generated based on the data to be written. In addition, in the data area 6 and parity area 7, the memory section 3 is composed of four DRAMs (4 bits) 8a, 8b, 8c, and 8d, as shown in FIGS. , the data address changes from “00000(l()” to “5FFF”)
F(H)”.

Parity address is from “60000(H)” to “7F”
FFF(H)", and the 0th, 4th, 8th, and 12th bits of parity data are calculated based on data from addresses 00000(H) to IFFFF(H). rewritten with parity,
The 1st, 5th, 9th, and 13th bits of parity data are from address 20000 (H).
It is rewritten with parity generated based on the data written to 3FFFF(H), and the 2nd, 6th, 10th, and 14th bits of parity data are written from address 40000(H) to 6FFFF()I. )
It is rewritten with parity generated based on the data written to. Moreover, as shown by the arrow in Figure 2, the parity generated based on the 4-bit data from the 0th bit to the 3rd bit is
The 13th bit of the parity data is rewritten, and the parity generated based on the 4-bit data from the 4th bit to the 7th bit is rewritten, and the parity is generated based on the 4-bit data from the 8th bit to the 11th bit. In the parity generated based on the 4-bit data from the 12th bit to the 15th bit, the 5th bit of the parity data is rewritten. That is, DRAM (A, B, C) into which 4 bits of data are written each.

D) DRAM (A,
B, C, D) are different from 8a, 8b, 8c, and 8d.

Next, the operation of the parity check method applied to the parity circuit including the memory section 3 will be explained based on the time charts of FIGS. 4 and 5.

Note that the data has a 16-bit configuration, and 4 of the data
It is assumed that parity is required for each bit.

Furthermore, when writing and reading data and parity to and from the four DRAMs 8a, 8b, 8c, and 8d, the page mode cycles of the DRAMs 8a, 8b, 8c, and 8d are utilized. Furthermore, in the page mode cycle, RAS and CAS are generated to access the memory, as shown in FIGS. 4(b) to 5(d) and 5(b) to (d). Ori, R.A.S.
The row address (A, s to A
, ) is given, the first falling timing of CAS is given, and that address becomes the column address (A1
□A, , A, to A,). That is, the space in the memory section 3 is used as a normal data memory (data area 6). Also, at the next falling timing of CAS, the column address “'H” (At*L
"H" (A t t ) -A is switched to A, and the space in the memory section 3 is changed from 6000 (H) to 7FFF.
F(H), and this space is used as a parity memory (parity area 7).

First, based on the page mode cycle shown in FIG.
For example, data “0110” is stored at address 28020()I).
...'' is written, that is, 0
The 4-bit data from the 3rd bit to the 3rd bit is “01”.
10", the CPU 1 generates RAS, and at the falling timing of this RAS, the data on the data bus 2 is transferred to the data area 6 at address 28020 (H).
(shown in (g) of the same figure).

That is, as mentioned above, the address is 28020 (H
), and the WE multiplied signal is set to the "L" level (as shown in FIG. 4(e)).

Subsequently, as shown in (f) of the same figure, the parity data of the parity area 7 is read out at the timing of the OE multiplied signal "L" level output from the CPU 1 (as shown in (g) of the same figure). At this time, as mentioned above, the address is 68020(l(,), and this address 6802
Parity data "..." of 0 (II) is read out.

On the other hand, when writing the data, parity is generated based on the data in a parity generation/check circuit 1114. In this case, since parity is generated in units of 4 bits of the data, the 4-bit data from the 0th bit to the 3rd bit is "0110", so
The parity of the 4-bit data is “O”, and
Similarly, parity is generated for the remaining four 4-bit data. Note that the parity is such that the total number of "1"s in the data is an even number. After writing the data, the generated parity is rewritten. At this time, since the address is 68020 (H) after the next fall of the above WE multiplied signal, that is, at the "L" level again, the 9th bit of the read parity data is 3rd from the O bit. The generated parity is rewritten to "O" by the 4-bit data of the bit. Parity is also generated for the 4-bit data from the 4th bit to the 7th bit of the write data, and the 13th bit of the parity data is rewritten with the generated parity. Furthermore, regarding the 4-bit data from the 8th bit to the 11th bit of the write data.

Parity is generated, and the first bit of the parity data is rewritten with the generated parity. Furthermore, parity is also generated for the 4-bit data from the 12th bit to the 15th bit of the write data, and the 5th bit of the parity data is rewritten with the generated parity.

In this way, when writing data, parity is generated in units of 4-bit data, and predetermined bit data of the parity data is rewritten using these generated parities.
RAM 8 a, 8 by 8 c.

The data is written to DRAMs 8a, 8b, 8c, and 8d different from 8d.

1 based on the page mode read cycle shown in Figure 5.
For example, set address 28020 (H) to data ``'0110''.
...”, CPU1 reads RAS
and CAS are generated, and after the fall of this CAS, the data data “0110...” in the first “L” level data area 6 of the OE multiplied signal is read out (see FIG.
Based on this read data, the parity generation/inspection circuit 4 generates data in units of 4 bits (O pits 3 bits, 4 bits to 7 bits, 8 bits to 11 bits, Parity is calculated every 12 bits (15 bits).

Subsequently, after the next fall of the CAS, the parity data in the parity area 7 is read out at the next "L" level of the OE multiplied signal (as shown in (f) and (g) in the same figure).
The 1st, 5th, 9th, and 13th bits of this parity data are the 4th bit of the read data.
Parity is bit-wise. Therefore, a parity check is performed using these four parities and the parity calculated above. That is, the first bit of parity data is compared with the parity calculated based on the 4-bit data from 8 bits to 11 bits, and the 5th bit of parity and the 4-bit data from 12 bits to 15 bits are compared. The 9th bit of parity is compared with the parity calculated based on the 4-bit data from bit 4 to bit 7, and the 13th bit of parity is compared with the parity calculated based on the 4-bit data from bit 4 to bit 7. The parity calculated based on the 4-bit data from bit to 3 is compared. Then, a parity error is generated based on the parity check based on the comparison, and an interrupt is applied to the CPU, so that the interrupt processing is executed by the CPU as in the conventional case.

In this way, the page mode cycle of the DRAMs 8a, 8b, 8c, and 8d is used to provide a data area and a parity area in the memory section 3 where data is written and read, and parity check is performed in the memory space. Therefore, there is no need to prepare memory dedicated to parity in addition to memory for data, and costs can be reduced accordingly.Especially in small systems, the unused area of memory section 3 can be used as the parity area. It is also possible to achieve further economical efficiency.

Further, in the parity check, since the parity check is performed in units of 4 bits of data, it is possible to further improve the accuracy of the parity check.

[Effects of the Invention] As explained above, according to the parity checking method of the present invention, a data area and a parity area are provided in a memory, and when writing data to the data area, the data is divided into 4-bit units. , calculated every 4 bits, and 4 bits of the predetermined parity data in the above parity area.
When rewriting the predetermined bit data at every other bit with the four parities calculated above, and reading out the data in the data area, the parity data corresponding to this read data is read out, and the predetermined bit data at every four bits of the parity data is rewritten. and the parity calculated based on the data in 4-bit units, and check the parity of the data.
There is no need for a memory dedicated to parity, and especially in small systems, the unused area of memory where data is written and read can be used as the parity area.In other words, the parity check can be performed using the data memory space. Cost can be reduced by the memory dedicated to parity.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and is a schematic block diagram of a parity circuit to which a parity check method is applied; FIG. 2 is a diagram for explaining the memory space of the parity circuit;
FIG. 3 is a diagram for explaining the memory space shown in FIG. 2, FIGS. 4 and 5 are time charts for explaining the operation of the above parity checking method, and FIG. 1 is a schematic block diagram of a parity circuit to which a test method is applied; FIG. In the figure, 1 is the CPU, 2 is the data bus, and 3 is the memory section (R
AM), 4 is a parity generation/check circuit, 6 is a data area, 7 is a parity area, 8a, 8b. 8c and 8d are DRAM (A), (B), (C), (D)
It is.

Claims (2)

[Claims] (1) A parity checking method in which data is written to a memory, data is read from the memory, and parity of the data is checked, wherein a data area and a parity area are provided in the memory, and data is written to the data area. On this occasion,
When predetermined bit data of parity data corresponding to a predetermined address of the parity area is rewritten with the parity calculated based on the data to be written, and when reading data of the data area, the parity corresponding to the read data is rewritten. 1. A parity checking method, comprising: reading parity data, comparing predetermined bit data of the parity data with a parity calculated based on the data, and performing a parity check of the data. (2) When writing the data, calculate parity for each 4-bit unit of the data, read the parity data, and write bit data at predetermined bit intervals of the parity data using the calculated four parities. The parity test method according to claim (1), wherein the parity test method is performed by: