JPH03163657A - Multi-processor system - Google Patents

Abstract

PURPOSE:To allow other processor processing to synchronize with a reset operation of each processor by executing quickly the own reset processing, when a reset request is generated, and also, making a communication inhibiting signal significant until the initialization processing is ended, when the reset is started. CONSTITUTION:A communication inhibiting signal on inhibiting signal lines 11-13 is monitored by an inhibiting signal monitoring means 8 provided in the inside of each processor 1-3, and based on a result of this monitoring, whether a communication is possible or not is informed to a transmitting/receiving means 5, and when the communication is possible, data is exchanged mutually through a data bus 4. In this case, when a reset request is generated in a processor 2, an internal reset means 6 is actuated, and a built-in inhibiting signal generating means 7 makes a communication inhibiting signal sent out to the inhibiting signal line 12 significant simultaneously with a start of the reset processing. In such a way, the processor 1 waits for the data transmission/ reception to the processor 2 until the communication inhibiting signal becomes insignificant, or suspends it and executes it in the next change.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a system in which a plurality of processors are connected to each other via a transmission path, and each processor executes predetermined information processing while mutually transmitting data. The present invention relates to a multiprocessor system, and particularly to reset processing of each processor in the multiprocessor system.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional multiprocessor system disclosed in, for example, Japanese Unexamined Patent Publication No. 62-245362. In the figure, reference numerals 1 to 3 denote a plurality of processors that are connected to other devices (not shown) and execute predetermined information processing while mutually transmitting data. Reference numeral 4 denotes a data path as a transmission line connecting these processors 1 to 30. In each of the processors 1 to 3, 5 is a transmitting/receiving means for exchanging data with other processors (1 to 3) via the data path 4, and 6 is a processor. This is a reset means for resetting the processors 1 to 3 equipped with the processors 1 to 3 when a reset request is generated in the processors 1 to 3.

Here, the illustrated multiprocessor system has a hierarchical structure with respect to reset control, in which processor 1 is the upper processor and processors 2 and 3 are the lower processors. Therefore, the reset of processors 2 and 3 is performed under the control of processor 1.

Next, the operation will be explained. Each of the processors 1 to 3 uses a transmitting/receiving means 5 provided inside each processor, and uses a data bus 4.
They exchange data with each other via , and each process the information.

Here, when a υ sector request is generated in the processor 1, the processor 1 activates the internal reset means 6 to reset itself, and sends a reset signal to the processors 2 and 3 to the internal transmitting/receiving means. 5 to the data bus 4. This reset signal is received by the transmitting/receiving means 5 of the processors 2 and 3 via the data bus 4, and each processor 2 button and 3 activates the internal reset means 6 in accordance with this reset signal to execute its own reset. .

Further, when a reset request is generated in the processor 2, the processor 2 sends the reset request to the processor 1 and the internal transmitting/receiving means 5 to the data bus 4. Upon receiving this reset request, the processor 1 generates a reset signal in synchronization with its own processing, and sends it back to the processor 2 from the transmitting/receiving means 5 via the data bus 4.

When the processor 2 receives this reset signal, it activates the internal reset means 6 to reset itself. In addition,
Even when a reset request occurs in the processor 3, the processor 3 is reset using the same procedure.

In this way, by performing reset control of the lower processors 2 and 3 by the upper processor 1, the reset operations of the lower processors 2 and 3 are synchronized with the processing of the higher processor 1, and the multiple processors 1 to 3 maintain normal communication between each other.

[Problem to be solved by the invention]

Since the conventional multiprocessor system is configured as described above, it is necessary to configure processors 1 to 3 hierarchically for reset control, which imposes restrictions on system construction and makes it impossible to construct a flexible system. If an abnormality such as a runaway program occurs in the lower processor 2 (3) and a reset request is sent, if the upper processor 1 is executing a process with a higher priority than the reset request. , this reset request is not accepted until the relevant processing is completed, and it takes a long time from the generation of the reset request until the reset processing is actually executed, and the abnormal state of the lower processor 2 (3) continues for a long period of time. In addition, if a reset request from the lower processor 2 (3) is not transmitted to the upper processor 1 due to a hardware abnormality, the lower processor will remain in an abnormal state forever. However, when an abnormality occurs, the relevant part must be reset immediately to minimize the abnormality, which is a fatal flaw in systems that require this.

This invention was made in order to solve the above-mentioned problems, and it is possible to promptly perform resent processing in response to a reset request of each processor without layering processors for reset control, and to reset each processor. An object of the present invention is to obtain a multiprocessor system that can synchronize the operations of other processors.

[Means to solve the problem]

The multiprocessor system according to the present invention includes a prohibition signal generating means that makes a communication prohibition signal significant for prohibiting communication with the processor during the period 1 from the start of reset to the end of the initialization process, and other devices. When the prohibition signal generating means of the processor monitors the communication prohibition signal generated and detects that it is significant, it sends an instruction to the transmitting/receiving means to prohibit communication with the processor that generated the communication prohibition signal. The system is equipped with a means for monitoring a prohibition signal.

[Effect]

Each processor in the present invention promptly executes its own reset processing using the reset means when a reset request is generated, and also uses the prohibition signal generating means from the time the reset is started until the initialization processing is completed. The generated communication prohibition signal is made significant, and when communicating with other processors, the prohibition signal monitoring means determines the validity/invalidity of the communication prohibition signal generated by the prohibition signal generation means of each processor. , if it is significant, communication by sending and receiving is υ
In this way, data is sent and received only when it is confirmed that the reset request has stopped and is unexpected.In this way, the reset process can be executed promptly in response to a reset request from each processor without tiering the processors for reset control. To realize a multiprocessor system that can synchronize the processing of other processors with the reset operation of the processor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 to 3 are processors, 4 is a data path as a transmission line, 5 is a transmitting/receiving means, and 6 is a reset means, which are the same or equivalent parts as the conventional ones with the same reference numerals in FIG. 2. It is.

A housing 7 is disposed within each processor 1 to 3, and is used to communicate with the processor 1 to 3 from the time the reset means 6 starts resetting until the initialization process of the processor 1 to 3 is completed. This is a prohibition signal generating means that makes a communication prohibition signal that prohibits transmission and reception of data significant. 8 is similarly arranged in each processor 1 to 3, and is arranged in each processor 1 to 3.
The prohibition signal generating means T in 3 monitors whether the communication prohibition signal generated is significant or not, and when it detects that the communication prohibition signal is significant, it transmits the prohibition signal that generated the communication prohibition signal to the transmitting/receiving means 5. Processor 1 to which generating means 7 belongs
This is a prohibition signal monitoring means for instructing prohibition of data transmission/reception with the third party. 11 to 13 are prohibition signal lines through which a communication prohibition signal from the prohibition signal generating means 7 is transmitted; 11 is a communication prohibition signal from the processor 1; 12 is a line from the processor 2; A communication prohibition signal from the processor 3 is transmitted.

Next, the operation will be explained. Each of the processors 1 to 3 monitors the communication prohibition signals on the prohibition signal lines 11 to 13 by the prohibition signal monitoring means 8 provided inside each processor, and based on the monitoring results, it instructs the transmitting and receiving means 5 whether or not communication is possible. If communication is possible, data is exchanged with each other via the data bus 4, and each information process is executed. For example, the prohibition signal monitoring means 8 of the processor 1 uses the prohibition signal line 1
It monitors the communication prohibition signals on buttons 2 and 13 and tries to send data to processor 2. In this case, the prohibition signal generating means 7 of the processor 2 determines whether the communication prohibition signal sent to the prohibition signal line 12 is significant or invalid. Since the processor 2 is not executing the reset process, the communication prohibition signal on the prohibition signal line 12 is meaningless. Therefore, the processor 1 sends the data to be transmitted to the data path 4 through the transmitting/receiving means 5, and the processor 2 receives the data from the data path 4 through the transmitting/receiving means 5.

Here, when a reset request occurs in the processor 2, the processor 2 activates the internal reset means 6 to start its own reset processing, and the prohibition signal generation means 7 in the processor 2 starts this reset processing. At the same time, the communication prohibition signal sent to the prohibition signal line 12 is made significant. Thereafter, the operation of the processor 2 proceeds from reset cancellation to initialization processing, but the prohibition signal generation means T
The communication prohibition signal continues to be significant until this initialization process is completed. Therefore, during that period, the determination result of the communication prohibition signal on the prohibition signal line 12 by the prohibition signal monitoring means 8 of the processor 1 is significant, and the prohibition signal monitoring means 8 is So, processor 2
Instructs to prohibit sending and receiving data with. Therefore, the processor 1 either waits for data transmission/reception to the processor 2 at 1, when the communication prohibition signal becomes invalid, or stops the communication and starts execution of the next process.

In this way, even if the processor 2, which is the communication partner, is reset asynchronously, the processor 1 can proceed with the processing in synchronization with the reset operation without transmitting or receiving erroneous data. Therefore, by pressing the reset control button and treating each processor as the same level without layering it,
It becomes possible to maintain normal communication between the plurality of processors 1 to 3.

Note that when a reset request is generated in the processor 1 or 3, the processor 1 or 3 is reset by the same procedure, and during that time, the prohibition signal generated by the prohibition signal generation means 7 of the processor 1 or 3 becomes significant. b1 Communication with that processor 1 or 3 is prohibited.

In the above embodiment, the communication prohibition signal is a signal transmitted through a prohibition signal line prepared for each processor, but an input signal within each processor that is accessible from other processors through a data bus is shown. It is also possible to prepare one bit in the output port or the common memory for a signal instructing prohibition of communication, and to determine whether the prohibition of communication is significant or invalid by manipulating this bit, which is similar to the above embodiment. be effective.

〔Effect of the invention〕

As described above, according to the present invention, when a reset request is generated, it promptly executes its own reset processing, and after the reset is started, the communication prohibition signal is made significant until the initialization processing is completed. In addition, when communicating with other processors, the validity/invalidity of the communication prohibition signal is determined, and if it is significant, communication is terminated, and data is sent and received only if it is invalid, so reset control A multiprocessor system that can quickly perform reset processing in response to a reset request from each processor without tiering processors, and can synchronize the reset operation of each processor with the processing of other processors. There are benefits to be gained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiprocessor system according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional multiprocessor system. 1 to 3 are processors, 4 is a transmission line (data node), 5
6 is a transmitting/receiving means, 6 is a reset means, 7 is a prohibition signal generating means, and 8 is a prohibition signal monitoring means. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A plurality of processors each execute predetermined information processing while exchanging data with each other, and a transmission line interconnecting the processors, each of the processors communicating with other processors via the transmission line. In a multiprocessor system, the multiprocessor system includes a transmitting/receiving means for transmitting and receiving the data between the processors, and a reset means for resetting the processor equipped with the transmitting/receiving means when a reset request is generated, wherein each of the processors is reset by the reset means. communication generated by the prohibition signal generation means for making a communication prohibition signal significant for prohibiting data transmission and reception with the processor from the start of the initialization process to the end of the initialization process; and communication generated by the prohibition signal generation means of the other processors. Monitoring the prohibition signal, and when detecting that the communication prohibition signal is significant, instructs the transmitting/receiving means to prohibit data transmission and reception with the processor to which the prohibition signal generation means that generated the communication prohibition signal belongs. A multiprocessor system characterized by being provided with prohibition signal monitoring means.