JPH03157899A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent test contents from being limited by providing a switching circuit which holds a 1st activation signal at active level and a 2nd activation signal at inactive level. CONSTITUTION:Before an internal test signal varies to the active level the active-level period of a timer signal S3 after being initialized to the active-level period of the timer signal S3, the 1st activation signal S5 is held at the inactive level and the 2nd activation signal S6 is held at the active level and inactive level according to the active level and inactive level of a redundancy switching signal S1. After the internal test signal S2 reaches the active level, the 1st activation signal is held at the active level and the 2nd activation signal S6 is held at the inactive level. For example, even when an external test signal EXT is inputted by utilizing one of input terminals for address signals ADX and ADY, those input terminals can be tested while put back to the inputs of address signals ADX and ADY. Consequently, the test contents are never limited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and particularly to a semiconductor memory device having a memory cell portion.

[Conventional technology]

Conventionally, this type of semiconductor memory device is
As shown in the figure, a memory cell unit including a plurality of memory cells, a redundant memory cell unit including a plurality of redundant memory cells, and an address block which is activated when the first activation signal 813 is at an active level. Signal A I) x, A Dv
According to Y decoder 4. An X decoder 3 forming a selection circuit for selecting a predetermined memory cell of one memory cell part 1 together with a Y cell part 1/actor part r), and a second activation signal Si
-4 is activated when the address signal A D is active level.
A redundancy decoder 6 of a redundancy selection circuit selects a predetermined memory cell of the redundant memory cell section 2 according to X, and sets a redundancy switching signal Sll to an active level when the selected memory cell of the memory cell section 1 is a defective memory cell The edge disconnection determination circuit 7 of the redundancy switching determination circuit, and the high potential detection circuit that sets the internal test signal Si2 to the active level when the active level is at the active level of the external test signal EX'r with a voltage higher than the normal operating voltage. 8, the redundancy switching signal Sil and the internal test signal S12 are integrated to form a second activation signal S],
4) and an inverter 1.G1 which inverts the second activation signal S14 and generates the first activation signal 813. It was configured to have the following.

In other words, when a defective memory cell exists in the memory cell section 1, normally when the address of this defective memory cell is specified, the redundancy switching (Ii No. 31.1) whose active level is low by disconnecting the fuse is performed. is generated, the memory cell in the redundant memory cell section 2 is selected, and the redundant memory cell section 2 is returned to the state before being switched and used (the state in which only the memory cell section 1 is used) for reading and writing. When you want to perform a test such as this, by setting the external test signal E There is.

The input of the external test signal EXT is usually the address signal AD.
X, ADY input terminals, control signal input terminals, etc. were used.

[Problem to be solved by the invention]

-1-In the conventional semiconductor memory device described in 1-, the input terminal of the external test signal EXT, which performs the test by returning to the state before switching to the redundant memory cell section 2, is connected to the address signal ADx.
, ADv and the control signal input terminal, and is configured to be able to perform the D1- only when the external test signal EXT is at the active level, so for example, the address signal A D x
, ADY input terminals are shared, there is a drawback that only half of the memory cells in the memory cell section 1 can be tested, and the contents of the memory cell section 1 are limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can prevent data contents from being restricted.

[Means to solve the problem]

The semiconductor memory device of the present invention includes a memory cell section including a plurality of memory cells, a redundant memory cell section including a plurality of redundant memory cells, and an addressable memory cell section that is activated when a first activation signal is at an active level. a selection circuit that selects a predetermined memory cell in the memory cell section according to a signal; and a selection circuit that is activated when a second activation signal is at an active level. a redundancy selection circuit that selects a predetermined memory cell of the redundant 5 memory cell section according to the address signal; and a redundancy switch that sets a redundancy switching signal to an active level when the selected memory cell of the memory cell section is a defective memory cell. A determination circuit, a high potential detection circuit that makes the internal signal active when an external test signal whose active level is higher than the normal operating voltage is at an active level, and a high potential detection circuit that is active only for a predetermined period from power-on. A timer circuit that generates a timer signal that becomes the internal test signal; The period is such that the first activation signal is set to an inactive level or an active level, and the second activation signal is set to an active level or an inactive level of 1/bell depending on the active level or inactive level of the redundancy switching signal. , a switching circuit that maintains the first activation signal at an active level and the second activation signal at an inactive level after the internal test signal becomes an active level.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, when the 2-memory cell section 1 includes a plurality of memory cells, the redundant memory cell section 2 includes a plurality of redundant memory cells, and the first activation input signal S5 is at an active level (high level), Activated address signals ADx, A
I) According to The redundant decoder 6 of the redundant selection circuit selects a predetermined memory cell in the redundant memory cell section 2 according to the address signal ADX and the memory cell in the selected memory cell section is a defective memory cell. When redundancy switching (No. 2 81 is set to active level (low - bell)
When the external test signal EXT, whose active level is higher than the normal operating type, is at the active level, the internal circuit
High electron) γ that lowers the signal S2 to a 1 m dynamic level (high level)
A detection circuit 8, a timer circuit that generates a timer signal S3 that is at an active level (high level) for a predetermined period from power-on, and a register RG1. A NOR gate G1 and an inverter I are initialized during the active level period of the timer signal S3, and after the active 1/bell period of the timer signal S3 has elapsed, a period before the internal test signal S2 becomes the active level. sets the first activation signal S5 to the inactive level and the active level according to the active level and inactive level of the redundant switching signal S1.
/bell, the second activation signal S6 is set to active l/bell, and after the signal S2 to internal test 1 becomes inactive level, the first activation signal S5 is set to active level, Second
The switching circuit 10 maintains the activation signal S6 at an inactive level of 1/bell.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of each part for explaining the operation of the second embodiment.

Immediately after the power is turned on, the timer signal S3 goes high and initializes the register RG of the switching circuit 10 (output signal S4 low 1/bell).

After this, normal operation begins, and the address signal ADx.

AI) 1. is input to the memory cell section 1. When access to the redundant memory cell section 2 is started, at time t6. in FIG. (up to σ) period), if the memory cell in the memory cell section 1 specified by the address signal ADX is not a defective memory cell, the fuse disconnection determination circuit 7 outputs a high-level redundancy switching signal S1, and the register R , G 1 output signal S
4 is at a low level, the first activation signal S5 is set at a high level to access the memory cell section 1, and when it is a defective memory cell, a low level redundancy switching signal S1 is output. Then, the second activation signal S6 is set to high level and the redundant memory cell section 2 is accessed.

When you want to return to the state before switching and using the redundant memory cell section 2 (a state in which only the memory cell section 1 is used) and perform a test such as fortune-telling, use the external dess I-signal EX'.
The high voltage detection circuit 8 causes the internal test signal S2 to go high.
A timer that sets the output signal S4 of , to a high level, , L
rJ, later). Since the output signal S4 of the registers R, G) remains at high level 17 even when the external test signal EXT and the internal signal S2 return to low level, the first activation signal S5 remains at high level. , the second activation signal S6 is held at a low level17. Access to memory cell 1 is performed regardless of the level of redundancy switching signal S1.

This operation continues even if the external test signal EXT is input [[[]. Therefore, for example, even if the external test signal 1-, X1' is input using one of the input terminals of the address signals ADx, ADv, This input terminal is used as address signal ADx
, ADv can be returned to the input for testing, so the test content is not limited.

FIG. 3 is a block diagram showing a second embodiment of the invention.

This embodiment is different from the case where the first embodiment has a redundant memory cell section 2 in the word direction. , shows the case where the differential memory 1 has a redundant memory cell section 2A in one direction.6 [Effects of the Invention] () 0 As explained above, the present invention has an external des
・Once the signal reaches the active level, a switching circuit is provided to maintain the first activation signal at the active level and the second activation signal at the inactive level even if the input of this external test signal is stopped.
: By using this configuration, even when inputting external test signals using address signal or control signal input terminals,
Since the input of this input terminal can be returned to an address signal or a control signal and the test can be continued, it is possible to prevent the test contents from being limited.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a timing diagram of various signals for explaining the operation of the embodiment shown in FIG. 1, FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. 4 is a conventional semiconductor memory device. FIG. 5 is a block diagram showing an example of this, and FIG. 5 is a timing diagram of each part of the semiconductor memory device shown in FIG. ■...Memory cell section, 2.2A...Redundant memory cell J
3, 3A... , 8... High potential detection circuit, 9... Timer circuit, 10... Switching circuit, 11... Sense amplifier/write circuit, 12... Input/output cut/fail circuit, 13... Redundant selector section, G
,...NOR gate, ■1... Inverter, RG Lujistor.

Claims (1)

[Claims] a memory cell section including a plurality of memory cells; a redundant memory cell section including a plurality of redundant memory cells; activated when a first activation signal is at an active level; a redundant selection circuit that is activated when a second activation signal is at an active level and selects a predetermined memory cell of the redundant memory cell section according to the address signal; A redundancy switching determination circuit that sets a redundancy switching signal to an active level when a memory cell in the cell section is a defective memory cell, and an internal test signal that sets a redundancy switching signal to an active level when an external test signal whose active level is higher than the normal operating voltage. a timer circuit that generates a timer signal that is at an active level for a predetermined period from power-on; and a timer circuit that is initialized during the active level period of the timer signal and that is set to an active level of the timer signal. After a period of , the first activation signal is set to an inactive level or an active level according to an active level or an inactive level of the redundancy switching signal during a period before the internal test signal becomes an active level, setting the second activation signal to an active level and an inactive level;
After the internal test signal becomes active level, the first
1. A semiconductor integrated circuit comprising: a switching circuit that maintains a second activation signal at an active level and a second activation signal at an inactive level.