JP3251253B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art Most defective semiconductor memory devices are caused by defective cells themselves, defective word lines, defective bit lines, and the like. Causes include variations in sense amplifiers composed of bit line pairs and pairs, bit line selection switches, sense amplifier control signals, bit line precharge signals, and the like.

[0003] Even among the causes of bit line failure, the sense amplifier operates with a small potential difference, so that the transistors constituting the sense amplifier often fail due to manufacturing variations.

[0004]

However, when investigating the cause, various conditions such as test patterns have been changed to investigate the cause.
There is a problem that it is very difficult to determine whether or not the output is unbalanced between the sense amplifiers connected to the paired bit lines, respectively.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device capable of easily determining whether or not a fault is caused by an imbalance in the output of a sense amplifier.

[0006]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a test circuit, a logic circuit, and a sense amplifier, and comprises a memory cell array comprising word lines and bit lines. a semiconductor memory device for inputting and outputting data to said test circuit, the outer
A test mode entry signal generated by a signal input to the external terminal is output, and the logic circuit includes:
Take the logic of the test mode entry signal output from the test circuit and the input signal of the row decoder circuit,
The word line is deactivated, and the sense amplifier deactivates the word line in response to an output signal of the logic circuit.
It can operate even in the sexual state.

The logic circuit is incorporated in a decoder circuit for outputting an address signal to the memory cell.

Further, a semiconductor memory device according to the present invention includes a test circuit, a transfer gate circuit, and a sense amplifier, and inputs and outputs storage data to and from a memory cell array through word lines and bit lines. Wherein the test circuit is adapted to output signals input to each external terminal.
The transfer gate circuit is turned on and off based on the test mode entry signal output from the test circuit, and the data of the memory cell is sense-undetected.
The sense amplifier,
Operable even when the word line is inactive.
You.

[0009]

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 and 2 are circuit diagrams showing a test circuit in a semiconductor memory device according to Embodiment 1 of the present invention.

A mode entry circuit in a semiconductor memory device according to a first embodiment of the present invention shown in FIG. 1 inputs a test mode signal to a test circuit shown in FIGS. 1 and 2 and outputs a test mode entry signal. The logic between the test mode entry signal output from the circuit and the input signal of the row decoder circuit is taken by a logic circuit to deactivate the word line.

Further, the logic circuit is incorporated in a decoder circuit for outputting an address signal to a memory cell.

Next, the semiconductor memory device according to the first embodiment of the present invention will be described in detail using a specific example.

The test circuit in the semiconductor memory device according to the first embodiment of the present invention comprises a combination of the first circuit shown in FIG. 1 and the second circuit shown in FIG.

The first circuit shown in FIG.
And a combination of an inverter 2a, 2b connected in series connected to one input terminal of the latch circuit 1 and an inverter 2c connected to the output terminal of the latch circuit 1. An internal clock ICLK is input and inverters 2a, 2 connected in series based on an external signal S.
b , the mode switching signal CS to the second circuit shown in FIG. 2 is output through the latch circuit 1 and the inverter 2c .

Further, the second circuit shown in FIG.
Circuits 3, 4, 5; inverters 6a, 6b for inverting the outputs of the NAND circuits 3, 4 and inputting them to two input terminals of the NAND circuit 5; and a test mode entry signal TEST1 based on a signal from the NAND circuit 5. And an output circuit 7 for outputting the same.

The second circuit shown in FIG.
The mode switching signal CS from the first circuit shown in FIG.
The signal RAS, the signal CAS, and the signal WE are inputted, and the NAND
When the address key signals A4, A5, A6 are input to the circuit 4, the outputs from the NAND circuits 3, 4 are output from the inverters 6a,
6b, input to the two input terminals of the NAND circuit 5,
The output circuit 7 outputs a test mode entry signal TEST1 based on the output signal from the AND circuit 5.

Further, as shown in FIG.
D circuits 8a, 8b, 8c and 8d .
NAND circuits 8a, 8b, 8c and 8d are X-DECOD
Are incorporated into ER circuit 8, or the second circuit shown in FIG. 2
The logic of the test mode entry signal TEST1 output from the decoder and the input signal of the row decoder circuit is calculated, and X-D
The ECODER 8e is controlled to make the word lines W0 to Wm inactive.

FIG. 3 is a characteristic diagram showing a timing for entering a test mode in the embodiment of the present invention.

As shown in FIG. 3, when an external signal S is inputted, a mode switching signal CS from the first circuit shown in FIG.
Signal RAS, signal CAS, signal WE, and address key signal
A4, A5, and A6 are input to the second circuit shown in FIG.
For example, when the external signal S is HIGH and the signals CS , R
AS, CAS, WE and address key signals A4, A5,
When A6 is LOW, the test mode entry signal T
EST1 becomes LOW . However, HIGH and L of each signal
The relationship with OW is not limited to the case described above.

The semiconductor memory device according to the first embodiment of the present invention shown in the figure shifts to the test mode based on the input of the external signal S, and the test mode entry signal TEST1 becomes low.
Becomes a HIGH from OW, the X-DECODER shown in FIG. 4 based on the test mode entry signal TEST1
8e, and deactivates all word lines W0 to Wm connected to the X-DECODER 8e.

FIG. 4 is a circuit diagram showing a part of a memory cell circuit and a peripheral circuit in a general semiconductor memory device.

In FIG. 4, a test mode entry signal TEST1 for deactivating a word line is input to an X-DECODER circuit 8 via an inverter 9, and the X-D
Logic circuits 8a, 8b,
8c and 8d take the logic of the test mode entry signal TEST1 output from the second circuit shown in FIG. 2 and the input signal of the row decoder circuit, and perform X-DECODER8.
In order to deactivate the word lines W0 to Wm by controlling e, the word lines W0 to Wm are not selected.

Since the word lines W0 to Wm are not selected, the memory cells TRUE, NO connected to the respective bit lines D, DB
Data from T will not be transmitted to each bit line pair D, DB.

However, the bit line precharge signal PDL
From HIGH to LOW, the activation signal SAN of the sense amplifier SA from １ ／ Vcc (voltage) level to LOW,
Activation signal SAP of sense amplifier SA is Ｖ VCC
When the level changes from the (voltage) level to HIGH, the sense amplifier SA is activated, and the pair of bit lines D and DB balanced at the potential of 1/2 VCC are used for manufacturing the MOS transistors constituting the sense amplifier SA. Will cause a potential difference.

FIG. 5 is a characteristic diagram showing an example of the internal waveform in the case described above. In the following description, the sense amplifier S
A phenomenon in which a potential difference occurs between a pair of bit lines D and DB connected to the output terminal of the sense amplifier SA due to manufacturing variations of each MOS transistor constituting A will be described as the inclination of the sense amplifier SA. I do.

There are two types of inclinations of the sense amplifier SA. When the potential of the bit line D becomes higher than the potential of the bit line DB, the sense amplifier SA is inclined to the D side or to the TRUE side.

On the other hand, when the potential of the bit line DB becomes higher than the potential of the bit line D, the sense amplifier SA is inclined to the DB side or to the NOT side.

A memory cell connected to the bit line D is called a TRUE cell, and a memory cell connected to the bit line DB is called a NOT cell.

The potential difference between the bit lines D and DB caused by the inclination of the sense amplifier SA is equal to the potential difference between the Y-DECO shown in FIG.
The signal is transmitted to the IO bus via the bit line selection signal line Y-SW selected by the DER 10.

The output signal of the IO bus is supplied to the DAMP circuit 1
1, output to the output terminal DQ via the OUT circuit 12.

The data read from the output terminal DQ is "0" or "1".
The slope of the sense amplifier SA,
When the sense amplifier SA is tilted toward the DB side, the data "1" is read from the output terminal DQ.
, Data “0” is read out.

FIG. 6 shows data "H", N
This shows an example of a pattern in which data “L” is written in the OT cell. That is, in FIG. 6, ○ indicates a memory cell, and among the bit lines for writing data to each memory cell, the memory cell connected to the TRUE side is connected to the data “H” and the NOT side. The present memory cell shows a pattern in which data “L” is written.

Using the circuit according to the embodiment of the present invention, for example, in the case of a memory cell having a circuit configuration as shown in FIG. 6 , data "0" is written to the memory cell connected to the word line X0 .
Then, a test for reading data “0” is performed.

For example, write data is written to the memory cell C00 of the sense amplifier SA connected to the bit line Y0.
If the expected value data is read out and the memory cell C00 passes the test, it can be understood that the sense amplifier SA is tilted to the DB side.
It turns out that it leans to the side.

As described above, the inclination of the sense amplifier connected to each bit line can be easily checked based on the pass / fail information of each cell.

Next, an example of a defect in the semiconductor memory device will be described with reference to FIG. FIG. 7 shows a pattern in which data "H" is written in the TRUE memory cell and data "L" is written in the NOT memory cell. This pattern shows a case where the TRUE memory cell of the bit line Y0 becomes defective. ing.

FIG. 8 illustrates the operation of the bit line pair D and DB under the condition of passing the defective bit line Y0 and the condition of failing. In the pattern 1, data "H" is written.
In this case, a test pattern for reading data "H" fails (FAIL), and the conditions of patterns 2, 3, and 4 show a case of passing (PASS). As shown in FIG.
Thus, in pattern 1, the cell on the D side has cell data "H".
Is stored in the TRUE cell because
The potential on the bit line D side is 1/2 VCC level
And the bit line DB side becomes 1/2 VCC.
The potential difference between the bit lines D and DB is ΔV1,
In step 1, data "H" is written and data "H" is read.
Fail with the test pattern. As shown in FIG.
As shown in pattern 2, the memory cells on the D side have data "
0 ”has been written, so that the cell data“ L ”
And the potential stored in the TRUE cell causes the bit line
The potential on the D side drops several mv from 1/2 VCC, and the bit line D
B, the potential becomes higher than the pass (P
ASS). As shown in FIG.
Since the memory cell on the side is a NOT cell, the memory on the DB side
The recell becomes cell data "H" and is stored in the NOT cell.
The potential on the bit line DB side is Ｖ VCC due to the applied potential.
Several mv above the level and higher than the bit line D.
In the condition of the pattern 3, it passes (PASS). FIG.
In pattern 4, as shown in FIG.
Since it is an OT cell, the memory cell on the DB side
Becomes “L”, and the potential stored in the NOT cell
The potential on the bit line DB side is several mv above the 1/2 VCC level.
The potential of the pattern 4
Pass (PASS) under the condition.

In this case, a failure occurs only when the cell on the D side among the cells connected to the bit line Y0 is data "H".

In the case of this failure, it cannot be distinguished whether the cause is a cell or a failure due to imbalance of the sense amplifier.

This is because the operation of the bit line pair in the patterns 2 and 3 has a higher potential difference on the DB side than the bit line on the D side, so that the sense amplifiers have the same inclination. From this result, it is conceivable that it depends on the inclination of the sense amplifier.

However, in the case of the pattern 4, the operation of the bit line pair is the same as that of the pattern 1, and the bit line passes even though the inclination of the sense amplifier is the same. Cannot be determined. There could be a cell cause.

The movements of the bit lines D and DB are the same in the patterns 1 and 4, but the results are not the same because the circuit configuration and the electric charge accumulated in the memory cell are different, so that the patterns between the bit lines D and DB are different. The generated difference potential is not the same between pattern 1 and pattern 4.

Conventionally, when such a defect occurs, there is no method for accurately examining the inclination of the sense amplifier to investigate the cause of the defect. Only the gate length of each transistor constituting the sense amplifier circuit is measured. In the case of an assembly, the resin must be unsealed, the cover film must be peeled off, and the gate length must be measured. ~
I had been investigating it for more than three days, but I couldn't understand it because high precision was required.

By using the circuit of the present invention and a simple test pattern program, the inclination direction of the sense amplifier can be easily checked by the capability of the sense amplifier without depending on the cell data. As a result, the number of man-hours spent on the failure analysis can be significantly reduced as compared with the related art.

Connected to the output terminal of the sense amplifier SA
Potential generated between the paired bit lines D and DB
If the difference (slope) matches, the cause is imbalance of the sense amplifier. If the difference (slope) does not match, the cause is no sense of the sense amplifier slope. You can see that. More specifically, the bit line pre-charge
Signal PDL changes from HIGH to LOW, sense amplifier
SA activation signal SAN is at 1/2 Vcc (voltage) level
From LOW to the activation signal SAP of the sense amplifier SA
From 1/2 VCC (voltage) level to HIGH
Then, the sense amplifier SA is activated, and the voltage of 1/2 VCC is
The pair of bit lines D and DB balanced with the potential are
Of each MOS transistor forming the sense amplifier SA
There will be a potential difference due to manufacturing variations. Sensea
Of each MOS transistor that composes the amplifier SA
Due to the variation, it is connected to the output terminal of the sense amplifier SA.
Potential difference occurs between the paired bit lines D and DB
If the phenomenon is expressed as the slope of the sense amplifier SA,
There are two types of inclination of the amplifier SA, one of which is
In this case, the potential is higher than the potential of the bit line DB.
The potential of the bit line DB is higher than the potential of the bit line D
Is the case. Checked by test patterns 1 to 4 shown in FIG.
If the sense amplifier tilt direction matches,
The threshold and gate length of each transistor
If they do not match, it is the inclination of the sense amplifier.
The cause of the
There is a problem with the threshold value of the
You can see that

(Embodiment 2) FIG. 9 is a circuit diagram showing Embodiment 2 of the present invention. A semiconductor memory device according to a second embodiment of the present invention has a test circuit and a transfer gate circuit, and inputs and outputs storage data to and from a memory cell array through word lines and bit lines. A test mode signal is input to the test circuit shown in FIG. 2, a test mode entry signal TEST1 is output, and the transfer gate circuits 13a and 13b are controlled by the transfer control circuit 14 based on the test mode entry signal TEST1 output from the test circuit. It is turned off and the bit lines D and DB are deactivated.

Transfer gate circuits 13a, 13b
Are provided on the bit lines D and DB connected to the memory cells TRUE and NOT of the memory cell array and the sense amplifier SA, and the data of the memory cells TRUE and NOT is stored in the sense amplifier SA.
It is designed to prevent transmission.

In the second embodiment of the present invention shown in FIG. 9, even if a word line is selected at the time of reading, data of the memory cells TRUE and NOT are stored in the sense amplifier SA as in the first embodiment.
, And operates using the transistor capability of the sense amplifier itself, so that the inclination of the sense amplifier can be easily determined.

[0051]

As described above, according to the present invention, data is not transmitted from a memory cell to a sense amplifier based on a test mode entry signal output in a test mode. Thus, the state of operation with the transistor capacity can be created, and the inclination of the sense amplifier can be easily determined.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a test circuit in a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a test circuit in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing timing for entering a test mode in the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a part of a memory cell circuit and a peripheral circuit in a general semiconductor memory device.

FIG. 5 is a characteristic diagram showing an example of an internal waveform.

FIG. 6 is a diagram showing an example of a pattern in which data “H” is written in a TRUE cell and data “L” is written in a NOT cell.

FIG. 7 is a diagram showing a pattern in which data “H” is written in a TRUE memory cell and data “L” is written in a NOT memory cell.

FIG. 8 is a diagram for explaining the operation of the bit line pair D and DB under the condition of passing the defective bit line Y0 and the condition of becoming defective.

FIG. 9 is a circuit diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Latch circuit 2a, 2b, 2c Inverter 3, 4, 5 NAND circuit 6a, 6b Inverter 7 Output circuit 8 X-DECODER circuit 8a-8d Logic circuit 13a, 13b Transfer gate circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-5498 (JP, A) JP-A-5-182500 (JP, A) JP-A-10-199298 (JP, A) JP-A-4-1992 278479 (JP, A) JP-A-11-39899 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 11/401-11/4099

Claims (3)

(57) [Claims] 1. A test circuit, a logic circuit, and a sense amplifier, a semiconductor memory device for inputting and outputting data to the memory cell array by the word line and a bit line, the test circuit, the external Depending on the signal input to the terminal
The logic circuit takes a logic of a test mode entry signal output from the test circuit and an input signal of a row decoder circuit, and deactivates the word line. The sense amplifier operates according to the output signal of the logic circuit.
A semiconductor memory device operable even when a node line is in an inactive state . 2. The semiconductor memory device according to claim 1, wherein said logic circuit is incorporated in a decoder circuit for outputting an address signal to said memory cell. 3. A semiconductor memory device having a test circuit, a transfer gate circuit, and a sense amplifier for inputting / outputting storage data to / from a memory cell array via word lines and bit lines, wherein the test circuit comprises: Depending on the signal input to each external terminal
And outputs a test mode entry signal produced, the transfer gate circuit o based on the test mode entry signal output from the test circuit
Off, the memory cell data is transmitted to the sense amplifier.
The sense amplifier operates when the word line is in an inactive state.
A semiconductor memory device that is also operable .