JPH086809A - Field programmable gate array - Google Patents

Abstract

PURPOSE:To periodically read out and verify memory contents without stopping a system by using the field programmable gate array(FPGA) which enables the verification of circuit information during circuit operation. CONSTITUTION:In execution mode, one of the lines of a memory word line 10, i.e., one of the memory cells in a control memory 3 and one of the memory cells in a logic block 4 can be selected according to a memory address input 7 in parallel to the output of values to a switch control line 13 and a logic block output line 15. This selecting process is performed completely independently of output operation to the switch control line 13 and logic block output line 15. Then the values at inverting circuit input terminals in the selected memory cells of the control memory 3 and logic block 4 are supplied as memory data 12 to a memory control part 2 and outputted to the outside. Consequently, while the circuit operation is carried on, the memory contents can be read back.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention determines the operation of a digital circuit by electrically writing circuit information inside a device according to a program supplied from the outside and electrically rewriting the circuit information. The present invention relates to a so-called field programmable gate array (FPGA).

[0002]

2. Description of the Related Art Conventionally, a RAM for holding circuit information in an FPGA capable of electrically rewriting circuit information.
As (Random Access Memory), SRAM (Static Access Memory)
RAM) is used. The SRAM has the advantages that data can be written at high speed, that it can be rewritten many times, and that it is easy to handle. Due to these advantages, it can be used as a RAM for holding circuit information in FPGA. It is widely used.

By the way, when the circuit information written in the RAM is changed due to some electrical factor, the circuit operation becomes an abnormal operation as in the case where a mechanical failure occurs. Therefore, in that case, whether or not the contents of the RAM match the circuit information at the time of writing, that is,
It is necessary to verify whether the contents of the RAM have changed and, if so, rewrite the contents of the RAM to an appropriate one.

Conventionally, in order to externally verify whether or not the contents of RAM have changed, the operation of the circuit, that is, the operation of the device is completely stopped, and the FPGA is
A method of verifying the contents of the RAM has been adopted by setting a readback mode for reading the contents of the RAM from the outside to read (read back) all the contents of the RAM. An FPGA for verifying the contents of RAM by such a method is, for example, a device called LCA manufactured by Xilinx, Inc. in the United States.

[0005]

As described above, in order to perform readback with the conventional FPGA, it is necessary to suspend the operation of the device. Therefore, when the FPGA is used inside the actually operating system, it is necessary to suspend the system only to verify the contents of the RAM of the FPGA. This was extremely inconvenient.

Therefore, there is a demand for an FPGA capable of verifying the contents (circuit information) of the RAM of the FPGA without suspending the system. The present invention has been made in view of the above circumstances, and an object thereof is to provide a field programmable gate array capable of verifying circuit information without stopping the operation of the device.

[0007]

A field programmable gate array according to claim 1 constitutes a digital logic circuit according to circuit information contained in a program supplied from the outside to provide a desired function. A field programmable gate array in which the circuit information can be electrically rewritten, and means for providing the desired function by the digital logic circuit and at the same time reading the circuit information supplied to the inside of the device and outputting it to the outside of the device. It is characterized by having.

According to a second aspect of the field programmable gate array of the present invention, the logic realization portion of the digital logic circuit and the holding of the data of the connection portion which connects the plurality of logic realization portions to each other are respectively realized by random access memories. A field programmable gate array to be realized, wherein two read lines are independently connected to a memory cell inside each random access memory for realizing logic inside the device and for reading data to the outside of the device. Of the two read lines, a control mechanism for setting the read line for logic realization in the device to either the active state or the inactive state, and the read mechanism for reading the data to the outside of the device from the read lines of the two systems. Read line is either active or inactive With two systems of control mechanism of the control mechanism for the rectangular state independently control mechanism of the two systems is characterized in that operate independently.

Further, in the field programmable gate array according to a third aspect of the present invention, a plurality of logic elements for realizing logic by a look-up table having a random access memory composed of a plurality of memory cells, and the plurality of logic elements are mutually connected. A field programmable gate array having a connecting portion for connecting, and holding the data of the connecting portion by the random access memory,
The first address is determined from a first memory address line, a first address decoder connected to the input terminal of the first memory address line, and a plurality of memory output signals output from the plurality of memory cells. A first memory cell selecting means for selecting one memory output signal according to an output signal of the decoder is provided, and a second memory address line and a second memory address line are provided in the lookup table. From the plurality of memory output signals and a second address decoder connected to an input terminal of the second address decoder independently of the first memory cell selection means in response to the output signal of the second address decoder. And a second memory cell selection means for selecting one memory output signal.

[0010]

According to the above configuration, the circuit information is read (read back) outside the device separately from the read circuit for the random access memory to determine the circuit operation.
It also has a dedicated read circuit for controlling the read circuits of these two systems independently. Therefore, it is possible to read back the memory contents to the outside of the device while performing the actual circuit operation, and to verify the circuit information during the circuit operation.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. First, regarding the first embodiment of the present invention,
This will be described with reference to FIGS. FIG. 1 shows a field programmable gate array (FPG) according to the first embodiment.
FIG. 2 is a diagram for explaining the overall configuration of A: Field Programmable Gate Array), and as shown in this diagram, the FPGA according to the first embodiment comprises an FPGA chip 1. F
The PGA chip 1 has an SRAM (Static Random Access).
A control memory 3 including a RAM such as a memory), a logic block unit 4, a programmable switch unit 5, an input / output block unit 6, and a memory control unit 2 for controlling the units 3 to 6 are provided.

The FPGA chip 1 includes the above-mentioned respective parts 2 to 6,
A memory address input 7 and a memory control input 8 for inputting signals from the outside of the chip 1 to the memory control unit 2;
A memory data input / output 9 for inputting / outputting memory data between the outside and the memory control unit 2; The disable line 11, the switch control line 13 that connects the control memory 3 to the programmable switch unit 5 and the input / output block unit 6, respectively, the logical block input line 14 that connects the logical block unit 4 and the programmable switch unit 5, and the logical block output It includes a line 15, a wiring segment 16 connecting the programmable switch unit 5 and the input / output block unit 6, and a data line 17 for outputting data from the input / output block unit 6 to the outside of the chip 1. Further, the memory control unit 2 and the control memory 3 are connected to each other and the memory control unit 2 and the logic block unit 4 are connected to each other by a line for transmitting the memory data 12.

FIG. 2 is a diagram showing an internal configuration of the memory control unit 2 shown in FIG. 1. As shown in FIG. 2, the memory control unit 2 has a memory address input 7, a memory control input 8, and a memory data input. It is composed of an output 9, a memory word line 10, a memory write enable line 11, a memory data 12, an address decoder 20, and a branch selection circuit 21.

FIG. 3 is a diagram showing an internal structure of the control memory 3 shown in FIG. 1. As shown in FIG.
Is connected to the 0 bit line 36 and the 1 bit line 37 based on the memory cell 30 to which the corresponding memory word line 10 is connected and the signal and the memory data 12 supplied by the memory write disable line 11. An AND that outputs a signal to the switch control line 13 by ANDing the output signal from the corresponding memory cell 30 and the signal supplied by the memory write disable line 11 with the memory data control circuit 35 that controls the plurality of memory cells 30. It is composed of a gate 34.

The memory cell 30 includes a pass transistor 33-1 connected to the 0-bit line 36, a pass transistor 33-2 connected to the 1-bit line 37, and an inverting circuit 31 connected to the pass transistor 33-1. -1, and an inverting circuit 31-2 connected to the pass transistor 33-2,
It is composed of inverting circuit input terminals 32-1 and 32-2.

FIG. 4 is a diagram showing an internal configuration of the logic block unit 4 shown in FIG. 1. As shown in FIG. 4, the logic block unit 4 has lookup table memories 40-1 and 40-4.
0-2, ... Since the look-up table memories 40-1, 40-2, ... Have the same structure, hereinafter, the look-up table memory 40 will be representatively described.
The configuration of -1 will be described.

The look-up table memory 40-1 is
The major difference from the control memory 3 (see FIG. 3) described above is that it includes a look-up table address decoder 41 to which the logic block input line 14 is connected, the output signal from the corresponding memory cell 30, and the look-up. The number of tri-state buffers 43 to which the signals supplied via the look-up table word lines 42 connected to the respective output ends of the table address decoder 41 are provided as many as the memory cells 30 and the number of AND gates 34 are set. One is that the output signals from all the tri-state buffers 43 are applied to one input end of the AND gate 34, and the signal from the memory write disable line 11 is applied to the other input end. is there.

Next, the operation of the FPGA according to this embodiment will be described with reference to FIGS. In order to realize a desired function on the FPGA chip 1, the logic block unit 4,
In order to determine the internal values of the programmable switch unit 5 and the input / output block unit 6, load data (circuit information) is transferred from outside the FPGA chip 1 via the memory data input / output 9 to the control memory 3 and the logic block unit 4. Need to write to. The mode for performing this write operation is called the write mode.

Specifically, the above-mentioned write mode is entered by applying a signal to the memory control input 8 to indicate the shift to the write mode. When a signal indicating the shift to the write mode is applied to the memory control input 8, the signal value on the memory write disable line 11 becomes “0”, and the signal values on the switch control line 13 and the logic block output line 15 become It becomes "0" due to the function of the AND gate 34. Therefore, all the switches inside the corresponding programmable switch unit 5 and input / output block unit 6 are released.

Under such a condition, the memory address input from the memory address input 7 is decoded by the address decoder 20 and only one of the memory word lines 10 becomes active. This allows
In the control memory 3 and the logic block unit 4, one memory cell 30 corresponding to the activated memory word line 10 is selected.

In writing data to each memory cell 30 selected here, the memory data 12 output from the memory data input / output 9 through the branch selection circuit 21 is input to the memory data control circuit 35, This is performed by the circuit 35 by setting the value of one of the 0-bit line 36 and the 1-bit line 37 to "0" and the other value to "1".

When the above writing is completed, the FPGA
Shifts to an execution mode in which the circuit function based on the written data is realized and the data is processed. In particular,
A transition to the execution mode is made by applying a signal indicating the execution mode to the memory control input 8. Memory control input 8
When a signal indicating the execution mode is applied to the memory write disable line 11, the value on the memory write disable line 11 becomes "1". At this time, in the control memory 3, the value on the switch control line 13 is A
By the function of the ND gate 34, the corresponding memory cell 30
It becomes equal to the value at the inverting circuit input terminal 32-2 inside. Therefore, the data (the value at each inverting circuit input terminal 32-2) representing the connection / disconnection state of the switches inside the corresponding programmable switch unit 5 and the input / output block unit 6 stored in each memory cell 30 is It is transmitted to each switch inside the programmable switch unit 5 and the input / output block unit 6 via the switch control line 13.

On the other hand, in the logic block unit 4, for each of the look-up table memories 40-1, 40-2, ... Lookup that activates only one output terminal according to the value of the logic block input line 14. Due to the function of the up table address decoder 41, only one of the lookup table word lines 42 becomes active. Then, the tristate buffer 43 to which the activated line is connected operates and the buffer 43
Corresponding to the inverting circuit input terminal 32 inside the memory cell 30
The value of −2 is output to the logic block output line 15 via the AND circuit 34.

Further, in the execution mode, a value is output to the switch control line 13 and the logic block output line 15 in parallel with any one of the memory word lines 10 depending on the memory address input 7. That is, one memory cell 30 in the control memory 3 and one memory cell 30 in the logic block unit 4 can be selected. This selection processing is performed completely independently of the output operation to the switch control line 13 and the logic block output line 15 described above.

In each of the control memory 3 and the logic block section 4, the value of the inverting circuit input terminal 32-2 inside the selected memory cell 30 is the selected memory cell 30.
Is supplied to the memory control unit 2 as the memory data 12 from the 0 bit line 36 and 1 bit line 37 corresponding to the memory data control circuit 35, and is output from the memory data input / output 9 to the outside of the FPGA chip 1.

As described above, in this embodiment, the control memory 3 and the look-up table memory 40-1,
40-2, ... Have a read-out mechanism for determining a logic and a switch configuration at the time of execution with respect to a signal line separately drawn from each memory cell 30 in addition to a normal SRAM configuration, and particularly a look-up mechanism. Up table memory 40-
, 40-2, ... Have independent address decoders.

In actual use, the operation is divided into two modes, a writing mode and an execution mode, and in the execution mode, the two memory read mechanisms can be made to function completely independently. On the other hand, in write mode,
It is dedicated to writing data to the memory, all switch settings are released, and the flow of execution data of the circuit is prohibited. This is because, at the time of execution, rewriting the connection of the switch temporarily causes a collision of data lines inside the device. That is, the inside of the device is protected by prohibiting execution in the write mode.

Next, a second embodiment of the present invention will be described with reference to FIGS. 1, 2, 5 and 6. Since FIGS. 1 and 2 are common to the first embodiment, description of each part shown in these figures will be omitted. FIG. 5 is a diagram showing an internal configuration of the control memory 3 (see FIG. 1) which is a constituent element of the FPGA according to the second embodiment. The configuration of the control memory 3 shown in this figure is the first shown in FIG. The difference from the control memory 3 in the embodiment is that the AND gate 34 is removed and the value of the inverting circuit input terminal 32-2 is directly output to the switch control line 13.

FIG. 6 is a diagram showing an internal configuration of the logic block unit 4 (see FIG. 1) which is a constituent element of the FPGA according to the second embodiment. The configuration of the logic block unit 4 shown in this figure is shown in FIG. 4 in the first embodiment shown in FIG.
The difference is that the AND gate 34 is removed and the output signals of the tri-state buffers 43 are combined and directly output to the logic block output line 15.

Next, the operation of the FPGA according to this embodiment will be described with reference to FIGS. 1, 2, 5 and 6. First, in this embodiment, all the memory cells 30 are reset when the power is turned on. Next, when a signal indicating the shift to the write mode is applied to the memory control input 8, the write mode is set, and the signal value of the memory write disable signal 11 becomes "0". Under such a state, the memory address input from the memory address input 7 is decoded by the address decoder 20, and only one of all the memory word lines 10 becomes active. As a result, one active memory word line 30 is selected in each of the control memory 3 and the logic block unit 4.

In writing data to each memory cell 30 selected here, the memory data 12 output from the memory data input / output 9 via the branch selection circuit 21 is input to the memory data control circuit 35, respectively. This is performed by the circuit 35 by setting the value of one of the 0-bit line 36 and the 1-bit line 37 to "0" and the other value to "1".

In the write mode, the value of the switch control line 13 corresponding to the memory cell 30 in which the value is written becomes equal to the value of the inverting circuit input terminal 32-2 inside the corresponding memory cell 30, and the corresponding programmable The connection / disconnection state of the switches inside the switch unit 5 and the input / output block unit 6 is transmitted to each switch. Simultaneously with such operation, in the logic block section, only one output terminal is activated for each of the lookup table memories 40-1, 40-2, ... According to the value of the logic block input line 14. Due to the function of the look-up table address decoder 41, any one of the look-up table word lines 42 becomes active.

Then, the tri-state buffer 43 to which the activated line is connected operates and the value of the inverting circuit input terminal 32-2 in the memory cell 30 corresponding to the buffer 43 is transferred to the logic block output line 15. Is output. As described above, in the present embodiment, in the write mode, it is possible to simultaneously realize the actual circuit function and process the data.

On the other hand, when the writing of the load data is completed, the FPGA shifts to the readback mode in which the memory value is read out to the outside of the chip for verification. Specifically, when a signal indicating the shift to the readback mode is applied to the memory control input 8, the memory write disable signal 11 becomes "1", and the readback mode is set. At this time, the circuit is executed in the same manner as in the write mode described above, and therefore only the operation of the readback mechanism will be described here.

In the readback mode, the value is output to the switch control line 13 and the logic block output line 15, and at the same time, the memory word line 10 is selected according to the memory address input 7. This selection operation is completely independent of other operations. From the 0 bit line 36 and 1 bit line 37 corresponding to the memory cell 30 selected here, through the memory data control circuit 35, the memory cell 3
The value of the inverting circuit input terminal 32-2 inside 0 is output and finally output from the memory data input / output 9 to the outside of the chip 1.

As described above, also in this embodiment, the control memory 3 and the look-up table memory 40-1,
40-2, ... Have a read-out mechanism for determining a logic and a switch configuration at the time of execution with respect to a signal line separately drawn from each memory cell 30, in addition to a normal SRAM configuration, Lookup table memory 40-1,
40-2, ... Have independent address decoders. Further, in the present embodiment, the switch setting and the look-up table logic are valid even in the write mode.

Therefore, the circuit shape can be dynamically changed during the circuit operation. As described in the first embodiment, rewriting the connection of the switch during execution temporarily causes a collision of data lines inside the device, but the user carefully selects the area for writing. This makes it possible to avoid such a collision. As described above, the second embodiment is equipped with the power-on reset function in order to prevent data collision when the power is turned on. As described above, the FPGA according to the first and second embodiments of the present invention is extremely flexible as compared with the conventional FPGA.

[0038]

As described above, according to the field programmable gate array (FPGA) of the present invention,
It is possible to read circuit information at the same time during execution of a circuit operation, which is impossible with a conventional FPGA. That is, it is possible to verify the circuit information during the circuit operation. An FPGA that realizes a circuit function by a random access memory may be rewritten for some reason when it is continuously used for a long time, but especially in a large-scale system. Is used, it is difficult to temporarily stop the system for verification of circuit information.

Here, if an FPGA capable of verifying circuit information during circuit operation is used as in the present invention,
Since it is possible to read and verify the memory contents (circuit information) on a regular basis without stopping the system, even if it is applied to a large-scale system that is difficult to stop, the system information can be maintained while maintaining the reliability of the circuit information. Can be operated. That is, the reliability of the operation of the system can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a field programmable gate array (FPGA) according to first and second embodiments of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a memory control unit 2 of the FPGA.

FIG. 3 is a diagram showing a schematic configuration of a control memory 3 of the FPGA according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a schematic configuration of a logic block unit 4 of the FPGA.

FIG. 5 is a diagram showing a schematic configuration of a control memory 3 of an FPGA according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a schematic configuration of a logic block unit 4 of the FPGA.

[Explanation of symbols]

1 FPGA Chip 2 Memory Control Section 3 Control Memory 4 Logic Block Section 5 Programmable Switch Section 6 Input / Output Block Section 7 Memory Address Input 8 Memory Control Input 9 Memory Data Input / Output 10 Memory Word Line 11 Memory Write Disable Line 12 Memory Data 13 Switch control line 14 Logic block input line 15 Logic block output line 16 Wiring segment 17 Data line 30 Memory cell 34 AND gate 35 Memory data control circuit 40-1, 40-2, ... Look-up table memory 41 Look-up table address decoder 43 Tristate buffer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/177 0836-5K

Claims (3)

[Claims] 1. A field programmable gate array capable of forming a digital logic circuit according to circuit information included in a program supplied from the outside to provide a desired function and electrically rewriting the circuit information. A field programmable gate array comprising means for providing a desired function by the digital logic circuit and at the same time reading the circuit information supplied inside the device and outputting it to the outside of the device. 2. A logic realization part of a digital logic circuit,
A field programmable gate array that realizes holding of data in a connection portion that connects a plurality of logic realization portions to each other by a random access memory, and a memory cell inside each random access memory for logic realization inside the device. And for reading data to the outside of the device, two read lines are independently connected, and one of the two read lines for logic realization inside the device is active or inactive. A control mechanism of two systems, that is, a control mechanism for setting the state and a control mechanism for setting the read line for reading data to the outside of the device to either the active state or the inactive state of the read lines of the two systems. Be prepared independently, and the control mechanisms of the two systems should operate independently. A field programmable gate array, wherein. 3. A plurality of logic elements for realizing logic by a look-up table having a random access memory composed of a plurality of memory cells, and a connection portion for connecting the plurality of logic elements to each other. A field programmable gate array that realizes holding of the data by the random access memory, a first memory address line, a first address decoder to which the first memory address line is connected to an input terminal, and A plurality of memory output signals output from a plurality of memory cells, and a first memory cell selection unit that selects one memory output signal according to an output signal of the first address decoder. A second memory address line and a second memory address line connected to the input end in the up table. A second one that selects one memory output signal from the address decoder and the plurality of memory output signals, in response to the output signal of the second address decoder, independently of the first memory cell selection means. A field programmable gate array having a memory cell selection means.