JPH03139827A - Forming method for low resistance layer on silicon by ion implanting of two or more elements having different atomic radii - Google Patents

Abstract

PURPOSE:To highly integrate an integrated circuit by combination ion implanting of two or more types of N-type or P-type impurities having larger atomic radii than the silicon atomic radii, and N-type or P-type elements having small atomic radii, and then heat treating it to electrically activate the impurity to form a N-type or P-type low resistance layer on the silicon. CONSTITUTION:Two or more types of impurities having larger atomic radis than silicon atomic radium and having smaller atomic radium than the silicon atomic radium are combination ion implanted to a silicon. The ion implanted impurities are redistributed by a method of alleviating lattice distortion generated by themselves in the heat treating step for recovering silicon lattice damaged by ion implanting. In this case, the low resistivity of the silicon is provided by utilizing the increase in the solid solution of one or more ion implanted impurities thus forming a low resistance layer in the silicon.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to the emitter of a bipolar transistor of a silicon integrated circuit, the source of a field effect transistor, and the like.
It can be used to form N-type or P-type layers that require thinness and low resistance, such as drains, resistance/capacitance electrodes, etc.

(Prior Art) As the degree of integration of silicon integrated circuits increases, the dimensions of each element constituting the integrated circuit inevitably become smaller. As a result, the resistance of the emitters of bipolar transistors, the sources and drains of field-effect transistors, and the electrodes of resistors and capacitors in integrated circuits becomes higher, and the time constant determined by the product of circuit resistance and capacitance becomes larger. The frequency response of the integrated circuit deteriorates. Conventional techniques for improving the drop in frequency response of integrated circuits due to higher integration are: (a) Emitter region of bipolar transistor and source region of field effect transistor in silicon integrated circuit.
By adding impurities to the silicon in the drain region at high density,
Measure to reduce the resistivity of silicon in that area.

(b) Choose impurities with high solid solubility to add to silicon to reduce the resistivity of silicon.

(c) The emitter region of a bibolar transistor and the drain region of a field effect transistor in a silicon integrated circuit.
Expand the cross-sectional area and shorten the length of the source region, resistor/capacitor electrodes, etc. to reduce the resistance of those electrodes.

(d) Transient annealing such as laser annealing achieves a higher solid solubility of impurities in silicon than in the thermal equilibrium state.

(e) A shallow N-type or P-type layer is formed by ion-implanting an impurity compound such as fluoride into silicon.

(Problem to be Solved by the Invention) As the degree of integration of silicon integrated circuits increases, the dimensions of component elements become smaller. This goes against the trend toward higher integration of circuits. Therefore, one successful method for increasing the degree of integration of integrated circuits is to reduce the resistivity of silicon itself. However, the reduction in silicon resistivity is limited by the solid solubility of added impurities. That is, in order for the impurity in silicon to be electrically activated and contribute to reducing the resistivity of silicon, the impurity must occupy a lattice position in silicon. Impurities added at a density higher than their solid solubility occupy interstitial positions in silicon, form aggregates, aggregate at dislocations, etc., and are not electrically activated, resulting in silicon resistance. It reduces the mobility of charge carriers and increases the resistivity without contributing to reducing the resistivity. The existence of this solid solubility limit for impurities cannot be avoided due to the essential properties of silicon itself. Boron and boron are impurities with high solid solubility in silicon, and the thermal diffusion coefficient of these impurities is is about an order of magnitude larger than the thermal diffusion coefficient of other commonly used silicon impurities, making it unsuitable for forming shallow low-resistance layers.

Herein lies the limit of conventional techniques that have attempted to lower the resistivity of silicon by relying only on the inherent properties of the material.

Controlling the solid solubility of impurities in silicon by transient annealing is undesirable because the silicon surface becomes high temperature, resulting in the formation of surface morphology and lattice defects. In addition, the resistance of a shallow N-type or P-type layer formed by ion-implanting an impurity compound such as fluoride into silicon is
It will never be low.

(Means for Solving the Problems) The present invention involves implanting into silicon a combination of two or more different types of impurities, one with an atomic radius larger than the atomic radius of silicon, and the other with an atomic radius smaller than the silicon atomic radius, and then During the heat treatment process to restore the silicon lattice destroyed by ion implantation, when the implanted impurities redistribute in such a way that they mutually relax the lattice strain caused by their own presence;
This method takes advantage of the phenomenon in which the solid solubility of one or several of the ion-precipitated impurities increases to lower the resistivity of silicon and form a low resistance layer in silicon. .

Impurities such as phosphorus, arsenic, and antimony are used to make silicon an N-type conductor, and impurities such as boron, gallium, and indium are used to make silicon a P-type conductor. The atomic radius of these impurities is 1.17 ohm for silicon, 1.10 ohm for phosphorus, 1.18 ohm for arsenic, and 1°36 ohm for antimony. Also, P-type impurity boron has a strength of 0.9 ohms, gallium has a strength of 1.26 ohms, and indium has a strength of 1.42 ohms. Several combinations of N-type impurities, P-type impurities, N-type impurities and P-type impurities, etc. are selected and ions are implanted into silicon. During the heat treatment process to restore the silicon lattice destroyed by ion implantation and electrically activate the ion-implanted impurities to obtain a low-resistance layer, the ion-implanted impurities were generated by their own presence. The lattice strains are redistributed in a mutually relaxing manner. During this redistribution, the ion-implanted 2
The phenomenon in which the solid solubility of one or several impurities increases is utilized.

In practicing the present invention, impurities may be ion-implanted into silicon at the same depth or at different depths. In the latter case, impurities implanted deep into the silicon are redistributed during heat treatment in such a way that they overlap with the distribution of impurities implanted near the surface of the silicon.

Whether the impurities are implanted into the silicon at the same depth or at different depths,
The rate of redistribution of these impurities may be suppressed by the thermal diffusion rate of impurities ion-implanted near the silicon surface, or by complexes of impurities or impurities and lattice defects formed during the early stage of heat treatment. Suppressed by thermal diffusion rate. In general, the thermal diffusion rate of the composite is slow compared to impurity thermal diffusion. If you choose an impurity that has a slow thermal diffusion rate in the silicon for ion implantation near the silicon surface, or choose a combination of impurities that will form a complex with a slow thermal diffusion rate, you can implant it shallowly near the silicon surface. Furthermore, a low resistance layer can be created.

(Example) FIG. 1 shows one example. ■ is N for silicon
Arsenic, which is a form impurity, was ion-implanted at an amount of 1x1016 atoms per unit area at an energy of 40 kiloelectron volts, and phosphorus was ion-implanted at an amount of 3xlO14 atoms per unit area at an energy of 20 kiloelectron volts, followed by heat treatment for 30 hours. This is the surface resistivity of heat-treated samples at different heat-treatment temperatures for minutes. in this case.

The ion implantation amount is set so that the lattice strain caused by the implanted arsenic in the silicon is compensated for and eliminated by the lattice strain caused by the phosphorus ion implanted so as to overlap the arsenic ion implantation distribution. .

In addition, ■ in Figure 1 is for comparison with the technology of the present invention.
The arsenic distribution was made to be approximately three times wider than that of the silicon N layer prepared using the conventional technique, that is, the sample of the present invention with the surface resistivity shown in (■) in Figure 1, to achieve a low resistance. The conditions for obtaining a layer are as follows: arsenic alone at 1x per unit area with an energy of 150 kiloelectron volts.
This figure shows the dependence of the surface resistivity of heat-treated silicon on the heat treatment temperature when only 1O" atoms were ion-implanted and the heat treatment time was 30 minutes. Even if the samples with the surface resistivities shown in the figure are the same, the distribution of arsenic is wider in the sample with the surface resistivities shown in ■ than in the sample with the surface resistivities shown in ■. With conventional technology, the solid solubility of arsenic does not change depending on the energy of ion implantation, so the distribution of arsenic is better when ions are implanted with an energy of 150 kiloelectron volts than when arsenic is implanted with an energy of 40 kiloelectron volts. Approximately 3
It becomes twice as wide, and its surface resistivity also increases by about one-third. Despite these poor ion implantation conditions, it can be seen that the resistance of the N-type silicon layer made according to the present invention is considerably lower than that made using conventional techniques.

■ in Figure 2 is silicon that is ion-implanted with arsenic and phosphorus under the same conditions as the sample whose surface resistivity was measured as shown in ■ in Figure 1, and then heat-treated at 950 degrees Celsius for 10 minutes.
Silicon was ion-implanted with 1xlO6 atoms per unit area at an energy of kiloelectron volts and heat-treated at 950 degrees Celsius for 10 minutes. This is a sketch of a transmission electron micrograph of silicon heat-treated at 950 degrees for 10 minutes.Dislocations remain at a considerable density in silicon that has been ion-implanted with only arsenic or phosphorous; No dislocations have been observed in ion-implanted silicon.In other words, the silicon lattice strain caused by arsenic ion implantation, which has a larger atomic radius than silicon, is compensated by phosphorous ion implantation, which has a smaller atomic radius than silicon.
It appears that it has disappeared.

FIG. 3 compares the solid solubility of impurities and the thermal diffusion of impurities in N-type silicon layers made according to the present invention and the conventional technique. ■ in Figure 3 shows that in order to make an N-type silicon layer,
Arsenic was ion-implanted at an amount of 1x1016 atoms per unit area at an energy of 40 kiloelectron volts, and phosphorus was ion-implanted at an amount of 3xlO'4 per unit area at an energy of 20 kiloelectron volts.

This figure shows the electron density distribution of a sample heat-treated at 950 degrees Celsius for 30 minutes. In addition, ■ in Figure 3 shows the electron density distribution obtained using the conventional technique, in which only arsenic was ion-implanted into silicon, 1xlo'' atoms per unit area at an energy of 40 kiloelectron volts, and heat-treated at 950 degrees Celsius for 30 minutes. This is what is shown.

The electron density distribution O in an N-type silicon layer made by ion-implanting arsenic and phosphorus according to the present invention is compared to the electron density distribution O in an N-type silicon layer made by ion-implanting only arsenic into silicon using the conventional technique. It is slightly shallower than the distribution (2), and its maximum electron density is increased to 2.1×1020 per unit volume compared to 1.2×1020 per unit volume in the conventional technology. In other words, by ion-implanting arsenic and phosphorus into silicon, the thermal diffusion of impurities was suppressed and the solid solubility of impurities was increased.

(Effects of the Invention) As described above, the present invention uses existing ion implantation technology, heat treatment technology, etc. to ion-implant two or more types of elements with different atomic radii, thereby repairing the silicon lattice destroyed by ion implantation. During the heat treatment to recover and electrically activate the implanted impurities, when those implanted impurities redistribute in such a way that they mutually relax the lattice strains caused by their own presence. , by utilizing the phenomenon in which the solid solubility of ion-implanted impurities increases, and by determining the rate of redistribution of these impurities depending on the thermal diffusion rate of impurities ion-implanted near the surface, complexes of impurities, or impurities. This is a new technology that is extremely effective in creating a shallow, low-resistance layer near the silicon surface by taking advantage of the thermal diffusion rate suppressed by a complex of lattice defects.

It has been shown that the technique according to the present invention can reduce surface resistivity, reduce dislocation density, increase solid solubility of impurities, and suppress diffusion of impurities, compared to conventional techniques. For example, in addition to arsenic ion implantation, 3% of the number of arsenic ions are implanted and heat treated silicon has a significantly lower surface resistivity than silicon that has only arsenic ion implanted and heat treated (Figure 1). The dislocation density is drastically reduced (Figure 2), the diffusion of arsenic is suppressed, and the solid solubility of arsenic is increased (Figure 3).
Was.

Silicon is a material that is physically stable and highly reliable. Furthermore, the device manufacturing technology is far more sophisticated than that of other semiconductors, and silicon integrated circuits can be produced at low cost. For the time being, increasing the degree of integration of this silicon integrated circuit and increasing its speed is a good idea from the standpoint of development time and cost. The present invention makes it possible to prevent the deterioration of response characteristics due to increased integration using existing technology without developing any new technology, and can greatly contribute to the current highly information-oriented society. It is.

[Brief explanation of the drawing]

1, 2 and 3 show examples of the present invention. This study shows that it is possible to form a shallow, low-resistance N-type layer on the surface of silicon by implanting ions with arsenic, which is a typical impurity for making silicon N-type, and then heat-treating it. In this example, the ion implantation distribution of arsenic and the ion implantation distribution of phosphorus overlap, and the lattice strain based on the difference in the atomic radius of the silicon atom and the ion implanted impurity, whose atomic radius is 1.17 ohmstron, is The sample was prepared by selecting the amount of ion implantation to compensate for the amount of arsenic, which has a radius of 1.18 ohmstrong, and the amount of phosphorus, which has an atomic radius of 1.10 ohmstrong. In this case, the ion implantation amount of phosphorus may be 3% of the ion implantation amount of arsenic, and the order of ion implantation is such that arsenic, which has a large atomic weight, is first ionized into silicon in order to minimize the disturbance of the ion implantation distribution due to the notucon phenomenon. followed by ion implantation of phosphorus. ■ in Figure 1 indicates that 40% of arsenic, an N-type impurity, is added to silicon.
Ion implantation of 1xlO" atoms per unit area at an energy of kiloelectron volts, and phosphorus ion implantation of 3xlO" atoms per unit area at an energy of 20 kiloelectron volts.
This is the surface resistivity of a sample prepared by the conventional technique for comparison with the technique of the present invention. In other words, arsenic is 150 kiloelectron volts per unit area.
This figure shows the surface resistivity of silicon that was heat-treated by ion-implanting only "xlO" atoms and heat-treating at different temperatures for 30 minutes. The surface resistivity was measured by the four-terminal method. Silicon is ion-implanted with arsenic and phosphorus under the same conditions as the sample whose surface resistivity was measured as shown in ■ in Figure 1, and then heat-treated at 950 degrees Celsius for 10 minutes.
Ion implantation of 1xlO'' atoms per unit area with an energy of kiloelectron volts was carried out at 950 degrees Celsius.
After heat treating silicon for 0 minutes, the phosphorus is heated to 3x10 phosphorus per unit area at an energy of 20 kiloelectron volts.
This figure shows a sketch of a transmission electron g-transparent photograph of silicon in which only four atoms were ion-implanted and heat-treated at 950 degrees Celsius for 10 minutes. Transmission electron micrographs were taken using an electron beam with an energy of 100 kiloelectron volts on samples thinned by polishing and chemical etching. Figure 3 compares the solid solubility of impurities and thermal diffusion of impurities in N-type silicon layers made by the present invention and the conventional technology. After ion-implanting l x l O" W atoms per unit area, and further ion-implanting 3 x lO" phosphorous atoms per unit area at an energy of 20 kiloelectron volts, the silicon was heat-treated at 950 degrees Celsius for 30 minutes. Electron density distribution, ■ in Figure 3 is a conventional technique in which only arsenic is ion-implanted at an energy of 40 kiloelectron volts at a rate of 1xlo"r!f per unit area, and then heat-treated at 950 degrees Celsius for 30 minutes. Figure 1 shows the electron density distribution of a material.

Claims (1)

[Claims] N has an atomic radius larger than that of silicon.
After ion-implanting a combination of two or more elements, such as an N-type or P-type impurity and an N-type or P-type impurity with a small atomic radius, heat treatment is performed to electrically activate the impurities to form an N-type or P-type impurity into silicon. A method of forming a shaped low resistance layer.