JP2943369B2 - Semiconductor substrate manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for gettering contaminants such as heavy metals and compounds in a method for manufacturing a semiconductor single crystal substrate.

[0002]

2. Description of the Related Art In semiconductor technology, the miniaturization of processes has been increasingly advanced, and contamination by processes and accompanying device malfunctions have become important problems. Gettering is a technique for stabilizing device characteristics and improving yield by diffusing contaminants out of a device formation region. There are roughly two types of conventional gettering technologies. One is intrinsic gettering (hereinafter abbreviated as IG method. For example, JP-A-63-51).
646), which utilizes the precipitation of interstitial oxygen contained in a CZ single crystal. The other is extrinsic gettering (hereinafter abbreviated as EG method.
No. 9733), which performs gettering by giving mechanical damage to the substrate.

In the above-mentioned IG method, a technique is required which allows interstitial oxygen in the substrate to be successfully deposited outside the element formation region. Usually, two heat treatments, namely, the formation of precipitate nuclei by low-temperature heat treatment and the formation of nuclei by high-temperature heat treatment, are performed in combination. Further, since the oxygen concentration in the pulled single crystal ingot changes, to obtain the same effect for all substrates,
Highly controlled pulling and heat treatment techniques are required. Conversely, it is difficult to stabilize the effect. However,
Since no processing (such as film formation) is performed from the outside, it can be said that this is a clean technology.

On the other hand, the EG method involves mechanical damage due to sand blast, phosphorus diffusion, ion implantation, polySi and Si ₃ N _4.
Is applied to the semiconductor substrate by mechanical damage or stress by depositing on the back surface of the semiconductor substrate, and heavy metal is gettered by the Cottrell effect on the dislocation or damage. This EG method can be easily performed and the effect is stable at first, but the damage is recovered during the heat treatment such as the element forming process, and the gettering effect does not last for a long time. There is a disadvantage that. Therefore, formation of damage that is difficult to recover by heat treatment is an important factor in the EG method. Further, in the case of the EG method in which a polySi or Si ₃ N ₄ layer is formed, a film is formed not only on the back surface but also on the front surface. It is not only an increase, but also a method that is vulnerable to contamination.

[0005]

As described above, the conventional IG method has problems in manufacturing time, man-hour, and cost, and requires highly controlled pulling technology and heat treatment technology. Is difficult to stabilize. In the conventional EG method, in the case of a method using mechanical damage or ion implantation damage, the damage is immediately recovered by heat treatment during an element forming process, and gettering does not last long. Poly Si or Si ₃ N ₄
In the method of forming a layer, there is a problem that device characteristics are deteriorated due to residual damage or contamination due to surface treatment.

The present invention has been made in order to solve the problems of the prior art as described above, and the manufacturing time is significantly shorter than that of the conventional IG method, and the cost can be reduced.
It is an object of the present invention to provide a method for manufacturing a semiconductor substrate having a gettering action, in which the gettering action lasts longer than the conventional EG method and the wafer is less contaminated during the getter process.

[0007]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. That is, in the present invention, after performing high-concentration ion implantation into a semiconductor substrate to form an amorphous layer, rapid thermal annealing (rapid annealing) is abbreviated as RTA. 2), a large number of residual defects are left at the interface between the amorphous and crystalline layers, and these residual defects are used as nuclei for getter sinks.

[0008]

The residual defects formed at the interface between the amorphous layer and the crystalline material by the above-mentioned steps are not recovered because the secondary defects grow even by the subsequent process heat treatment. Therefore, the action of gettering lasts long. In addition, ion implantation and R
Since only TA is performed, wafer contamination during the getter process is reduced as compared with other EG methods.

[0009]

FIG. 1 is a sectional view showing the steps of an embodiment of the present invention. In FIG. 1, first, as shown in FIG. 1A, an Si single crystal substrate 1 is prepared. As the single crystal substrate 1, in the case of a large-diameter wafer, a substrate made by the CZ method is generally used. Next, as shown in (b), a group IV element such as Si or C or a dopant of the same conductivity type as the substrate, for example, a large heavy element such as Sb + or As + in the case of an n-type substrate, as shown in FIG. P can also be implanted to form the amorphous layer 2. Next, as shown in (c), RTA (Rapid Thermal Annealing) is performed. The temperature is about 900 ° C. to 1100 ° C. and the time is about several tens of seconds. As a result, a residual defect layer 3 remains at the interface between the amorphous layer 2 and the crystalline layer. Further, as shown in (d), the secondary defect layer 4 grows by the subsequent process heat treatment, so that the residual defect is not easily recovered.

Next, the operation will be described. Gettering is the reverse-concentration diffusion of substances that are present in a near-homogeneous state.
Use the effect. The Cottrell effect means that heavy metals such as Cu and Fe are attracted to a strain field formed by dislocations. Therefore, how efficiently dislocations are formed and stabilized is important in gettering, particularly in the case of the EG method. When ions are implanted into a silicon substrate, the implanted ions collide with Si atoms at lattice sites and damage the silicon substrate. When the implanted dose is small, it becomes a point defect, but as the implanted dose increases, it becomes cluster-like, and when it is more than the critical dose (up to 5 × 10 ¹⁴ / cm ^{2 for} Si +), it becomes amorphous (2 in FIG. 1). . RTA is performed on the wafer in this state. The temperature is about 900 to 1100 ° C., and the time is at most about several tens of seconds. Such R
When TA is performed, residual defects (3 in FIG. 1) remain between the amorphous layer and the crystal layer. This is because a rapid and short-time heat treatment causes random recrystallization, which leaves defects near the interface. Such defects are difficult to be eliminated by the subsequent heat treatment and remain during the process of forming the element. The interstitial oxygen is attracted to the strain field generated near this defect to precipitate SiO ₂ . The interstitial silicon generated by this is OSF (OxidationInd
ucet Stacking Fault (oxidation-induced stacking fault). These defects collectively serve as getter sinks to getter heavy metals. In particular, in a miniaturization process in which the temperature of the process is being reduced, the device acts as a powerful getter sink. As a result of the above-described steps, the gettering of the contaminants in the element formation region was surely performed, so that the withstand voltage characteristics of the formed element were improved. In particular, the withstand voltage failure of the n-channel device was greatly reduced from 60% of the conventional device to 5%, and a clear effect was confirmed.

FIGS. 2 and 3 are electron micrographs (magnification: about 23,000 times) of the actual crystal structure inside the silicon substrate.
FIG. 2 shows ion implantation into the silicon substrate 1 and RTA
3 shows an electron micrograph of a cross section of the wafer after the heat treatment, and FIG. 3 shows an electron micrograph of a cross section of the wafer after the heat treatment. FIG. 2 clearly shows the residual defect layer 3 and FIG. 3 shows the secondary defect layer 4 clearly.

FIG. 4 is a sectional view showing a manufacturing process of another embodiment of the present invention. In this embodiment, the amorphous layer 2 is formed deep from the back surface by performing ion implantation for forming an amorphous layer at a high energy of about several MeV. By doing so, the interface between the amorphous layer 2 and the crystalline layer becomes 2
As a result, two residual defect layers 3 and 3 'are formed by performing RTA. As a result, more getter sinks can be created, and a stronger gettering action can be provided. Further, by deeply implanting ions, there is also an effect that the getter sink and the element formation region are brought closer to each other, whereby a stronger gettering action can be obtained.

Next, FIG. 5 is a sectional view showing a manufacturing process of a third embodiment of the present invention. In this embodiment, an amorphous layer 2 is formed in a deep portion of the surface by performing high-energy ion implantation of about several MeV from the surface of a silicon substrate 1, and RTA is performed to form a two-layer residual defect layer 3. 3 ′. If the getter sink is formed below the element formation region on the substrate surface as described above, the distance between the getter sink and the element formation region can be further reduced.

[0014]

As described above, according to the present invention, an amorphous layer is formed in a semiconductor substrate by ion implantation, and thereafter, a heat treatment by rapid thermal annealing is performed to form a residual defect layer. With this configuration, it is difficult for the defect layer to be easily recovered by a heat treatment during a later element formation process, and the gettering action lasts longer than in the conventional EG method. Since it can be performed in a very short time as compared with the IG method, the cost can be reduced and the method is more stable than the IG method. The contamination of the wafer during the getter process is less than in other EG methods. And other excellent effects. Further, in the embodiment shown in FIG. 4, since the number of defect layers is two, the getter function becomes stronger. In the embodiment shown in FIG. 5, the gettering action is further enhanced because the getter sink and the element formation region are close to each other.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a view showing an electron micrograph of a crystal structure inside a silicon substrate after RTA.

FIG. 3 is a view showing an electron micrograph of a crystal structure inside a silicon substrate after heat treatment.

FIG. 4 is a sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Amorphous layer 3, 3 '... Residual defect layer 4 ... Secondary defect layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/322 H01L 21/265

Claims (1)

(57) [Claims] A semiconductor substrate having a depth not to be an element formation region;
Forming an amorphous layer by ion implantation in a portion, above the semiconductor substrate, the Rapid <br/> de Thermal the amorphous layer I by the annealing of the single heat treating the entire substrate at once
Forming a residual defect layer in an interface region with a crystal layer , wherein the contaminant deteriorating device characteristics is gettered by the residual defect layer.