JPH0311694A - Connection of semiconductor ic - Google Patents
Connection of semiconductor icInfo
- Publication number
- JPH0311694A JPH0311694A JP14400689A JP14400689A JPH0311694A JP H0311694 A JPH0311694 A JP H0311694A JP 14400689 A JP14400689 A JP 14400689A JP 14400689 A JP14400689 A JP 14400689A JP H0311694 A JPH0311694 A JP H0311694A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- terminal
- printed wiring
- leads
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 20
- 238000003825 pressing Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 19
- 238000002844 melting Methods 0.000 abstract description 6
- 230000008018 melting Effects 0.000 abstract description 6
- 239000002245 particle Substances 0.000 description 7
- 239000011295 pitch Substances 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 239000011324 bead Substances 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 3
- 238000002788 crimping Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- -1 solder plating Chemical class 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000012798 spherical particle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
ント配線基板表面に搭載し、電気的・機械的に接合する
ＩＣの接合方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of bonding an IC, which is mounted on the surface of an integrated circuit board and electrically and mechanically bonded.
近年の電子機器の多機能化、小型軽量化、薄型化等の進
展に伴い、これらに用いられる半導体搭載用プリント配
線基板や、高集積化が進む半導体ＩＣについても、ファ
インピッチ化対応が強く求められてきている。特に、半
導体ＩＣについて、樹脂封止半導体ＩＣパッケージにつ
いては、リードピッチが０．５ ｍｍ以下のパッケージ
が出現し実用化が進んでいる。In recent years, as electronic devices have become more multifunctional, smaller, lighter, and thinner, there is a strong demand for fine-pitch printed wiring boards used in these devices, as well as semiconductor ICs that are becoming increasingly highly integrated. It's been getting worse. In particular, regarding semiconductor ICs, packages with lead pitches of 0.5 mm or less have appeared and are being put into practical use as resin-sealed semiconductor IC packages.
半導体ＩＣをプリント配線基板に搭載する方法は、従来
、半田を溶融して接合する方法が広く一般的に用いられ
ている。即ち、■半導体搭載用プリント配線基板のスル
ーホール部に予め樹脂モールド封止された半導体ＩＣの
リードを差し込み、プリント配線基板の半導体ＩＣを挿
入した面とは反対側より、フローソルダーその他の方法
により溶融半田によって半導体ＩＣのリード部とスルー
ホールとを電気的に接続する方法、■半導体搭載用プリ
ント配線基板の半導体ＴＣ接続用端子部に半田ペースト
を印刷し、次に表面実装用の半導体ＩＣのリードビンを
前記端子部と位置合わせし、必要に応じて接着前で仮止
めした後、半田ペーストを遠赤外線加熱、レーザー光加
熱、ペーパーフェイズリフロー加熱等の方法によって溶
融して接着する方法等、或いは、ＴＡＢ （テープオー
トメーテドボンディング）方式の如く、インナーリード
ポンディングによりリードと接続し、さらに樹脂封止さ
れた半導体ＩＣを金メツキ又は半田メツキさこれた半導
体搭載用プリント配線基板の接続端子部に位置合わせし
た後、加熱することにより前記リードと基板の接続端子
部を接合する方法等が用いられている。Conventionally, a widely used method for mounting a semiconductor IC on a printed wiring board is to melt and bond solder. In other words, ■ Insert the leads of a semiconductor IC that has been molded in resin into the through-hole of a printed wiring board for mounting semiconductors, and then solder the leads of the printed wiring board by flow soldering or other methods from the opposite side of the printed wiring board to the side where the semiconductor IC was inserted. A method of electrically connecting the lead part of a semiconductor IC and a through hole using molten solder, ■ Printing solder paste on the terminal part for semiconductor TC connection of a printed wiring board for mounting a semiconductor, and then After aligning the lead bin with the terminal part and temporarily fixing it before bonding if necessary, melting and bonding the solder paste by a method such as far infrared heating, laser beam heating, paper phase reflow heating, etc., or , as in the TAB (tape automated bonding) method, the leads are connected by inner lead bonding, and the resin-sealed semiconductor IC is then gold-plated or solder-plated to the connecting terminal part of the printed wiring board for mounting the semiconductor. After alignment, a method is used in which the leads and the connecting terminal portions of the substrate are bonded by heating.
しかし、従来の半田溶融法による接続方法によれば、半
田ブリッジによる端子回路間ショー１−に基づく接続不
良や、半田を溶融するための高温による配線基板や搭載
する電子部品に対するダメージが避けられない問題があ
った。However, according to the conventional connection method using the solder melting method, connection failures due to short circuits between terminals due to solder bridges and damage to the wiring board and mounted electronic components due to the high temperature required to melt the solder are unavoidable. There was a problem.
本発明は、これらの従来法の欠点を改良し、新規接続方
法を桿案するものであり、半田溶融温度（通常２２０〜
２６０°Ｃ）以下の温度で接続することが可能であり、
且つ、ファインピッチ対応肩面
能で、個４信頼性に優れた半導体ＩＣの接続方法を提供
することを目的としたものである。The present invention improves the shortcomings of these conventional methods and proposes a new connection method.
It is possible to connect at temperatures below 260°C,
Another object of the present invention is to provide a method for connecting semiconductor ICs that is capable of supporting fine pitches and has excellent reliability.
本発明は、半導体搭載用プリント配線基板の半導体接続
用回路端子部を含み該回路端子部に囲まれた領域全体、
又は、半導体ＩＣの周囲に設けられたリードピンの一列
分に対応する半導体接続用回路端子部全体を含む領域に
、異方性導電フィルムを載置し仮止めした後、前記回路
端子部と半導体ＩＣのリードとを位置合わせすると共に
、リード／回路端子部を加熱・加圧して接続することを
特徴とする半導体ＩＣの接続方法である。The present invention relates to the entire area of a printed wiring board for mounting a semiconductor including a circuit terminal portion for connecting a semiconductor and surrounded by the circuit terminal portion;
Alternatively, after placing and temporarily fixing an anisotropic conductive film on an area including the entire semiconductor connection circuit terminal portion corresponding to one row of lead pins provided around the semiconductor IC, the circuit terminal portion and the semiconductor IC are placed. This method of connecting a semiconductor IC is characterized by aligning the leads and connecting the leads/circuit terminals by heating and pressurizing them.
本発明の対象となる半導体ＩＣは、表面実装タイプの半
導体ＩＣであり、所謂ＳＯＰ （スモールアウトライン
パッケージ）、ＤＩＰ（デュアルインラインパッケージ
）、ＱＦＰ（クアドフラットパッケージ）等のリード付
き半導体ＩＣは全て用いることができる。The semiconductor IC to which the present invention is applied is a surface-mount type semiconductor IC, and all semiconductor ICs with leads such as so-called SOP (Small Outline Package), DIP (Dual Inline Package), and QFP (Quad Flat Package) can be used. I can do it.
半導体搭載用プリント配線基板としては、従来仕様の半
導体搭載用基板は全て用いることが可能である。即ち、
ガラス／エポキシ樹脂銅張積層板を通常の回路加工法に
よって回路形成した後、接続端子部を半田メツキ、金メ
ツキ、錫メツキ等の各種金属メツキを施した半導体搭載
用基板は全て用いることができる。又更に、従来は不可
能であった０、５〜０．１ ｍｍのファインピッチで回
路形成した有機基板プリント配線板であっても、更には
接続端子部が銅箔又は上記の各種メツキを施した場合の
いづれも適用可能である。As the printed wiring board for mounting a semiconductor, any semiconductor mounting board of conventional specifications can be used. That is,
Any semiconductor mounting board can be used in which a circuit is formed on a glass/epoxy resin copper-clad laminate using normal circuit processing methods, and then the connection terminals are plated with various metals such as solder plating, gold plating, tin plating, etc. . Furthermore, even in organic printed wiring boards with circuits formed at a fine pitch of 0.5 to 0.1 mm, which was previously impossible, the connection terminals can be coated with copper foil or the various platings mentioned above. Any of these cases is applicable.
異方性導電フィルムは、高い絶縁性を有する樹脂または
樹脂組成物に導電性粒子を分散させたフィルムであり、
電極パターン間に挿入し加熱圧着することで、フィルム
の厚み方向には導通性を示し、面方向には絶縁性を示す
フィルムである。本発明で使用する異方性導電フィルム
としては、半導体ＩＣや、各種の電子部品を搭載した実
装基板に求められる要求特性に基づいて、圧着後の高倍
頼性タイプが好んで用いられる。Anisotropic conductive film is a film in which conductive particles are dispersed in a resin or resin composition having high insulation properties,
By inserting the film between electrode patterns and heat-pressing it, the film exhibits conductivity in the thickness direction and insulation property in the plane direction. As the anisotropic conductive film used in the present invention, a high-reliability type after crimping is preferably used, based on the required characteristics for semiconductor ICs and mounting boards on which various electronic components are mounted.
異方性導電フィルムは、導電性粒子としてニッケル粉、
半田粉や、プラスチックビーズに金属メキした球状粒子
が用いられ、電極とメカニカルに接触することで導通を
発現するが、半田粉を使用したタイプでは、粒子が柔ら
かいため、圧着後の形状は圧着前の直径の１．５倍から
４倍程度に押しつぶされて接触面積が大きくなり、バイ
ンダーとして働く絶縁性樹脂がこれを接続用端子部とリ
ード間に固定して安定な導電性を示し、またプラスチッ
クビーズに金属メツキをした粒子の場合、もとのプラス
チックビーズの固さによってメカニズムが異なると考え
られる。即ち、柔らかい粒子の場合、粒子は球状から楕
円状におされ反発力を持ったままバインダー樹脂によっ
て接続端子部とり一ト間に固定され、安定な導電性を示
す。これに対して固い粒子の場合、メツキされた導電性
粒子は半導体搭載用プリント配線基板の電極の金属或い
は金属メツキ層にめりこむ状態で圧着され、更に、バイ
ンダー樹脂によって接続端子部とリードに固定され、安
定な導電性を示すと考えられる。Anisotropic conductive film uses nickel powder as conductive particles,
Solder powder or spherical particles made of metal-plated plastic beads are used, and conduction occurs when they come into mechanical contact with electrodes. However, in the type that uses solder powder, the particles are soft, so the shape after crimping is the same as before crimping. The contact area increases by being crushed to about 1.5 to 4 times the diameter of the lead, and the insulating resin that acts as a binder fixes this between the connection terminal and the lead, exhibiting stable conductivity. In the case of beads with metal plating, the mechanism is thought to differ depending on the hardness of the original plastic beads. That is, in the case of soft particles, the particles are changed from spherical to elliptical and are fixed between the connection terminals by the binder resin while retaining repulsive force, and exhibit stable conductivity. On the other hand, in the case of hard particles, the plated conductive particles are crimped by sinking into the metal or metal plating layer of the electrode of the printed wiring board for mounting semiconductors, and are further fixed to the connection terminals and leads with a binder resin. , it is thought to exhibit stable conductivity.
本発明においては第１図に示したように、先ず半導体部
品を接続するための回路端子部（２）を初めとする回路
を形成したプリント配線基板（１）を用意しくａ図）、
次いで回路端子部（２）を覆うように異方性導電フィル
ム（３）を載せて仮止めする（ｂ図）。In the present invention, as shown in Fig. 1, first, a printed wiring board (1) on which a circuit including a circuit terminal part (2) for connecting semiconductor components is formed is prepared (Fig. a),
Next, an anisotropic conductive film (3) is placed and temporarily fixed so as to cover the circuit terminal portion (2) (Figure b).
半導体ＩＣ（４）を、そのリード（５）が回路端子部（
２）と合致するように位置合せしてプリント配線基板（
１）に搭載し、リード（５）部を加熱・加圧して回路端
子部（２）に接合する。この時、異方性導電フィルム（
３）は、加熱・加圧された部位のみが導電性を持つよう
になり、リード（５）と回路端子部（２）とが電気的に
接続される。The semiconductor IC (4) has its leads (5) connected to the circuit terminal section (
2) and align it to match the printed wiring board (
1), and the lead (5) part is heated and pressurized to join it to the circuit terminal part (2). At this time, an anisotropic conductive film (
In 3), only the heated and pressurized portion becomes conductive, and the lead (5) and the circuit terminal portion (2) are electrically connected.
プリント配線基板（１）上の異方性導電フィルム（３）
を被覆する範囲は、第２図に示したように、半導体ＩＣ
の周辺に出ている多数のリードピン（６）の全体を含む
ような範囲に対応する領域とするのが良い。具体的には
、第２図（ａ）のように半導体ＩＣの１個分のリードビ
ン（６）全部を含むように点線で囲まれた範囲Ａに対応
する領域でも良いし、また、第２図（ｂ）のように半導
体ＩＣの１つの辺に出ている１列分のリードピン（６）
を含むように点線で囲まれた範囲Ｂに対応する複数の領
域に分けて被覆しても良い。Anisotropic conductive film (3) on printed wiring board (1)
As shown in Figure 2, the area covered by the semiconductor IC
It is preferable that the area corresponds to a range that includes all of the many lead pins (6) protruding around the area. Specifically, as shown in FIG. 2(a), it may be an area corresponding to the area A surrounded by a dotted line so as to include the entire lead bin (6) for one semiconductor IC, or One row of lead pins (6) protruding from one side of the semiconductor IC as shown in (b)
The coating may be divided into a plurality of areas corresponding to the range B surrounded by the dotted line so as to include the area B.
異方性導電フィルムはそれ単独で充分な密着性を有して
いるが、半導体搭載用プリント配線基板の接続ランド形
状や、半導体ＩＣのリードビンの形状によって密着面積
が不足する場合は、圧着部分を別の例えば絶縁性熱圧着
フィルム或いは絶縁性接着剤で補強しても一向に差し支
えない。The anisotropic conductive film has sufficient adhesion on its own, but if the adhesion area is insufficient due to the shape of the connection land of the printed wiring board for semiconductor mounting or the shape of the lead bin of the semiconductor IC, the crimped part may be There is no problem in reinforcing it with other materials such as an insulating thermocompression film or an insulating adhesive.
以下、本発明の詳細について実施例を用いて説明する。Hereinafter, details of the present invention will be explained using examples.
通常の回路形成法で作製した半導体搭載用プリント配線
基板（端子部メツキ無し、接続端子／端子間隔−０，２
５ｍｍ１０．２５ｍｍ）を用い、第２図（ｂ）の方法に
より、半導体ＩＣ接続用端子及び端子間樹脂封止された
リード巾／リードピッチ−０，２ｍｍ／ ０．３ ｍｍ
の半導体ＩＣパッケージ（ＳＯＰ）をプリント配線基板
の所定の端子の位置に位置合わせした後、基板と半導体
ＩＣの接合部分を１７０°Ｃで３０秒加熱・加圧し、半
導体搭載回路基板を作製した。半導体を搭載したプリン
ト配線基板の端子部と搭載された半導体・ＩＣのリード
の導通抵抗を測定したところ、０．０７〜０．６７Ω（
ｎ−１６）の範囲であり、端子リード間にショートは見
られなかった。Printed wiring board for mounting semiconductors manufactured using normal circuit forming method (no plating on terminals, connection terminal/terminal spacing -0,2
5mm x 10.25mm), and the semiconductor IC connection terminals and the terminals were resin-sealed using the method shown in Figure 2(b).Lead width/lead pitch -0.2mm/0.3mm
After aligning the semiconductor IC package (SOP) with the predetermined terminal position of the printed wiring board, the joint portion of the board and the semiconductor IC was heated and pressurized at 170°C for 30 seconds to produce a semiconductor-mounted circuit board. When we measured the conduction resistance between the terminals of the printed wiring board on which the semiconductor was mounted and the leads of the mounted semiconductor/IC, we found that it was 0.07 to 0.67Ω (
n-16), and no short circuit was observed between the terminal leads.
実施例と同じ半導体搭載用プリント配線基板を用い、そ
の半導体ＩＣ接続用端子部にメタルマスクを用いて半田
ペーストを印刷し、次に実施例と同じ半導体ＩＣパッケ
ージを全く同様にして位置合わせした後、基板全体を２
２０°Ｃのリフロー炉で４５秒加熱して半田ペーストを
溶融し、半導体ＩＣパッケージをプリント配線基板に形
成された所定の接続用端子部に接続し、半導体ｒｃ＠載
基板基板製した。Using the same semiconductor mounting printed wiring board as in the example, solder paste was printed on the semiconductor IC connection terminal part using a metal mask, and then the same semiconductor IC package as in the example was aligned in exactly the same manner. , the whole board is 2
The solder paste was melted by heating in a reflow oven at 20° C. for 45 seconds, and the semiconductor IC package was connected to a predetermined connection terminal portion formed on a printed wiring board, thereby producing a semiconductor rc@ mounting board.
実施例と同様にしてプリント配線基板の端子部−
と半導体ＩＣのリードの導通抵抗を測定した結果、０．
０５〜０．１１Ω（ｎ＝１３）の範囲であったが、３ケ
所に半田ブリッジによる回路ショートが見られた。As a result of measuring the conduction resistance between the terminal portion of the printed wiring board and the lead of the semiconductor IC in the same manner as in the example, it was found to be 0.
Although the resistance was in the range of 0.05 to 0.11 Ω (n=13), circuit shorts due to solder bridges were observed at three locations.
また、半導体ＩＣパッケージのプリント配線基板への密
着強度については、半田を用いる従来法で３２０ｇ（Ａ
ｖ、ｎ＝１０．１ピン当たり）であるのに対して、本発
明による異方性導電フィルムを用いた場合は２２０ｇ〜
２７０ｇで、必要且つ十分な強度を有していた。In addition, the adhesion strength of the semiconductor IC package to the printed wiring board is 320 g (A
v, n = 10.1 pins), whereas when using the anisotropic conductive film according to the present invention, it is 220 g ~
At 270g, it had the necessary and sufficient strength.
以上の結果から、実施例に見られるように、本発明は従
来の半田の溶融による電気的・機械的接合方法に比べて
、ＩＣと基板とをはるかに低温での接合を可能とするば
かりか、優れた導通抵抗を示すと共に、従来では不可能
であったファインピッチの半導体ｒｃと半導体搭載用プ
リント配線基板の接続を可能ならしめるものであった。From the above results, as seen in the examples, the present invention not only makes it possible to bond an IC and a substrate at a much lower temperature than the conventional electrical/mechanical bonding method by melting solder. In addition to exhibiting excellent conduction resistance, it also made it possible to connect a fine-pitch semiconductor RC and a semiconductor mounting printed wiring board, which was previously impossible.
〔発明の効果］
本発明の半導体ＩＣの接続方法によれば、従来は不可能
であった０、 ５ ｍｍピッチ以下の極ファインピッチ
を存する半導体ＩＣ及び半導体搭載用回路基板の端子部
の接合が可能になり、また、従来は半田を使用するため
に、半田の溶融温度に耐える耐熱性が必要であった半導
体搭載用基板材料に加えて、例えばポリエステルベース
フレキシブル回路基板にも、半導体ＩＣを搭載すること
が可能になるなど、今後径々、高集積化、ファインピッ
チ化の進む半導体ＩＣの接続方法として極めて有用であ
る。[Effects of the Invention] According to the method for connecting semiconductor ICs of the present invention, it is possible to join the terminal portions of semiconductor ICs and semiconductor mounting circuit boards having extremely fine pitches of 0.5 mm or less, which was previously impossible. In addition to semiconductor mounting substrate materials, which previously required heat resistance to withstand the melting temperature of solder due to the use of solder, semiconductor ICs can now be mounted on polyester-based flexible circuit boards, for example. It is extremely useful as a connection method for semiconductor ICs, which will become increasingly highly integrated and fine pitched in the future.
第１図は異方性導電フィルムを用いて半導体ＩＣを接続
する工程を示す図で、第２図は本発明の方法で異方性導
電フィルムを被覆する範囲の一実施例を説明する図であ
る。FIG. 1 is a diagram showing a process of connecting semiconductor ICs using an anisotropic conductive film, and FIG. 2 is a diagram illustrating an example of the range covered by an anisotropic conductive film using the method of the present invention. be.
Claims (1)
路端子部を含み該回路端子部に囲まれた領域全体、又は
半導体ＩＣの周囲に設けられたリードピンの一列分に対
応する半導体接続用回路端子部全体を含む領域に、異方
性導電フィルムを載置し仮止めした後、前記回路端子部
と半導体ＩＣのリードとを位置合わせすると共に、リー
ド／回路端子部を加熱・加圧して接続することを特徴と
する半導体ＩＣの接続方法。(1) Semiconductor connection circuit terminal corresponding to the entire area including the semiconductor connection circuit terminal part of a semiconductor mounting printed wiring board and surrounded by the circuit terminal part, or corresponding to one row of lead pins provided around the semiconductor IC. After placing an anisotropic conductive film on the area including the entire part and temporarily fixing it, align the circuit terminal part and the lead of the semiconductor IC, and connect the lead/circuit terminal part by heating and applying pressure. A method for connecting semiconductor ICs, characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14400689A JPH0311694A (en) | 1989-06-08 | 1989-06-08 | Connection of semiconductor ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14400689A JPH0311694A (en) | 1989-06-08 | 1989-06-08 | Connection of semiconductor ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0311694A true JPH0311694A (en) | 1991-01-18 |
Family
ID=15352121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14400689A Pending JPH0311694A (en) | 1989-06-08 | 1989-06-08 | Connection of semiconductor ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0311694A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386624A (en) * | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60193353A (en) * | 1984-03-15 | 1985-10-01 | Hitachi Chem Co Ltd | Connection of electronic parts |
| JPS62109878A (en) * | 1985-11-07 | 1987-05-21 | Sony Chem Kk | Adhesive sheet having anisotropic electrical conductivity |
-
1989
- 1989-06-08 JP JP14400689A patent/JPH0311694A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60193353A (en) * | 1984-03-15 | 1985-10-01 | Hitachi Chem Co Ltd | Connection of electronic parts |
| JPS62109878A (en) * | 1985-11-07 | 1987-05-21 | Sony Chem Kk | Adhesive sheet having anisotropic electrical conductivity |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386624A (en) * | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
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