JPH01226162A - Connection of semiconductor chip - Google Patents
Connection of semiconductor chipInfo
- Publication number
- JPH01226162A JPH01226162A JP63052848A JP5284888A JPH01226162A JP H01226162 A JPH01226162 A JP H01226162A JP 63052848 A JP63052848 A JP 63052848A JP 5284888 A JP5284888 A JP 5284888A JP H01226162 A JPH01226162 A JP H01226162A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- electrode
- connection
- insulating adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000000853 adhesive Substances 0.000 claims abstract description 26
- 230000001070 adhesive effect Effects 0.000 claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 5
- 238000003825 pressing Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 23
- 230000010076 replication Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 14
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体チップと基板上の接続電極との電気的
接続に関するものであり、特に、フェースダウンボンデ
ィング法に係る電気的接続方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to electrical connection between a semiconductor chip and connection electrodes on a substrate, and in particular to an electrical connection method related to face-down bonding method. .
従来の技術
従来、電子部品の接続端子と基板上の回路パターン端子
との接続には半田付けがよく利用されていたが、近年、
例えばＩＣフラットパッケージ等の小型化と、接続端子
の増加により、接続端子間、いわゆるピッチ間隔が次第
に狭くなり、従来の半田付は技術で対処することが次第
に困難になって来た。Conventional technology In the past, soldering was often used to connect the connection terminals of electronic components and the circuit pattern terminals on the board, but in recent years,
For example, due to the miniaturization of IC flat packages and the increase in the number of connection terminals, the so-called pitch distance between the connection terminals has gradually become narrower, and it has become increasingly difficult to handle conventional soldering techniques.
そこで、最近では裸の半導体チップを基板上の接続電極
に直付けして実装面積の効率的使用を図ろうとする方法
が考案されてきた。なかでも、半導体チップを基板上に
接続するに際し、半導体チツブをフェースダウン（下向
き）にして、あらかじめ端子電極上にメツキ等により形
成したハンダからなる突起電極（バンプ）を高温に加熱
して融着する方法が、接続後の機械的強度が強く、接続
の回数も１回で済むことなどから有益な方法であるとさ
れている。Therefore, recently, a method has been devised in which a bare semiconductor chip is directly attached to connection electrodes on a substrate in order to efficiently use the mounting area. In particular, when connecting a semiconductor chip to a substrate, the semiconductor chip is placed face down (downward) and protruding electrodes (bumps) made of solder that have been formed by plating or the like on the terminal electrodes are heated to high temperatures and fused. This method is said to be advantageous because it has strong mechanical strength after connection and requires only one connection.
以下図面を参照しながら、上述した従来のハンダバンプ
による半導体チップの接続方法の一例について説明する
。An example of the conventional method for connecting semiconductor chips using solder bumps will be described below with reference to the drawings.
第３図は従来のハンダバンプによる半導体チップの接続
方法の概略説明図である。第３図において、７は半導体
チップで、８は端子電極である。FIG. 3 is a schematic explanatory diagram of a conventional method for connecting semiconductor chips using solder bumps. In FIG. 3, 7 is a semiconductor chip and 8 is a terminal electrode.
９はハンダからなる突起電極（バンプ）である。9 is a protruding electrode (bump) made of solder.
ＩＯは接続電極で、１１は基板である。IO is a connection electrode, and 11 is a substrate.
以上のように構成されたハンダバンプによる半導体チッ
プの接続方法について、以下その概略について説明する
。The method for connecting semiconductor chips using the solder bumps configured as described above will be briefly described below.
まず、半導体チップ７の端子電極８にあらかじめハンダ
からなる突起電極（バンプ）９を形成しておき、この半
導体チップ７を下向きにして基板１１の接続電極１０に
位置合せを行う。その後、２００〜３００℃の高温に加
熱してハンダを溶融し、融着させることによって電気的
接続を得るものである。First, protruding electrodes (bumps) 9 made of solder are formed in advance on the terminal electrodes 8 of the semiconductor chip 7, and the semiconductor chip 7 is aligned with the connection electrodes 10 of the substrate 11 with the semiconductor chip 7 facing downward. Thereafter, the solder is heated to a high temperature of 200 to 300° C. to melt and fuse the solder, thereby obtaining an electrical connection.
このような突起電極（バンプ）９は、まず半導体チップ
７の端子電極８に、Ｃｒ ％ Ｃｕ 、Ａ ｕ等の金属
薄膜を形成した後、メツキによりハンダを積層して形成
するものである。Such protruding electrodes (bumps) 9 are formed by first forming a metal thin film of Cr%Cu, Au, etc. on the terminal electrodes 8 of the semiconductor chip 7, and then layering solder by plating.
発明が解決しようとする課題
しかしながら上記のような方法では、
＋１） ハンダを溶融する際に高温に加熱する必要が
あり、熱応力の影響を受は易い。Problems to be Solved by the Invention However, the above method has the following problems: +1) It is necessary to heat the solder to a high temperature when melting it, and it is easily affected by thermal stress.
（２）ハンダによる接続のために基板側の接続電極がハ
ンダ接続可能なものである必要があり、汎用性に欠ける
。(2) Since the connection is made by soldering, the connection electrode on the board side needs to be connectable by solder, which lacks versatility.
（３）突起電極（バンプ）を形成するハンダが加熱溶融
する際に流れ、ショートが発生する危険がある。(3) There is a risk that the solder forming the protruding electrodes (bumps) will flow when heated and melted, causing a short circuit.
（４） 基板への固定が突起電極（バンプ）部のみで
なされているため接着強度が弱（、接続の安定性に欠け
る。(4) Since the bonding to the substrate is done only by the protruding electrode (bump) portion, the adhesive strength is weak (and the connection is not stable).
などといった課題を有していた。There were issues such as these.
本発明は上記の課題に鑑みてなされたものであり、その
目的とする所は、半導体チップと実装基板とを容易に、
かつ、信頼性良く電気的接続を行う接続方法を提供する
ことである。The present invention has been made in view of the above problems, and its purpose is to easily connect a semiconductor chip and a mounting board.
Further, it is an object of the present invention to provide a connection method that performs electrical connection with high reliability.
課題を解決するための手段
本発明は上記の課題を解決するため、微細端子電極が形
成された半導体チップの配線パターンを具えた基板への
電気的接続において、該半導体チ・７プ上の端子電極部
を除く所定の位置、または、該基板上の接続電極部を除
く所定の位置に熱硬化性の絶縁性接着剤を塗布、または
、転写によって形成する工程と、該基板上の所定の位置
に前記半導体チップを載置する工程と、該基板と該半導
体チップとを加圧しながら加熱し、前記絶縁性接着剤を
硬化せしめ、該基板の接続電極への該半導体チ・ノブの
電気的接続を得る工程とからなることを特徴として半導
体チップの電気的な接続を実現しようとするものである
。Means for Solving the Problems In order to solve the above problems, the present invention provides a method for electrically connecting a semiconductor chip on which fine terminal electrodes are formed to a substrate having a wiring pattern. A step of applying or transferring a thermosetting insulating adhesive to a predetermined position other than the electrode part or a predetermined position other than the connection electrode part on the substrate, and a predetermined position on the substrate. placing the semiconductor chip on the substrate, heating the substrate and the semiconductor chip while applying pressure to harden the insulating adhesive, and electrically connecting the semiconductor chip/knob to the connection electrode of the substrate. This method aims to realize electrical connection of semiconductor chips.
作用
本発明は上記した方法によって、半導体チップ上の端子
電極にあらかじめ形成した突起電極（ハンプ）を基板の
接続電極に絶縁性接着剤の加熱硬化により圧着した状態
で保持することにより、電気的接続を行い、かつ、この
絶縁性接着剤によって半導体チップを固定するため、容
易で信頼性の高い半導体チップの電気的な接続が可能と
なる。Function The present invention uses the method described above to establish an electrical connection by holding a protruding electrode (hump) formed in advance on a terminal electrode on a semiconductor chip in a state in which it is pressed to a connecting electrode of a substrate by heating and curing an insulating adhesive. In addition, since the semiconductor chip is fixed with this insulating adhesive, easy and reliable electrical connection of the semiconductor chip is possible.
実施例
以下、本発明の一実施例の半導体チップの接続方法につ
いて、図面を参照しながら説明する。EXAMPLE Hereinafter, a method for connecting semiconductor chips according to an example of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例における半導体チップの
接続方法の概略説明図である。第１図において、ｌは半
導体チップ、２は端子電極、３は突起電極（バンプ）で
ある。４は熱硬化性の絶縁性接着剤である。５は接続電
極であり、６は基板である。FIG. 1 is a schematic explanatory diagram of a method for connecting semiconductor chips in a first embodiment of the present invention. In FIG. 1, 1 is a semiconductor chip, 2 is a terminal electrode, and 3 is a protruding electrode (bump). 4 is a thermosetting insulating adhesive. 5 is a connection electrode, and 6 is a substrate.
以上のように構成された半導体チップの接続方法につい
て、以下図面を用いてその動作を説明する。The operation of the method for connecting semiconductor chips configured as described above will be described below with reference to the drawings.
まず、半導体チップ１の端子電極２にあらかじめ突起電
極（バンプ）３を形成しておき、この半導体チップ１の
端子電極２部を除く所定の位置にデイスペンサーによる
塗布やスタンピングによる転写などによって、熱硬化性
の絶縁性接着剤４を形成する。First, protruding electrodes (bumps) 3 are formed in advance on the terminal electrodes 2 of the semiconductor chip 1, and heat is applied to predetermined positions of the semiconductor chip 1 except for the terminal electrodes 2 by coating with a dispenser or transfer by stamping. A curable insulating adhesive 4 is formed.
そして、第１図（ａ）に示す様に、この半導体チップ１
を下向きにして基板６の接続電極５に位置合せを行い、
基板６上に半導体チップｌを載置した後、加圧しながら
加熱し絶縁性接着剤４を硬化させることによって、第１
図（ｂ）に示す様に、突起電極（ハンプ）３と接続電極
５が圧着した状態で保持される。Then, as shown in FIG. 1(a), this semiconductor chip 1
Align it with the connection electrode 5 of the substrate 6 with it facing downward,
After placing the semiconductor chip l on the substrate 6, the first
As shown in Figure (b), the protruding electrode (hump) 3 and the connecting electrode 5 are held in a crimped state.
このとき、絶縁性接着剤４は硬化反応が進むにつれて熱
収縮するため、半導体子ツブ１の突起電極（バンプ）３
と基板６の接続電極５の間での密着性が増し接続の安定
性が向上できる。At this time, since the insulating adhesive 4 heat-shrinks as the curing reaction progresses, the protruding electrode (bump) 3 of the semiconductor tube 1
The adhesion between the connecting electrode 5 of the substrate 6 and the connecting electrode 5 of the substrate 6 is increased, and the stability of the connection can be improved.
また、絶縁性接着剤４の加熱硬化は、ハンダによる接続
に比べて低温で行うため、熱応力による影響を軽減する
ことができ、かつ、絶縁性接着剤４によって半導体チッ
プ１の固定を行っているため、極めて安定な接続が得ら
れる。In addition, since heating and curing of the insulating adhesive 4 is performed at a lower temperature than that of soldering, the influence of thermal stress can be reduced, and the semiconductor chip 1 can be fixed by the insulating adhesive 4. This provides an extremely stable connection.
さらに、突起電極（バンプ）３と接続電極５の電気的接
続は圧着による接触状態で行うため、突起電極（バンプ
）３の構成材料はハンダである必要はなく導電体であれ
ばいかなるものでもよく、かつ、基板６の接続電極５の
材質を配線材料であればいかなるものでもよい。Furthermore, since the electrical connection between the protruding electrode (bump) 3 and the connection electrode 5 is made by contacting by crimping, the constituent material of the protruding electrode (bump) 3 does not have to be solder, but may be any conductive material. , and the material of the connection electrode 5 of the substrate 6 may be any wiring material.
以上のようにして、半導体チップｌと基板６を極めて安
定に、かつ、汎用性のある方法で接続が可能となる。In the manner described above, it is possible to connect the semiconductor chip 1 and the substrate 6 in an extremely stable and versatile manner.
第２図は本発明の第２の実施例における半導体チップの
接続方法の概略説明図である。FIG. 2 is a schematic explanatory diagram of a method for connecting semiconductor chips in a second embodiment of the present invention.
第１の実施例と異なるのは、第２図（ａｌに示したよう
に絶縁性接着剤４を基板６の接続電極５部を除く所定の
位置にデイスペンサーによる塗布やスタンピングによる
転写などによって形成した点である。The difference from the first embodiment is that, as shown in FIG. This is the point.
これにより、半導体チップｌ上に絶縁性接着剤４の形成
が困難な場合にも本発明による接続方法が適用できる。Thereby, the connection method according to the present invention can be applied even when it is difficult to form the insulating adhesive 4 on the semiconductor chip l.
なお、実施例において突起電極（バンプ）３を半導体チ
ップｌの端子電極２に形成するとしたが、基板６の接続
電極５に形成してもよい。In the embodiment, the protruding electrodes (bumps) 3 are formed on the terminal electrodes 2 of the semiconductor chip l, but they may be formed on the connection electrodes 5 of the substrate 6.
また、突起電極（バンプ）３の形成は、従来例のハンダ
バンプのようにメツキによる形成に限られたものでなく
、いかなる方法による形成を行ってもよい。Further, the formation of the protruding electrodes (bumps) 3 is not limited to formation by plating like the conventional solder bumps, but may be formed by any method.
さらに、絶縁性接着剤４の材質は、エポキシ系樹脂、シ
リコーン系樹脂、ポリイミド系樹脂、フェノール系樹脂
等、熱収縮性があって、かつ、熱硬化性の絶縁性接着剤
であればいかなるものでもよい。Furthermore, the material of the insulating adhesive 4 may be any heat-shrinkable and thermosetting insulating adhesive such as epoxy resin, silicone resin, polyimide resin, phenol resin, etc. But that's fine.
この絶縁性接着剤４において、加熱硬化時の熱収縮が大
きく、かつ、接着力の強いものを用いた場合には、基板
６上に半導体チップ１を載置した後に加熱して絶縁性接
着剤４を硬化させることによって、加圧を必要とするこ
となしに、突起電極（バンプ）３と接続電極５が、絶縁
性接着剤４の熱収縮のみで圧着した状態で保持すること
もできる。If the insulating adhesive 4 has a large thermal shrinkage during heating and hardening and has a strong adhesive force, the insulating adhesive 4 may be heated after placing the semiconductor chip 1 on the substrate 6. By curing the insulating adhesive 4, the protruding electrode (bump) 3 and the connecting electrode 5 can be held in a pressed state only by thermal contraction of the insulating adhesive 4, without requiring pressure.
発明の効果
以上に説明したように、本発明の半導体チップの接続方
法によれば、絶縁性接着剤によって半導体チップと基板
間の電気的接続部以外の部分を接着することにより、半
導体チップの突起電極（バンプ）と基板の接続電極を圧
着状態で電気的接続を行うことができ、接続温度が低く
、容易で信顛性の高い電気的接続が可能となり、極めて
実用価値が高い。Effects of the Invention As explained above, according to the semiconductor chip connecting method of the present invention, by bonding the parts other than the electrical connection between the semiconductor chip and the substrate with an insulating adhesive, the protrusions of the semiconductor chip can be fixed. Electrical connections can be made with the electrodes (bumps) and connection electrodes of the substrate bonded together, the connection temperature is low, easy and highly reliable electrical connections can be made, and this has extremely high practical value.
第１図は本発明の第１の実施例における半導体チップの
接続方法を示す概略説明図、第２図は本発明の第２の実
施例における半導体チップの接続方法を示す概略説明図
、第３図は従来の半導体チップの接続方法を示す概略説
明図である。
１．７・・・・・・半導体チップ、２．８・・・・・・
端子電極、３．９・・・・・・突起電極（バンプ）、４
・・・・・・絶縁性接着剤、５，１０・・・・・・接続
電極、６，１１・・・・・・基板。
代理人の氏名 弁理士 中尾敏男 はか１名第１図
第２図
／−一一手導イ本ｆ−２１
４−−４ぎ縁姓掃看荊
６−−−場淡１１壓
６−−−基級1 is a schematic explanatory diagram showing a method of connecting semiconductor chips in a first embodiment of the present invention, FIG. 2 is a schematic explanatory diagram showing a method of connecting semiconductor chips in a second embodiment of the present invention, and FIG. The figure is a schematic explanatory diagram showing a conventional method for connecting semiconductor chips. 1.7... Semiconductor chip, 2.8...
Terminal electrode, 3.9...Protruding electrode (bump), 4
...Insulating adhesive, 5, 10... Connection electrode, 6, 11... Substrate. Name of agent: Patent attorney Toshio Nakao 1 person Figure 1 Figure 2/-11 Hand Guide book f-21 4--4 relationship name cleaning view 6---Batan 11 壓6-- −Basic level
Claims (3)
ターンを具えた基板への電気的接続において、前記半導
体チップ上の端子電極部を除く所定の位置、または、前
記基板上の接続電極部を除く所定の位置に熱硬化性の絶
縁性接着剤を塗布、または、転写によって形成する工程
と、前記基板上の所定の位置に前記半導体チップを載置
する工程と、前記基板と前記半導体チップとを加圧しな
がら加熱し、前記絶縁性接着剤を硬化せしめ、前記基板
の接続電極への前記半導体チップの電気的接続を得る工
程とからなることを特徴とする半導体チップの接続方法
。(1) When electrically connecting a semiconductor chip on which fine terminal electrodes are formed to a substrate with a wiring pattern, connect the semiconductor chip to a predetermined position other than the terminal electrode portion on the semiconductor chip, or connect the connecting electrode portion on the substrate. a step of applying or transferring a thermosetting insulating adhesive to a predetermined position other than the substrate; a step of mounting the semiconductor chip at a predetermined position on the substrate; and a step of attaching the semiconductor chip to the substrate. A method for connecting a semiconductor chip, comprising the step of heating while applying pressure to harden the insulating adhesive to electrically connect the semiconductor chip to a connection electrode of the substrate.
てなるものであることを特徴とする請求項第（１）項記
載の半導体チップの接続方法。(2) The method for connecting a semiconductor chip according to claim (1), wherein the semiconductor chip is formed by forming protruding electrodes on terminal electrodes.
のであることを特徴とする請求項第（１）項記載の半導
体チップの接続方法。(3) The method for connecting semiconductor chips according to claim (1), wherein the substrate is formed by forming protruding electrodes on connection electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63052848A JPH01226162A (en) | 1988-03-07 | 1988-03-07 | Connection of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63052848A JPH01226162A (en) | 1988-03-07 | 1988-03-07 | Connection of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01226162A true JPH01226162A (en) | 1989-09-08 |
Family
ID=12926266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63052848A Pending JPH01226162A (en) | 1988-03-07 | 1988-03-07 | Connection of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01226162A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997004481A1 (en) * | 1995-07-20 | 1997-02-06 | Matsushita Electric Industrial Co., Ltd. | Carrier, semiconductor device, and method of their mounting |
| US6482676B2 (en) | 1997-01-09 | 2002-11-19 | Fujitsu Limited | Method of mounting semiconductor chip part on substrate |
| JP2005210470A (en) * | 2004-01-23 | 2005-08-04 | Soshin Electric Co Ltd | Passive components |
| JP2016197723A (en) * | 2015-04-02 | 2016-11-24 | ヘレウス ドイチェラント ゲーエムベーハー ウント カンパニー カーゲー | Method for manufacturing board structure, board structure, method for bonding electronic component to board structure, and electronic component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58121634A (en) * | 1982-01-12 | 1983-07-20 | Seiko Epson Corp | Moldless mounting method |
-
1988
- 1988-03-07 JP JP63052848A patent/JPH01226162A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58121634A (en) * | 1982-01-12 | 1983-07-20 | Seiko Epson Corp | Moldless mounting method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997004481A1 (en) * | 1995-07-20 | 1997-02-06 | Matsushita Electric Industrial Co., Ltd. | Carrier, semiconductor device, and method of their mounting |
| US6037657A (en) * | 1995-07-20 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Carrier, semiconductor device, and method of their mounting |
| US6482676B2 (en) | 1997-01-09 | 2002-11-19 | Fujitsu Limited | Method of mounting semiconductor chip part on substrate |
| JP2005210470A (en) * | 2004-01-23 | 2005-08-04 | Soshin Electric Co Ltd | Passive components |
| JP2016197723A (en) * | 2015-04-02 | 2016-11-24 | ヘレウス ドイチェラント ゲーエムベーハー ウント カンパニー カーゲー | Method for manufacturing board structure, board structure, method for bonding electronic component to board structure, and electronic component |
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