JPH03102640A - Automatic gain controller for optical memory device - Google Patents

Abstract

PURPOSE:To reduce the reproduction error just after the end of recording or erasure by providing a 1st control means holding a control voltage at recording or erasure. CONSTITUTION:When a pre-format hold timing signal is brought into a high level in the case of holding an AGC voltage in a pre-format AGC amplifier 65, an output signal of an inverter 91 is inverted from a high level to a low level. Since an output signal of an AND circuit 90 is kept at a low level or inverted attended therewith, a transistor (TR) 81 remains in the off-state or is switched. Since a control voltage is held at recording or erasure in this way, the amplification factor of an automatic gain controller at recording or erasure is kept to be a value before the recording or erasure. Thus, a reproduction error just after the end of recording or erasure is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic gain control device that is installed in an optical memory device that performs recording, erasing, or reproduction in an optical memory, and that adjusts the gain according to the amplitude of a reproduced signal. It is.

[Conventional technology]

Conventional optical memory devices will be described below, taking as an example a magneto-optical memory device that performs recording, erasing, and reproduction on a magneto-optical disk.

As shown in FIG. 33(a), the magneto-optical disk is formed by coating a recording magnetic film 2805 on a disk substrate 2804. The recording magnetic film 2805 is formed so that the axis of easy magnetization is perpendicular to the film surface, and the direction of magnetization indicated by the arrow in the recording magnetic film 2805 is in a predetermined direction (for example, in the figure). It is initialized so that the direction of magnetization is A).

During recording, a laser beam 2803 emitted from a semiconductor laser 2801 is focused by an objective lens 2802 to a diameter of approximately lam, and is irradiated onto a recording magnetic film 2805.

At that time, a recording signal 2807 corresponding to the information to be recorded
The strength of the light intensity of the laser beam 2803 is controlled based on the following (see FIG. 2(b)). The temperature of the region irradiated with the high-intensity laser beam 2803 locally increases to exceed the Curie temperature, and the coercive force of that region decreases significantly. As a result, the direction of magnetization in the region where the coercive force has decreased is reversed to the same direction as the externally applied magnetic field 2806 applied simultaneously with the irradiation of the laser beam 2803 (direction of magnetization B in the figure). In this way, information corresponding to the recording signal 2807 is recorded on the recording magnetic film 2805. Below, mark 2 is the part where the magnetization in direction B is recorded as described above.
809, a region where magnetization in direction A is recorded is called a non-mark 28lO. Erasing information recorded on the recording magnetic film 2805 is performed in the same manner as during recording by reversing the direction of the externally applied magnetic field 2806 from that during recording, and changing the direction of magnetization to the original initializing direction (i.e., This is carried out by returning the magnetization direction A). As a result, the erased portion is a non-mark 281
It becomes o.

In this example, the laser beam 28o3 is used as the recording signal 280.
Externally applied magnetic field 2806 of constant strength modulated according to 7
In addition to this, there is also a magnetic field modulation method in which the intensity of the laser beam 28o3 is kept constant and the direction of the externally applied magnetic field 28o6 is modulated according to the recording signal 2807. You may record it.

The disk substrate 2804 is made of glass or plastic, and as shown in FIG. 33(a), address information indicating the addresses of tracks and sectors is carved in advance as physical irregularities 2808. There is.

Since the above address information is inscribed in advance in a certain format, recording and erasing operations cannot be performed thereafter. The portion carved in advance as physical unevenness 2808 will be referred to as a preformat portion 3003 hereinafter. On the other hand, each operation of recording and erasing information is performed in a part other than the preformat part 3003, and this part is referred to as an MO (magneto-optical) part 3002. Usually, the preformat section 3003 and the MO section 3002 are arranged alternately on spiral or concentric tracks 3005, as shown in FIG. The preformat section 3003 and the MO section 3002 form one sector 30 as a pair.
It consists of 04.

The magneto-optical disk 3001 has a large number of sectors 3 on a track 3005, each of which is assigned address information.
004, and each operation of recording, reproducing, and erasing information is performed in units of 3004 sectors.

Further, as shown in FIG. 36, in the preformat section 3003 on the track 3005, either the concave portion or the convex portion of the unevenness 2808 in FIG. 33 is marked 28l1.
and the other of the concave part or the convex part is a non-mark 2
812.

Furthermore, as mentioned above, the MO section 3002 has an MO (magneto-optical)
Signal mark 2809 and non-mark 2910 in between
will be recorded.

Next, during reproduction of the magneto-optical disk 3001, as shown in FIG. 2805 is irradiated. However, the laser beam 2803 is linearly polarized light, and the light intensity of the laser beam 2803 is made weaker than during each recording/erasing operation. When the reflected light of the linearly polarized laser beam 2803 from the magneto-optical disk 3001 passes through or is reflected by the recording magnetic film 2805, its plane of polarization is rotated by the Faraday effect or the Kerr effect. This direction of rotation is between mark 2809 and non-mark 281.
0, they rotate in opposite directions. Reproduction is performed by detecting this difference in polarization direction. As a result, for example, two types of reproduced signals S as shown in FIG.
1.S2 is generated.

Next, to briefly explain the reproduction optical system for obtaining the reproduction signals S1 and S2, as shown in FIG. 37, the reflected light 320l from the magneto-optical disk 3001 is
(Analyzer) 3202 and two detected light beams 3210
・3211 has two photodetectors 3 for each polarization direction
Guided by 203/3204. And photodetector 320
3 and 3204, the signals are converted into electrical signals that vary depending on the light intensity, and output as reproduced signals S1 and S2. As will be detailed later, the above reproduced signals S1 and S2
By adding and operating , the preformat section 3
003 and the signal from the MO section 3002 can be separated into 77B, and furthermore, the signal from the MO section 3002 can be converted to mark 2.
Since the mark 809 and the non-mark 2810 can be read out separately, the information recorded on the recording magnetic film 2805 can be reproduced.

As shown in FIG. 38(a), let the reflected light vector from the non-mark 2810 (magnetization direction A) in the MO section 3002 be α, and the reflected light vector from the mark 2809 (m-oriented direction B) be β. , α and β are reflected light vectors rotated in opposite directions by the rotation angle of the polarization plane. The reflected light vectors α and β are detected in two polarization directions X and Y by an analyzer (PBS) 3202, respectively. This 2
The two polarization directions X and Y are perpendicular to each other.

The magnitudes of the detected light vectors α8 and β7, which are obtained by projecting the reflected light vectors α and β in the polarization directions X and Y, respectively, are the reproduced signal Sl.
and the reproduction signal S2.

Furthermore, the detection light vectors α8 and β correspond to the detection lights 3210 and 321l in FIG. 37, respectively.

As is clear from FIG. 38(a), the reproduced signal S1 corresponds to a high level for the non-mark 28lO, and a low level for the mark 2809. On the other hand, the reproduced signal S
2 is low level for non-mark 2810, mark 28
The high level corresponds to 09, and the reproduced signal S
The polarity is opposite to that of 1. Then, the reproduced signal S1・S
2 is input to a differential amplifier to improve the S/N ratio, and is differentially amplified to reproduce information.

Next, based on FIG. 38(b), the preformat section 3
The reproduced signals S1 and S2 reproduced from 003 will be described. Since the preformat section 3003 does not perform any recording or erasing operations, the direction of magnetization is only A. In the preformat section 3003, diffraction of the laser beam occurs due to the shapes of the marks 2811 and non-marks 2812 made up of the unevenness 2808. Therefore, as shown in FIG. 38(b), the reflected light vector α is longer depending on the unevenness 2808 (corresponding to the reproduction of the non-mark 2812).
, and a short reflected light vector T (corresponding to reproduction of mark 2811).

By projecting this onto the polarization directions X and Y of the analyzer (PBS) 3202, analyzer vectors αx and Tv are obtained, respectively. The magnitude of the analyzer vectors α8 and γ1 is the reproduced signal S1.
Compatible with S2. Both reproduced signals S1 and S2 are
The non-mark 28l2 due to the unevenness 2808 corresponds to a high level, and the mark 2811 corresponds to a low level. Therefore, this reproduced signal SL-52 has the mark 2809 and the non-mark 2810 of the magneto-optical recording shown in FIG. 38(a).
Unlike the case of , the polarity is the same. That is, the third
As shown in FIGS. 4(b) and 4(c), the reproduced signals S1 and S2 have the same polarity in the preformat section 3003, and become signals with inverted polarities in the MO section 3002.

Therefore, by adding the reproduced signals S1 and S2, only the signal of the preformat section 3003 is obtained, and the reproduced signal Sl-
32 makes it possible to obtain only the signal of the MO section 3002, and in this way, it is possible to improve the S/N ratio.

The differential signal or addition signal from the above two types of reproduction signals St-S2 is an auto gain control amplifier (hereinafter referred to as A
It is conceivable to perform amplification while adjusting the degree of amplification so that the amplitude after amplification is approximately constant using a GC amplifier (referred to as a GC amplifier). The above AGC amplifier includes, for example, a voltage control amplifier and a control voltage (hereinafter referred to as AGC voltage) for adjusting the amplification degree of the voltage control amplifier so that the amplitude of the output signal of the voltage control amplifier is approximately at a predetermined level. ).).

[Problem to be solved by the invention]

However, in the above-mentioned magneto-optical memory device,
Immediately after a recording or erasing operation, the amplification degree of the AGC amplifier may become excessively small and playback may not be performed properly. That is, in FIG. 46, in the sector 3004 indicated by A in FIG. In step 3004, the preformat section 3003 is reproduced and the information recorded in the MO section 3002 is erased.

In that case, in the sector 3004 of A, the semiconductor laser 28
01 (Fig. 33) rises to a high level corresponding to the above-mentioned recording light quantity, the reproduction signals S1 and 32 (here, recorded) in the MO section 3oo2 rise as shown in Fig. 46(b) The amplitude of the laser beam 2803 (FIG. 27) (a signal based on the reflected light from the magneto-optical disk 3001) becomes extremely large. As a result, the same figure (
As shown in d), the AGC voltage begins to rise, and the amplification degree of the voltage-controlled amplifier begins to decrease accordingly, so that the output signal level of the voltage-controlled amplifier gradually decreases, as shown in part (c) of the same figure.

However, after that, sector 3004 indicated by B and then C
When reproducing the preformat section 3002 of the sector 3004 of B-C, the amplification degree of the voltage-controlled amplifier remains low, so the signal is amplified by the voltage-controlled amplifier as shown by B or CI. The amplitude of the reproduction signal of the subsequent preformat section 3002 becomes extremely small, and there is a possibility that a reproduction error may occur.

Similarly, when erasing is performed in the sector 3004 indicated by C, the amount of light from the semiconductor laser 2801 becomes larger than during reproduction, so that the reproduced signals S1 and 32 (
Here, the amplitude of the signal (based on the reflected light from the erasing laser beam 2803 reflected by the magneto-optical disk 3001) increases, and as a result, the amplification degree of the voltage control amplifier decreases. During playback from the preformat section 3002 (see section D), the output signal level of the voltage control amplifier also drops, making it impossible to perform accurate playback. Furthermore, in the magneto-optical memory device, at the time of access, the laser beam 280 is emitted as shown in FIG.
3 is a track 3005 provided in the form of a guide groove provided on the disk substrate 2804 or a preformat portion 3
It moves in the radial direction of the disk substrate 2804 as indicated by the arrow P or Q while crossing the unevenness 2808 at 003. In that case, the track 3005 or the unevenness 280
Since the amount of reflected light differs between the portion 8 and the other portions, a reproduced signal S1 or S2 as shown in portion A in FIG. 48 is obtained. On the other hand, when reproducing information, the reproduction signal Sl or S
2 is shown in section B in the figure.

In this way, during access, the amplitude of the reproduced signal S1 or S2 becomes larger or smaller than when reproducing information. This varies depending on the depth and width of the guide groove. Therefore, the amplification degree of the AGC amplifier decreases or increases accordingly. As a result, a reproduction error may occur even when reproducing information immediately after access. Note that when the access speed is relatively low, by providing a high-pass filter in the processing system of the reproduced signal S1 or S2, the track 3005 or unevenness 2808 as shown in part A of FIG.
Since it is possible to remove the vibrational disturbance caused by the access, playback errors are less likely to occur immediately after access, but since it is usually preferable to speed up the access as much as possible, it is possible to reduce or increase the amplification of the AGC amplifier immediately after access. Reproduction errors caused by this are difficult to avoid.

The above-described reproduction errors immediately after recording/erasing or access can be reduced by increasing the response speed of the 80C amplifier to changes in the amplitude of the input signal. In addition, when performing the test write as described above, the AG
Since it is necessary to follow the C voltage ((d) in the figure), it is necessary to increase the response speed of the AGC amplifier as much as possible in order to carry out the test write meaningfully.

However, if the response speed of the AGC amplifier is increased, for example, when a defective pulse occurs due to a damaged part or dust on the magneto-optical disk 3001, the
Since the GC amplifier immediately responds to the defective pulse and the amplification degree decreases, reproduction errors are likely to occur. Note that the response speed of the AGC amplifier is originally set to be low in order to reduce reproduction errors caused by the above-mentioned defective pulses.

As described above, whether the response speed of the AGC amplifier is set low or high, reproduction errors are likely to occur for different reasons. Basically, it is preferable to set the response speed of the AGC amplifier to be low in order to reduce the influence of the defective pulse, but in this case, reproduction errors due to delayed response of the AGC amplifier are unavoidable.

[Means to solve the problem]

In order to solve the above-mentioned problems, an automatic gain control device for an optical memory device according to a first aspect of the present invention is provided in an optical memory device that performs recording, erasing, or reproduction in an optical memory, and is provided with an automatic gain control device for an optical memory device that performs recording, erasing, or reproduction in an optical memory. An automatic gain control device for an optical memory device that adjusts the degree of amplification based on a generated control voltage, characterized by comprising a first control means for holding the control voltage during recording or erasing. be.

This auto gain control device further includes a recorded area determining means for determining an area where information has been recorded during reproduction, and holding the control voltage in eight areas where information is not recorded based on the determination of the recorded area determining means. It is preferable to include a second control means.

Further, it is preferable that the above automatic gain control device further includes response speed changing means for changing the response speed in multiple stages.

Further, the automatic gain control device for an optical memory device according to the second aspect of the present invention is capable of recording, erasing, or reproducing information in an optical memory that has a preformat section in which addresses and the like are recorded in advance and a data section in which arbitrary data can be recorded. In an automatic gain control device for an optical memory device, which is provided in an optical memory device that performs A first auto gain control section that adjusts the gain, and a second auto gain control section that adjusts the gain of the reproduction signal reproduced from the data section, and only the second auto gain control section. A recorded area determining means for determining an area where information has been recorded during reproduction, and a holding means for holding the control voltage in an area where information is not recorded based on the determination by the recorded area determining means are provided. It is a feature.

[For production]

The auto gain control device for the optical memory device according to the first aspect of the present invention holds the control voltage during recording or erasing, so that the amplification degree of the auto gain control device changes when recording or erasing starts. The previous value will be retained. Therefore, the degree of amplification at the start of playback immediately after the end of recording or erasing is the same as the degree of amplification at the end of the previous playback, so the playback signal is amplified at an approximately appropriate amplification degree even during playback immediately after the end of recording or erasing. You will be able to do this. This makes it possible to reduce reproduction errors immediately after recording or erasing ends.

By the way, in an area where information is not recorded in the optical memory, the amplitude of the reproduced signal is at a low level, so the amplification degree of the automatic gain control device increases to near the maximum value. In that case, when passing through the unrecorded area and approaching the recorded area, the amplification remains at an excessive level, so
This makes normal reproduction difficult.

Therefore, in the first aspect of the present invention, if it is determined at the time of reproduction whether the information has been recorded or not, and if the control voltage is held in the unrecorded area, the control voltage may be held in the unrecorded area. Since the amplification degree is maintained at the amplification degree at the time of the previous reproduction of the recorded area, the next time the reproduced signal is amplified at almost the appropriate amplification degree immediately after reaching the recorded area. You will be able to do this.

Furthermore, in the first aspect of the present invention, if a response speed changing means for changing the response speed in multiple stages is provided, for example,
By increasing the response speed of the auto gain control device when detecting the control voltage of the auto gain control device (equivalent to the AGC voltage mentioned above), such as during the above test light, and holding the control voltage during that time. By not doing so, it becomes possible to respond to changes in the amplitude of the reproduced signal at minute intervals such as sectors, but
When reproducing normal information, by setting the response speed relatively low, it is possible to reduce the influence of defective pulses and the like, thereby reducing reproduction errors.

Further, as described above, the optical memory may be divided into a preformer/format part and a data part, and while addresses and the like are recorded in advance in the preformat part, arbitrary data may be recorded in the data part. By the way, when determining the recorded area and the unrecorded area of information as described above and holding the control voltage of the auto gain control device in the unrecorded area, the data section usually includes the recorded area and the unrecorded area. However, information such as addresses is always recorded in the preformat section.

Therefore, in the preformat section, it is usually not necessary to determine whether a recorded area is an unrecorded area or to hold the auto gain control device. Therefore, as in the second aspect described above, the first auto gain control section adjusts the amplification degree of the reproduced signal reproduced from the brifoma note section and the amplification degree of the reproduced signal reproduced from the data section. and a second auto gain control section to
a recorded area determining means for determining a recorded area of the second information only in the second (7), t-} gain control section during reproduction;
If a hold means is provided to hold the control voltage in the unrecorded area based on the judgment of the recorded area judgment means, the first auto gain control section for the preformat section will be able to determine the recorded area. Since the means and the holding means are not required, the structure of the first auto gain control section for the preformat section can be simplified.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 to 32.

First, a magneto-optical disk 1201 as an example of optical memory
This article describes the precautions of a magneto-optical disk device for recording, reproducing, and erasing data.

As shown in FIG. 9, a magneto-optical disk 1201 is rotationally driven by a spindle motor 1202, and an optical head l
Information is recorded, reproduced, and erased by a laser beam 1204 emitted from a laser beam 203. During recording or erasing, an external magnetic field is applied from an external magnetic field applying magnet 1205 at the same time as the laser beam 1204 is irradiated. Note that the direction of the external magnetic field during recording and erasing can be reversed, for example, by rotating the external magnetic field applying magnet 1205 with a motor or the like (not shown). Alternatively, the external magnetic field applying magnet 1205 may be an electromagnet to obtain an external magnetic field for recording and erasing.

During recording, the semiconductor laser 280 in the optical head 1203
1 (see FIG. 10), a semiconductor laser drive current 1210 is manually applied from the recording circuit 1206. The light intensity of the semiconductor laser 2801 is appropriately controlled by the semiconductor laser drive current 12IO. Also, during playback, the optical head l20
3, a reproduction signal 1211 (third
4) consisting of two types of reproduced signals S1 and S2 as shown in FIG. 4 is output. Reproduction data 1212 reproduced by reproduction circuit l207 is sent to controller 1208.

In the controller l208, the timing of various control signals 1213 is determined based on the reproduction data 1212, and these control signals 12l3 are sent to the recording circuit 1206 and the reproduction circuit 1207. Further, a magnetic field control signal l214 is transmitted from the controller 1208 to the external magnetic field applying magnet 1205, and the direction of the external magnetic field is controlled. As shown in FIG. 10, the recording circuit 1206 includes a modulation circuit 1302, and a controller 1208 (FIG. 9).
The recording data 131l sent from is input to the modulation circuit 1302. In the modulation circuit 1302,
Recorded data 1311 is converted into modulated data 1310 according to the recording format by a control signal 1213. This modulation is performed, for example, according to the 2.7 modulation method described later. Modulation data l310 is transmitted to semiconductor laser drive circuit 1301.
Based on this, the semiconductor laser drive circuit 13
The semiconductor laser drive current l210 is output from 01 and transmitted to the semiconductor laser 2801 in the optical head 1203. At the same time, a control signal 1213 from the controller 1208 is input to the semiconductor laser drive circuit 130l, and the light intensity of the semiconductor laser 2801 is appropriately controlled according to each recording, reproduction, and erasing operation.

Further, as shown in FIG. 11, the reproduction circuit 1207 includes a signal processing circuit 1401, and the reproduction signal 1211 (reproduction signals S1 and S2) from the optical head 1203 (FIG. 9) is input to the signal processing circuit 1401. , where synchronization is achieved. From the signal processing circuit 1401, synchronization data 1410 is sent to the demodulation circuit 1402, and at the same time, the sector mark signal 1 is sent to the demodulation circuit 1402.
411 is transmitted to controller 1208. Demodulation of synchronized data 1410 is achieved by performing the opposite conversion to that of modulation circuit 1302 in FIG.

Various control signals 1213 are transmitted from the controller 1208 to the signal processing circuit 1401 and the demodulation circuit 1402. Demodulated playback data 1212 is output from the demodulation circuit 1402.
is output to controller 1208.

As shown in FIG. 12, the controller 1208 includes a timing generation circuit 1501. Sector mark signal 141 from signal processing circuit 1401 (Fig. 11)
1 is manually inputted to a timing generation circuit 150l, where a reference timing signal 1510 is generated at the timing of each sector and transmitted to the control circuit 1502. Also, reproduced data 1 from the demodulation circuit 1402 (Fig. 11)
212 is input to the control circuit 1502. The control circuit 1502 receives various control signals 12l3 from the above two types of input signals, and also inputs and outputs information to and from an external device.

The modulation circuit 1302 in FIG. 10 performs modulation based on the modulation method shown in Table 1, for example. This is the so-called
This is called the 2.7 modulation method, and the input data (recorded information) shown in the left column of Table 1 is converted into predetermined modulation data shown in the right column of the same figure. At that time, in the modulation data,
The number of consecutive bits of "O" is set to be 2 to 7 bits. Then, for example, according to the sector format shown in FIG. 14(a), at an appropriate timing,
Modulation data 1310 is output to semiconductor laser drive circuit 1301 in FIG.

In FIG. 14(a), the preformat section 3003
is determined from a sector mark section 1701 for obtaining synchronization timing in units of sectors, and an ID section 1702 containing sector address information. These are the 33rd
As shown in the figure, a mark 281l that cannot be recorded or erased
and physical irregularities 2808 corresponding to non-marks 2812
It is engraved on the magneto-optical disk 1201 by. The MO section 3002 as a data section records information data.
It consists of a normal use range 1703 for reproduction and erasing, and a pair of gap parts 1704 and 1705 located before and after the normal use range 1703. Then, the modulation data 1310 is recorded in the normal use range 1703. The record at this time is
As shown in FIG. 33 or 36, mark 2809 and non-mark 2810 are performed by the MO signal. Note that the gap portions 1704 and I705 arranged between the preformat portion 3003 and the MO portion 3002 are extra areas for recording information in the normal use range 1703. In other words, these gap portions 1704 and 1705 are connected to the rotation of the spindle motor 1202 and the sector 300.
This area takes into account the fact that the recording start position and recording end position shift back and forth due to a phase error that occurs between the four units of synchronization timing and the like.

As shown in FIG. 13, the semiconductor laser drive circuit 13
01 includes a recording/erasing light amount control circuit 1803, and this recording/erasing light amount control circuit 1803 includes a modulation circuit 1302.
From (FIG. 10), modulation data 1310 is input to the semiconductor laser drive circuit 1301.

Further, a reproduction light amount control signal 1810 is input from the controller 1208 (FIG. 9) to the reproduction light amount control circuit 1801,
During reproduction, the amount of reproduction light from the semiconductor laser 2801 in the optical head 203 is appropriately controlled.

Recording/erasing light amount control signal 1 from controller 1208
81l is input to a recording/erasing light amount control circuit 1803, and the light amount of the semiconductor laser 2801 corresponding to recording and erasing is controlled. Furthermore, the high-frequency superposition switch signal l812 from the controller 1208 is input to the high-frequency superposition circuit 1802, and based on this, the high-frequency superposition circuit 1802 generates an output signal 18l6 that is turned on and off at high frequency. By being superimposed on the output signal 1814 of the reproduction light amount control circuit 1801, the noise of the semiconductor laser 2801 caused by the return light from the magneto-optical disk 1201 is reduced. Note that the output signal l816 of the high frequency superimposition circuit 1802 is output to the addition circuit 1805 only during reproduction.

Reproducing light amount control circuit 1801, recording/erasing light amount control circuit 1
803 and each output signal 18 of the high frequency superimposition circuit 1802
14 to 1816 are added by an adder circuit 1805, and a semiconductor laser drive current of 12lO is input to the semiconductor laser 2801. Semiconductor laser 280 1 light! (light intensity) is converted into an electrical signal that changes according to the light intensity by a photodetector 1806 in the optical head 1203, and a light intensity monitor signal 1813 is transmitted to the controller 1208 via a light intensity monitor circuit 1804. It has become.

In the controller 1208, the light amount monitor signal l813
Based on the reproduction light amount control signal 1810, the recording/
Erasing light amount control light amount 1811 and high frequency superimposition switch signal 1812 are output. In other words, the semiconductor laser 280l
The light intensity (amount of light) is controlled to be appropriate during playback and during recording/erasing.

Next, to explain each operation of recording Sj and erasing information, the first
4. As shown in FIG. 4(b), the high frequency superimposed switch signal 18
12 becomes a low level (゛゜0'') in the normal use range ■Ma03 (see figure (a)), and becomes a high level (``1'') in other parts. That is, the MO part 3002
The high frequency superimposition circuit 18 in the normal use range 1703 within
Turn off the high frequency superimposition by 02 and set the normal usage range to 170
For settings other than 3, it is turned on. Along with this, the modulated data 1310 is recorded as an MO signal in the normal use range 1703, as shown in FIG.

At this time, as shown in the same figure (d), the semiconductor laser 280
1 light level (light intensity) 1910 is normal use range 17
03 will be high level, other than that will be low level.

That is, the sector synchronization timing is detected from the sector mark section 1701 in the preformat section 3003, address information etc. are read out from the ID section 1702, and while confirming a predetermined address, the MO section 3002
Information is recorded and erased.

On the other hand, when reproducing information recorded in the normal use range 1703, as shown in FIG. In addition, since no recording is performed, the modulated data 1 3 1 0 is at a low level (“O”) as shown in FIG.
). Furthermore, as shown in FIG. 2(d), the light amount level 1910 is a low level. In other words, the sector mark section 170 in the preformat section 3003 ((a) in the same figure)
1 to sector 3004, and ID
Address (address) information etc. are read out from the section 1702,
While checking the predetermined address (address) one after another, MO section 3
From 002 onwards, information recorded as an MO signal is reproduced.

More specifically, the timing generation circuit 1501 in FIG. 12 is a signal processing circuit 1401 as shown in FIG.
Sector mark signal 1411 output from (Fig. 11)
A sector mark detection circuit 2101 is provided. A sector mark detection circuit 2101 detects the presence or absence of a sector mark, and outputs a sector mark detection signal 2110 based on the detection. Sector mark detection signal 21
10 is transmitted to a counter 2102, a timer circuit 2104, and a determination circuit 2106, respectively.

The output signals 2111 and 21l2 of the counter 2102 and the timer circuit 2104 are respectively input to the switch circuit 2103, and the switch circuit 2103 selects one of the output signals 211l and 2112 and outputs it as the reference timing signal 1510.

This reference timing signal 1510 is also input to the data portion determination circuit 2107, and based on this, a data portion determination signal 2116, which will be described later, is output. Timer circuit 210
4, another output signal 2113 is transmitted to the window generation circuit 2105. The output signal 2114 of the window generation circuit 2105 is input to the determination circuit 2106.

The determination circuit 2106 generates a timing determination signal 211 from the output signal 2l14 and the sector mark detection signal 2110.
5 (described later) is output. Timing judgment signal 2115
Therefore, in the switch circuit 2103, the counter 2102
Either one of the output signal 2111 of the timer circuit 2111 and the output signal 2112 of the timer circuit 2104 is selected. The reference timing signal 1510, the data portion determination signal 2116, and the timing determination signal 2l15 are each supplied to the control circuit 15.
02 (Figure 12). Control circuit 1
502, based on the various signals 15lO, 2115, 2116 outputted from these timing generation circuits 1501 and the reproduction data 1212, the various control signals 1213 described above are transmitted to the recording circuit 1206 and the reproduction circuit 1207 (
(Fig. 9), and each control of recording, reproduction, and erasure of information is performed.

As shown in FIG. 17, the sector mark detection circuit 21
01 includes a counter circuit 2201 and a signal processing circuit 14
Sector mark signal 1 output from 01 <Figure 11)
411 monitors the counter circuit 2201, for example,
9 counter numbers. It is transmitted to Nos. 1 to 9. Counter No. Each output signal 2211 to 221 of 1 to No. 9
9 are respectively transmitted to a determination circuit 2202, and a sector mark detection signal 2110 is output based on the determination result of the determination circuit 2202. As described above, the sector mark detection circuit 2101 detects the sector mark portion 1701 (for example, FIG. 14(a)) and determines the synchronization timing necessary to perform each sector-based recording, playback, and erase operation. This is the circuit to obtain.

Based on FIG. 18, the counter No. in the counter circuit 2201 described above. 1~No. 9 will be explained. Here, the notch turn of the sector mark portion 1701 is, for example,
Mark 2811 and non-mark 2 as shown in FIG.
812. In this example, as shown in Figure (a), multiple marks are created so that the ratio of mark length and non-mark length is in the order of 5:3:3:7:3:3:3:3:5. 2811 is engraved.

The sector mark signal 1411 obtained by reproducing the turn of the mark 2811 and the non-mark 2812 is, for example, low level ("0") in the mark part and low level ("0") in the non-mark part, as shown in FIG. It is converted into a binary signal that becomes high level (“1”) at .

This sector mark signal 14l1 is transmitted to the counter No. 1.
~No. 9, first, the counter N
o,1 ((e) in the figure) counts the number of clocks of the counter clock 2310 corresponding to the mark length "5". The counter clock 2310 has a higher frequency than the sector mark signal 1411, as shown in FIG. 2(d). If this count is within a predetermined range, it means that the first mark 2811 (mark length ゜'5'') has been accurately detected.
Similarly, a non-mark 28 with a non-mark length of ``3''
l2 is detected. In this way, the marks 2811 and non-marks 2812 of the sector mark section 1701 are sequentially detected, and finally the mark length "'5" is detected as the counter NO.
9 detects.

The detection signals 2211 to 2219 of the nine marks 2811 or non-marks 28l2 obtained as described above are sent to the determination circuit 2202 (FIG. 17).

Then, these nine marks 281l or non-marks 281
It is determined whether or not all or part of the detection results for 2 match the pattern of the sector mark portion 1701.
2 is determined. As a result, the sector mark portion 17
01, the sector mark detection signal 2110 becomes low level (“O”). The sector mark detection signal 2110 obtained as above is used as synchronization timing for each sector 3004. can be used.

Next, based on FIG. 19, the timing generation circuit 1501
The waveforms of each part of will be explained below.

As shown in FIG. 2(b), the sector mark detection signal 211
0 becomes low level when the sector mark section 1701 ((a) in the figure) in the preformat section 3003 is detected, and the falling edge of this sector mark detection signal 2110 coincides with the synchronization timing of the sector 3004. Become. The counter 2102 receives the sector mark detection signal 21
After counting a predetermined number of counts from the falling edge of 10, the counter output signal 21 is output as shown in FIG.
Set l1 to low level. On the other hand, the count number of the timer circuit 2104 is calculated by adding the count number of the counter 2102 to one sector 300.
It is set to be larger by the sector length of 4.

Therefore, as shown in FIG. 19(d), the timer circuit 2
The falling edge of the output signal 2112 of the sector 104 almost coincides in timing with the falling edge of the counter output signal 21l1 of the next sector 3004.

Further, as shown in FIG. 2(e), the window generation circuit 21
The output signal 2114 of 05 is the sector mark detection signal 21
Based on the falling edge of 10, the next sector 3004
The sector mark detection signal 2110 becomes low level with a predetermined window width near the falling edge. If a falling edge of the sector mark detection signal 2110 exists when the output signal 2114 of the window generation circuit 2105 is at a low level, the timing determination signal 2115, which is the output signal of the determination circuit 2106, will change to the solid line in FIG. As shown in , the level has reached a high level. On the other hand, sector mark detection signal 2
If there is no falling edge of 110, the signal becomes low level (indicated by the dotted line in FIG. 3(f)). Therefore, the timing determination signal 2115 is a signal that determines whether the sector mark portion 1701 was detected within a predetermined range or whether there was a detection error.

In the switch circuit 2103, the sector mark section 17
If 01 is detected, the counter output signal 2111
is selected, and if there is a detection error otherwise, the timer circuit output signal 2112 is selected. As a result, as shown in FIG. 4(g), even if the detection ξ of the sector mark portion 1701 occurs, the reference timing signal 1510 is reliably corrected based on the timing of the sector 3004 before processing. Can be output. The reference timing signal 1510 obtained in this way is transmitted to the data part determination circuit 2107.

The data section determination circuit 2107 is a type of counter, and its output signal, the data section determination signal 2116, is the MO section 3
It becomes low level in the normal use range 1703 of 002 ((h) in the figure). data part determination signal 2116
can be used as a signal to distinguish between the preformat section 3003 and the MO section 3002. The reference timing signal l510 and timing determination signal 2 obtained in this way
115 and the data portion generation signal 2116 are transmitted to the control circuit 1502 in FIG. In the control circuit 1502, the above signals 1510, 2115 and 2
The various control signals 1213 described above are generated based on the signal 116.

Next, the operation of the signal processing circuit 1401 in FIG. 11 will be explained based on FIGS. Circuit 1401 (second
It is input to the buffer amplifier 2501 in Figure 0). Output signal 2510 of buffer amplifier 2501 is transmitted to MO waveform processing section 2502 and preformat waveform processing section 2503. From the MO waveform processing unit 2502, the MO unit 3
While the MO binary signal 2511 corresponding to the mark 2809 and non-mark 2810 recorded as the MO signal in 002 is output, the preformat waveform processing unit 2503
IDZ value conversion signal 25{2 corresponding to mark 2811 and non-mark 2812 of preformat section 3003
is output. These binary signals 2511 and 2512
is input to the data synchronization unit 2504, and the data synchronization unit 2
PLL in 504 (PHASE LOCKECD
I, oop), synchronous data 2513 synchronized with the clock is generated, and the demodulation circuit 1402 (.
(Figure 1).

Further, the preformat waveform processing section 2503 generates a sector mark signal 1411, and the timing generation circuit 15 generates a sector mark signal 1411.
01 (Figure 12).

In the signal processing control section 2505, the signal processing circuit 1
Various control signals 2514 to 2517 are input and output between each section in 401. Further, various control signals 1213 are input/output to/from the controller 208 in FIG.

FIG. 21 shows waveforms of each part of the signal processing circuit 1401.

As shown in Fig. 2l (b) and (c), the reproduced signals S1 and S2 are M
It is differentially applied in the O waveform processing section 2502 and the MO section 300
Only the two MO signals are separated, further binarized, and the MO
A binary signal 2511 is generated ((d) in the same figure). or,
The reproduced signals S1 and S2 are processed by the preformat waveform processing section 25.
03, only the information in the preformat section 3003 is separated, and further binarized to obtain an IDZ digitized signal 2512 and a sector mark signal 1411 ((e) and (g) in the same figure).

MO section 30 by differential and addition of reproduced signals S1 and S2.
The reason why the preformat section 3003 and the preformat section 3003 can be separated is that the polarities of the reproduced signals S1 and S2 are reversed in the MO section 3002, as shown in FIG. This is because the portion 3003 is the same. The MOZ digitized signal 2511 and the ID binary signal 25l2 are each converted into synchronous data 2513 synchronized with a clock in a data synchronization section 2504, as shown in FIG. 21(f).

FIG. 22 is a detailed explanation of the waveform in FIG. 21. For example, based on the modulation data 1310 (FIG. 22(a)) that has been determined based on the modulation rules in Table 1 above, With the unevenness 2808 (or MO signal), the mark 2811 (or 2809) and the non-mark 281 as shown in FIG.
2 (or 2810) is recorded. These marks 2811 (or 2809) and non-marks 2
812 (or 2810) is reproduced by irradiation with the laser spot 2701, and as shown in FIG. 3(C), the reproduced signals S1 and S2 are signals that take a peak value at the center of the mark 2811 (or 2809).

The MO2-valued signal 2511 or 102-valued signal 2512 is a signal that has detected this peak position, and its rising edge coincides with the peak position (see (d) in the figure). In the PLL in the data synchronization unit 2504, MO2
A synchronous clock is generated from the digitized signal 2511 or the ID binary signal 2512, and synchronized with this clock to obtain synchronous data 25l3. As shown in FIG. 4(e), the synchronization data 2513 is data obtained by faithfully reproducing the modulation data 1310.

FIG. 7(a) shows the main part of the preformat waveform processing section 2503. The above-mentioned reproduced signals S1 and S2 are input to the summing amplifier 64 in the preformat waveform processing section 2503, where, as described above, St S2 is added to the preformat section 300 in the reproduced signal.
Only information No. 3 is separated. The information in this preformat section 3003 is for preformat A.
The signal is input to the GC amplifier 65, where it is amplified according to the amplitude, and then binarized by the binarization circuit 66 and output as the aforementioned IDZ digitized signal 25l2.

Further, FIG. 7(b) shows the main part of the MO waveform processing section 2502, and the reproduced signals S1 and S2 are transmitted to the MO waveform processing section 2502.
The signal is input to the differential amplifier 74 in the reproduction signal 502, where S1 and S2 are differentiated as described above, so that only the MO signal in the reproduced signal is separated. The MO signal is input to the MO signal AGC amplifier 75, where:
After being amplified according to the amplitude, the binarization circuit 76 outputs 2
The signal is converted into a value and an MO binary signal 2511 is output. Note that the AGC voltage is output from the MO signal AGC amplifier 75 to the A/D converter 49 in the controller 1208 (see FIG. 3l).

Next, the structure of the preformat AGC amplifier 65 that serves as the first auto gain control section will be described in more detail. As shown in FIG. 4, the preformat AGC amplifier 65 mainly consists of a clamp circuit 7.
8, a converter 79, an AGC voltage generation circuit 80, and a voltage control amplifier (hereinafter referred to as VCA) 77, and the addition signal which is the output signal of the addition amplifier 64 mentioned above is input to the VCA 77. There is.

The amplification degree of the VCA 77 changes according to the AGC voltage output from the AGC voltage generation circuit 80, and as shown in FIG. 43, the amplification degree is configured to decrease as the AGC voltage increases.

The output of the VCA 77 is transmitted to the binarization circuit 66 (FIG. 7) and is also input to the clamp circuit 78. In the clamp circuit 78, the DC component in the output signal of the VCA 77 is cut, and the positive output of the AC component (corresponding to the peak-to-peak value) is converted to the forward voltage drop value of the diode D by the diode D in the same circuit 78. The negative output is transmitted to the inverting input terminal of the subsequent comparator 79 without being clamped.

In the comparator 79, the reference voltage ■ is applied to the non-inverting input terminal. and the output voltage of the clamp circuit 78 are compared in magnitude.

The output signal of the comparator 79 is input to one input terminal of an AND circuit 90, and the other input terminal of the AND circuit 90 is connected to an inverter 9 which serves as a first control means.
A preformat hold timing signal l13 (described later) is inputted via the preformat signal l13. Then, the output signal of the AND circuit 90 is passed through the resistor 92 to the AGC
It is input to the voltage generation circuit 80.

In the above arrangement, the operation when the preformat hold timing signal 113 is at a low level and the preformat AGC amplifier 65 does not hold the AGC voltage will be described first. At this time, the input signal from the inverter 91 to the AND circuit 90 becomes high level, so the output signal of the AND circuit 90 is transmitted from the converter 79 to the A
It is determined by the input signal to the ND circuit 90.

Now, the output amplitude of the clamp circuit 78 is the reference voltage ■.

If it is larger than , the output signal of the comparator 79 becomes high level, and therefore the output of the AND circuit 90 also becomes high level, so that the transistor 81 is turned on.

Therefore, the capacitor 83 is charged by the power supply VCC via the charging resistor 82, and the AGC voltage, which is the voltage across the capacitor 83, increases. At this time, the charging time constant is
It is determined by the charging resistor 82 and capacitor 83. AGC occurring at connection point A between charging resistor 82 and capacitor 83
The voltage is fed back to the VCA 77 as a control voltage for amplification adjustment, but if the AGC voltage increases as described above, the VCA77
The amplification degree of CA77 decreases.

On the other hand, the output amplitude of the clamp circuit 78 is the reference voltage ■. If the output signal is smaller than , the output signal of the comparator 79 and therefore the output signal of the AND circuit 90 becomes low level, and the transistor 81 is turned off, so that the charge stored in the capacitor 83 is discharged via the discharge resistor 84. Ru. At this time, the discharge time constant is determined by the discharge resistor 84 and the capacitor 83. As the capacitor 83 discharges, the AGC
The voltage becomes smaller and the amplification degree of the VCA 77 becomes larger.

As is clear from the above explanation, there is a relationship between the beak-to-beak value (P-P value) of the S1 and S2 addition signals and the AGC voltage as shown in FIG. It can be seen that in the normal amplitude range, the AGC voltage increases monotonically with respect to the beak-to-beak value of the differential signal. That is, A
The maximum and minimum values of the GC voltage correspond to the maximum and minimum values of the peak-to-peak values of the summed signal. Note that the clamp circuit 78 described above may be a full-wave rectifier circuit.

Next, in the preformat AGC amplifier 65,
The operation when holding the GC voltage will be described. However, the AGC amplifier 65 for preformat
The voltage is held when the optical head 12 is in a mode that requires holding during recording/erasing, etc. described below.
03 (FIG. 9) is the MO section 3 in each sector 3004.
002, and when the optical head 1203 passes through the preformat section 3003 of each sector 3004, the address information, etc. of the preformat section 3003 is reproduced even when recording or erasing. Since it is necessary, the AGC voltage hold is released.

Therefore, one hold period of the AGC voltage in the preformat AGC amplifier 65 is the period during which the AGC voltage passes through the MO section 3002 of one sector 3004, and when recording, erasing, etc. are performed continuously on multiple sectors 3004. In the preformat section 3003 and MO section 3003 of each sector 3004, turning on (hold release) and holding of the AGC voltage are repeated alternately.

In the AGC amplifier 65 for preformat, the AGC
When holding the voltage, if the preformat hold timing signal 113 is set to high level,
The output signal of inverter 91 is inverted from high level to low level. Accordingly, if the output signal of the AND circuit 90 has been at a low level (that is, the output signal of the comparator 79 has been at a low level), it will remain at a low level from now on, and the output signal of the AND circuit 90 will remain at a high level until then ( That is, if the output signal of the comparator 79 is high level, it is inverted to low level, so if the transistor 81 was previously off, it remains off and the transistor 8
If 1 was previously on, it will be switched off.

Therefore, hold tie approval signal 1 for preformat
13 is set to high level, the charge accumulated in the capacitor 83 will be discharged after that, but one hold period in the preformat AGC amplifier 65 is the MO of one sector 3004.
3002, so if the discharge time constant of the capacitor 83 and the discharge resistor 84 is set sufficiently large, the amount of change in the charge of the capacitor 83 during one hold period, that is, the AGC Since the amount of change in voltage is very small, it can be considered that the AGC voltage is held at a substantially constant value during one hold period.

As described in connection with FIGS. 46 to 48, accurate reproduction becomes difficult due to fluctuations in the amplification degree of the AGC amplifier during recording/erasing and during access. Therefore, the preformat AGC amplifier 65 is set to hold the AGC voltage during recording/erasing and access (however, as described above, only during the period when it passes through the MO section 3002 of each sector 3004). .

FIG. 2 shows a logic circuit for controlling the hold timing of the AGC voltage in the preformat AGC amplifier 65.

This logic circuit consists of an OR circuit 100.
A recording/erasing timing signal 94 and an access timing signal 95 are input to 0. The recording/erasing timing signal 94 is a signal that is at a high level when recording or erasing, and is at a low level at other times, and the access timing signal 95
is a signal that is high level when accessing and low level otherwise. Therefore, as is clear from Table 2 below, the preformat hold timing signal 113 obtained as the output signal of the OR circuit 100 is at a high level (“1”) at the time of recording/erasing or accessing.
, otherwise it becomes low level (“0′).

Also, A. The GC voltage detection timing signal 96 is a signal that is at a high level when an AGC voltage is detected by a test light, etc., which will be described later, and is at a low level at other times.
The GC voltage detection timing signal 96 is used as it is as the AGC speed control signal 97 for preformat. The preformat AGC speed control signal 97 is a signal for switching the response speed of the preformer/former AC/C amplifier 65 into two stages, for example, high speed and low speed, and as shown in Table 2, the ACC voltage At the time of detection, the preformat AGC speed control signal 97 is at a high level (
"'1"), and Brifoma. , the response speed of the AGC amplifier 65 for preformat is high, and when the AGC voltage is not detected, the AGC speed control signal 97 for preformat is set to low level (“'O”), and the AGC amplifier 65 for preformat The response speed of is said to be slow. Note that the symbol x in Table 2 indicates that it may be either "1" or "0".

Next, a circuit for switching the response speed of the preformat AGC amplifier 65 into two stages, for example, high speed and low speed, will be described.

As shown in FIG. 6, this circuit that serves as a response speed changing means is configured as a response speed changing/resetting circuit 101 that also has an AGC voltage reset function. That is, the response speed change/reset circuit 101
It consists of a pair of oven collectors 87 and 88 and a discharge resistor 89, and the output of the oven collector 88 is connected to the charging resistor 82 in the preformat 800 amplifier 65.
and a connection point A between the capacitor 83 and the capacitor 83.

A preformat AGC speed control signal 97 is input to the oven collector 87, while the open collector 8
An AGC reset signal 102 for pre-format is input to 8. The preformat ACC speed control signal 97 becomes high level when the AGC voltage is detected. At this time, the output of the open collector 87 becomes low level, and a discharge resistor 89 is connected in parallel with the discharge resistor 84 in FIG. As a result, the time required for discharging the capacitor 83 is shortened.

On the other hand, the preformat AGC reset signal 102 becomes high level when the system is started up or when a system abnormality occurs. At this time, the discharge resistor 84 is short-circuited, so that the discharge is instantaneously completed.

Next, a more specific structure of the MO signal AGC amplifier 75 having the role of the second auto gain control section will be explained. As shown in Figure 5, the AGC for MO signal
The main part of the amplifier 75 is constructed in the same way as the preformat AGC amplifier 65. Here, members having the same functions are given the same reference numerals and their explanations will be omitted.

In the MO signal AGC amplifier 75, the AGC voltage generated by the AGC voltage generation circuit 80 is input to the hold circuit 93 and one contact 94a of the analog switch 94. The hold circuit 93 has a role as a second control means in claim 2 of the claim column and a hold means in claim 4, and is, for example, an A/
The D converter and the subsequent D/A converter are used to hold the AGC voltage sampled at a predetermined timing. The output signal of the hold circuit 93 is input to the other contact 94b of the analog switch 94. A hold timing signal 103 for the MO signal, which will be described later, is supplied to the hold circuit 93 and the analog switch 94, and this hold timing signal 103 for the MO signal is at low level, so that the M
When not holding the AGC voltage in the O signal AGC amplifier 75, as shown in the figure, the analog switch 9
4 contacts 94a and 94b are opened, and the AGC voltage is fed back to the VCA 77 as it is. The operation of the clamp circuit 78 and the AGC voltage generation circuit 80 when the AGC voltage is not held is as follows: ■The input signal to the CA 77 is S.
Clamp circuits 78 and A in the preformat AGC amplifier 65 except for the differential signals of 1 and S2.
Since the operation is similar to that of the GC voltage generation circuit 80, detailed explanation will be omitted here.

On the other hand, as will be described later, when the AGC voltage is held during recording/erasing, etc., the contact 94 of the analog switch 94
constant AGC held with a and 94b closed
The voltage is fed back to the VCA 77, and the amplification degree of the VCA 77 is maintained at a constant value. In the MO signal AGC amplifier 75, the AGC voltage is held by the preformat section 3003 of each sector 3004 and the M
This is performed for both parts of O section 3002. Note that the MO signal AGC amplifier 75 is also provided with a response speed change/reset circuit 101 similar to the preformat AGC amplifier 65. Further, as the hold circuit 93, the above-mentioned A
Instead of having a /D converter and a D/A converter, an analog sample and hold circuit may be used.

Note that instead of the hold circuit 93, an analog switch may be used to fix the voltage to a constant voltage. In this case, since there will be some deviation from the actual AGC voltage, it is preferable to set the above-mentioned deviation to be as small as possible.

The MO signal AGC amplifier 75 holds the AGC voltage at the time of recording/erasing and access, as well as the preformat AGC amplifier 65 and the MO section 3.
When reproducing 002, the AGC voltage is held even in an unrecorded area where no information pulse group is detected. This is because, as mentioned above, when the MO signal AGC amplifier 75 is operated even in the unrecorded area, the amplitude of the reproduced signal is almost zero level in the unrecorded area, so the amplification degree increases near the maximum level, and the next Second, when accessing a recorded area, the degree of amplification may become excessive and accurate reproduction may not be possible. On the other hand, the preformat section 3002
Since information such as addresses is always recorded in the pre-format AGC amplifier 65, the hold/on control of the AGC voltage is not performed based on the detection of pulse groups (recorded areas). be. Note that the circuit for detecting the pulse group will be described in detail later.

The logic circuit for switching between holding and turning on the AGC voltage in the MO signal AGC amplifier 75 is as shown in Fig. 3.
It includes a NOR circuit 104 and an OR circuit 105. N
The pulse group detection signal 106 and the AGC voltage detection timing signal 96 are input to the OR circuit 104 . As will be described later, the pulse group detection signal 106 is a signal generated based on the determination result of the MO signal recorded area and unrecorded area in the MO section 3002. If it is a recorded area that is detected, the level is high, and if it is an unrecorded area where no pulse group is detected, the level is low.

The OR circuit 105 receives the output signal of the NOR circuit 104,
The recording/erase timing signal 94 and the access timing signal 95 described above are input, and the output signal of this OR circuit 105 is used as the hold timing signal 103 for the MO signal. Also, here, the AGC voltage detection timing signal 96 is directly used as the AGC speed control signal 107 for the MO signal. In this case, the MO data hold timing signal and AGC speed control signal change as shown in Table 3 for each input signal combination. That is, the MO signal hold timing signal 103 becomes high level when an information pulse group is not detected in the MO (data) section 3002 during recording/erasing, access, and playback mode. , MO signal A
The AGC voltage of the GC amplifier 75 is held at the value immediately before the start of recording, erasing, etc. The MO signal hold timing signal 103 is also input to the inverter 91 (FIG. 5), so that the capacitor 83 is no longer charged and the output of the hold circuit 93 becomes the AGC voltage.

Here, regarding the control of holding/on switching of the AGC voltage in each of the AGC amplifiers 65 and 75 and the switching control of response speed when adjusting the amplification degree based on the AGC voltage, we will explain step 1 based on the flowchart in FIG. To explain further, first, it is determined whether or not it is recording/erasing time (S
L), if so, AG of both AGC 65 and 75
C voltage is held (S2).

On the other hand, if it is not during recording/erasing in S1, it is determined whether or not it is during access (S3), and if it is during access, the AGC voltages of both AGC amplifiers 65 and 75 are held (S2).

If it is not the time of access, then it is determined whether or not it is the time of AGC voltage detection such as a test light described later (S4
), if so, after setting the response speed to fast (35
), the AGC voltages of both AGC amplifiers 65 and 75 are turned on (S6).

On the other hand, if the AGC voltage is not being detected in S4, the only remaining mode is the playback mode.
This means that the information recorded in is being played back. In that case, it is determined whether or not a pulse group by the MO signal is detected (S7). If detected, it means that the recorded area is being played back, so after setting the response speed to a low speed, (S8), the AGC voltages of both AGC amplifiers 65 and 75 are turned on, and the degree of amplification is adjusted based on the amplitude of the reproduced signal (S6).

On the other hand, if the pulse group due to the MO signal is not detected in S7, it means that an unrecorded area in the MO section 3002 is being reproduced.
Only the C voltage is held (S2).

In FIG. 8, a sector 3004 indicated by A ((a
)), the MO signal is recorded in the MO section 3002, and the M signal recorded in the MO section 3002 is recorded in the sector 3004 indicated by B.
The O signal is regenerated, and in sector 3004 indicated by C, the MO signal is regenerated.
It is assumed that the MO signal recorded in section 3002 is to be erased.

In that case, the amplitude of the reproduced signal S1·32 (FIG. 3(b)) becomes excessive in the MO section 3003 of the sector 3004 of A, but in this embodiment, the MO section 3003 of the sector 3004 of A
Since the AGC voltages of both AGC amplifiers 65 and 75 are held, the preformat AGC voltage is
The AGC voltage of Amb 65 ((d) in the same figure) is in sector 3 of A.
Since the value at the end of playback of the preformat section 3003 of 004 was held, the value of the preformat section 30 of sector 3004 of B is held as shown in part 81 of FIG.
The amplification degree of the preformat AGC amplifier 65 when reproducing data 03 becomes an appropriate value, and the preformat section 3003 of the sector B 3004 is smoothly reproduced.

Similarly, in sector C 3004 to be erased, MO section 3
Since the AGC voltages of both the AGC amplifiers 65 and 75 are held when the signal 002 passes, the reproduction of the preformat section 3003 of the next D sector 3004 is also performed properly.

In addition, in the sector B 3004 that performs playback, the MO section 3
Assuming that there is no pulse group due to the MO signal in 002, the AGC voltage of the preformat AGC amplifier 65 is held when passing through the MO section 3002 of the B sector 3004, so the preformat section of the next C sector 3004 is held. 3003 is also played properly.

By the way, the size of the mark 2809 in magneto-optical recording changes depending on the recording conditions such as the recording light amount, the recording pulse length, and the externally applied magnetic field 2806.

That is, as shown in FIGS. 39A and 39B, as the amplitude of the recording pulse, that is, the amount of recording light increases, the size of the recorded mark 2809 increases (however, the length of the recording pulse is constant). Furthermore, as shown in FIGS. 40(a) and 40(b), even if the recording pulse length is increased while the amplitude of the recording pulse is held at a constant value, the mark recorded is approximately proportional to the recording pulse length. The size of 2809 increases.

As described above, if the size of the mark 2809 varies, errors may occur in the reproduced data. For example, in FIG. 41, under the recording conditions in which the mark 2809 is recorded with the size shown by the solid line in FIG. 41, the S/N ratio is the best, as shown by the solid line in FIG. 41(b). . On the other hand, when recording, the size of the mark 2809 is larger or smaller than the recording light amount (or recording pulse length) corresponding to the solid line, as shown by the dotted line in FIG. It can be seen that if the amplitude is too large or too small, the amplitude (beak peak value) of the reproduced signal becomes small, as shown by the dotted line in FIG.
(See Publication No. 0138). Therefore, in order to obtain error-free reproduced data, it is necessary to always optimally control the recording conditions.

For optimal control of recording conditions, record information with a predetermined fundamental frequency is experimentally recorded (test write) in a magneto-optical memory by changing the recording light intensity, etc., and the conditions are determined so that the amplitude of the reproduced signal during reproduction is maximized. It is known that the following recording is performed under the recording conditions at that time. By the way, in that case,
In order to actually determine the amplitude of the reproduced signal, a circuit for detecting the maximum amplitude, envelope, first and second harmonics, etc. is required, so there is a problem that the circuit structure becomes complicated.

Therefore, the magneto-optical memory device is used for the MO signal GC amplifier 7.
5, it is conceivable to obtain the amplitude of the reproduced signal by sampling the AGC voltage for controlling the amplification degree of the MO signal AGC amplifier 75.

That is, under the recording conditions where the amplitude of the reproduced signal is maximum,
Since the amplification degree of the MO signal AGC amplifier can be considered to be at a level close to the minimum level, test writing was performed under multiple recording conditions to determine the MO signal AGC amplifier 75.
By finding the recording condition that minimizes the amplification degree (determined by the AGC voltage), it can be determined that this is approximately the optimal recording condition.

To explain more specifically with reference to FIG. 42, for example, the figure (a)
Eight sectors 3004 indicated by A-H are used as recording areas for test writing, and each MO section 3004 is written with increasing recording light intensity (or recording pulse length) as shown in FIG.
Assume that test writing is performed on 02.

M in sector 3004 recorded as above
When the information in the O section 3002 is reproduced, as shown in FIG. 42(c), for example, an MO signal consisting of a differential signal of the above reproduced signals S1 and S2 is obtained for each sector 3004.

Furthermore, since there is a relationship between the AGC voltage and the amplification degree of the MO signal AGC amplifier 75, as shown in FIG. 43, as the AGC voltage increases, the amplification degree decreases.
Corresponding to the amplitude of the MO signal 004, the AGC voltage changes as shown in FIG. 42(d).

That is, as the amplitude of the MO signal increases, the AGC voltage increases, and accordingly, the MO signal 80C amplifier 75
The degree of amplification becomes smaller. Note that there is a relationship as shown in Figure 44 between the beak peak value (T'-P value) of the differential signal of S1 and S2 and the AGC voltage, and in the normal amplitude range in the figure, the AGC voltage is It increases almost monotonically as the beak-to-beak value of the differential signal increases.

The AGC voltage of each sector 3004 is sampled at the sample timing shown in FIG. 42(e) (for example, at the rising edge of each pulse).

Then, the recording light amount (or recording pulse length) corresponding to the maximum value of the AGC voltage (corresponding to the position where the amplitude of the MO signal is maximum) is determined, and from now on, recording and recording will be performed using this recording light amount (or recording pulse length). Each erasing operation is performed.

In the above example, the AGC voltage of the MO signal AGC amplifier 75 obtained by reproducing sectors E, F, and G is at the same level, and the recording light amount (or recording pulse length) of sector G is
It can be seen that the AGC voltage decreases (that is, the amplitude of the MO signal decreases) whether the value is made larger or smaller. Therefore, the optimum recording conditions are determined from the recording light amount (or recording pulse length) of sectors E, F, and G.

In general, when recording conditions such as recording light intensity and recording pulse length are changed, the recording mark length also changes accordingly, and as shown in Figure 45, the recording mark length corresponds to the optimal recording condition indicated by the broken line in the figure. If the length is longer or shorter than the length, the AGC voltage will decrease and the S/N ratio will decrease.

Also, at this time, bit jitter becomes large. For convenience of explanation, when changing the recording conditions, it is assumed that the recording pulse length is constant when changing the recording light amount, and that the recording light amount is constant when changing the recording pulse length.

In the test light described above, for example, if the recording light amount is to be changed sequentially, the light amount monitor circuit 1804 described above
(FIG. 13), the light amount monitor signal l813 is sent to the processor 70 in the controller 1208 shown in FIG.
and stored in a storage element such as RAM or E2FROM provided in the processor 70, for example.

Then, as shown in FIG. 42(C), sectors 300 of A-H
When sequentially reproducing the MO signals recorded in sector 4, each sector 3
The AGC voltage of the MO signal AGC amplifier 75 is sampled every 004 and stored in the above-mentioned storage element.

Then, the optimum recording condition when the AGC voltage becomes the maximum is determined, and thereafter, during recording, the processor 70 outputs a recording/erasing light amount control signal 1811 and a recording pulse length control signal corresponding to the above-mentioned optimum recording condition. Ru.

Recording/erasing scene ijl The control signal 1811 is the recording/erasing scene described above.
It is input to the erasing light amount control circuit 1803 (Fig. 13),
The amount of light from the semiconductor laser 2801 is controlled during recording and erasing.

On the other hand, the pulse length control signal is sent to the aforementioned modulation circuit 1302, and modulated data is controlled based on this.

That is, as shown in FIG. 32, recording data l311 sent from the controller 1208 is input to the modulation section 71 in the modulation circuit 1302. The modulation section 71 performs modulation in synchronization with the timing signal, for example, according to the 2,7 modulation method as shown in Table 1. The modulated recording data 1311 is processed in a recording format unit 72 to match the recording format in synchronization with the timing signal, and further modulated in a recording pulse length control unit 73 based on the above-mentioned pulse length control signal. Data 1310 is generated. This modulation data 1310 is output to the semiconductor laser drive circuit 1301 in FIG. In this way, the recording pulse length can be controlled.

A pulse group detection circuit for detecting whether or not a pulse group based on an MO signal exists in the MO section 3003 will be described below.

That is, as shown in FIG. 23, the pulse group detection circuitry 7 includes, for example, a retriggerable pulse generation circuit 16,
The retriggerable pulse generation circuit 16 has an AGC for MO signal.
An MOZ digitized signal 2511, which is an output signal of a binarization circuit 76 that binarizes the MO signal amplified by the amplifier 75, is input.

When a pulse group exists in the MOZ value signal 2511, the pulse group detection circuit 17 detects the pulse group detection signal 1 for τ seconds.
06 (see FIG. 30(C)) is set to high level. Since the pulse group detection circuit 17 consists of a retrieval full pulse generation circuit l6, in the MO2 value conversion signal 2511,
When the next pulse is input within τ seconds after the previous pulse is input, the pulse group detection signal 106 continues for τ seconds.
is considered to be at a high level.

FIG. 24 shows one example of the structure of the retriggerable pulse generation circuit 16. Here, the retriggerable pulse generation circuit 16
is set up in the one-shot multivibrator 18. The time τ during which the pulse group detection signal 106 is set to high level is set by the resistor R and the capacitor C. Specifically, τ is proportional to RC.

Figure 25 is an example of a configuration in which a shift register 19 is used as the retriggerable pulse generation circuit {6. The serial input terminal IN is set to high level, and the clock input terminal C) [
A clock of frequency fc is input to the shift output terminal m.
Let the Nth output of the recording area detection signal P be the recorded area detection signal P. Also, M
The O2 value signal 2511 is input to the clear terminal CL.

In this case, τ=NX C1/fC).

FIG. 26 shows an example in which an N frequency division counter 20 is used as the retriggerable pulse generation circuit {6. A binary MO signal 2511 is input to the clear terminal CL, and the output from the output terminal m is used as the pulse group detection signal 106. This pulse group detection signal 106 is also input to one input terminal of the AND circuit 21. , the frequency f is applied to the other human input terminal of the AND circuit 21.
The clock of e is inputted, and the output of the AND circuit 21 is inputted to the clock terminal CK of the N-divided counter 20. In this case as well, τ=NX (1/fc).

FIG. 30(a) shows an example of the output signal of the MO signal AGC amplifier 75, and FIG. 30(b) shows an example of the output signal of 2{I! An example of the MO binarized signal 2511 binarized by the conversion circuit 76 is shown in FIG.
An example of the pulse group detection signal 106 generated based on the MO binarized signal 25l1 is shown in FIG.

Here, when one pulse exists in the MOZ digitized signal 2511, the time τ for setting the pulse group detection signal 106 to a high level is the maximum pulse interval T between adjacent pulses in the MOZ digitized signal 106. It is set to be larger than X. As a result, the pulse group detection circuit 17
The pulse group detection signal 106, which is the output of
), a signal approximately equal to the recorded area of the pulse group by the MO signal in the output signal of the MO signal AGC amplifier 75 can be obtained.

Next, a modified example of the pulse group detection circuit will be shown.

In this modification, when a defective pulse as shown by dotted line S or T in FIG. 30(a) exists in the unrecorded area of the pulse group by the MO signal, based on this defective pulse, the ), the pulse group detection signal 106 is erroneously set to high level, as shown by the dotted line U or V, and the MO
This is a measure to prevent errors from occurring in signal reproduction.

That is, the pulse group detection circuit 17 in the modified example is constituted by an appropriate retrigger pull pulse generation circuit 22 and a leading pulse removal circuit 23, as shown in FIG. The leading pulse removal circuit 23 receives the MO2 value conversion signal 2511
This is a circuit for invalidating the output of the retriggerable pulse generation circuit 22 for the first M pulses.

FIG. 28 shows a specific example of the structure of the leading pulse removal circuit 23. Here, an M-ary counter 24 is arranged as a leading pulse removing circuit 23 in the preceding stage of the retrigger pull pulse generating circuit 22, and the leading M pulses in the MO2-valued signal 2511 are removed. Instead of this M-ary counter 24, an M shift register may be used.

FIG. 29 shows another example of the configuration of the leading pulse removal circuit 23. Here, a shift register 25 as the leading pulse removing circuit 23 is arranged after the retriggerable pulse generating circuit 22, and a retriggerable pulse generating circuit 23 is arranged. The output of the circuit 22 is input to the clear terminal CL of the shift register 25, and the MO2 value conversion signal 2511 is input to the clock terminal CK of the shift register 25.
is input, and the M-th shift output QM is used as the pulse group detection signal 106'.

Here, tying control will be explained using an example where M=1, that is, the output of the retriggerable pulse generation circuit 22 is disabled for only the first pulse in the MO2-valued signal 2511. I do.

As shown in FIG. 30(a), if the number of defective pulses in the unrecorded area of the MO signal is only one pulse, this defective pulse is invalidated by the leading pulse removal circuit 23. ), the tweet pulse group detection signal 106' is never set to high level based on the defect pulse.

In addition, in the area where the pulse group by the MO signal has been recorded,
The timing at which the pulse group detection signal becomes high level is 1.
Although there will be a delay by a pulse, for example, a delay of several pulses will not have any adverse effect on the hold timing of the AGC voltage. Therefore, the reliability of the AGC operation does not deteriorate.

Note that in the above embodiment, the AGC voltages of both AGC amplifiers 65 and 75 are held at the time of access.
As described above, when the access speed is relatively low, it is not necessarily necessary to hold the AGC voltage.

Further, in the above embodiment, the preformat section 30
03 and the MO section 3002, however, only one type of reproduction signal may be originally used.

Further, in the above embodiments, the magneto-optical disk 1201 is used as an example of an optical memory, but it is also possible to use a phase-change optical disk on which information can be rewritten or on which desired information can be recorded only once. The present invention can also be applied to an automatic gain control device for an optical memory device that performs recording or reproduction on a write-once optical disc or the like.

〔Effect of the invention〕

As described above, the automatic gain control device for an optical memory device according to the first aspect of the present invention records information in an optical memory.
In an automatic gain control device for an optical memory device, which is provided in an optical memory device that performs erasing or reproduction, and which adjusts the degree of amplification based on a control voltage generated according to the amplitude of a reproduction signal, the above control voltage is applied during recording or erasing. The structure includes an i-th control means for holding the i-th control means.

As a result, since the control voltage is held during recording or erasing, the amplification degree of the automatic gain control device is maintained at the value before recording or erasing is started during recording or erasing. Therefore, the degree of amplification at the start of playback immediately after the end of recording or erasing is the same as the degree of amplification at the end of the previous playback, so the playback signal is amplified at an approximately appropriate amplification degree even during playback immediately after the end of recording or erasing. You will be able to do this. Therefore, it is possible to reduce reproduction errors immediately after recording or erasing ends.

By the way, in the unrecorded area of the optical memory, the amplitude of the reproduced signal is at a low level, so if there are continuous unrecorded areas, the amplification degree of the automatic gain control device gradually increases to near the maximum value. In that case, when the signal passes through the unrecorded area and reaches the recorded area, the amplification degree remains at an excessive level, making it difficult to perform normal reproduction.

Therefore, the first Ll. In I, a recorded area determining means for determining a recorded area of information during reproduction;
If a second control means is added to hold the control voltage in the unrecorded area based on the judgment of the recorded area determination means, when passing through the unrecorded area, the amplification degree will be the same as that of the previous recording. Since the amplification level at the time of reproduction of the recorded area is maintained, the reproduced signal can be amplified at a substantially appropriate amplification level even immediately after reaching the recorded area.

Furthermore, in the first aspect of the present invention, if a response speed changing means for changing the response speed in multiple stages is provided, for example,
By increasing the response speed of the auto gain control device when detecting the control voltage of the auto gain control device (corresponding to the AGC voltage mentioned above) such as during the test write described above, it is possible to This makes it possible to respond to changes in the amplitude of the reproduced signal. On the other hand, when reproducing normal information, by setting the response speed relatively low, it is possible to reduce the influence of defective pulses and the like, thereby reducing reproduction errors.

Further, the automatic gain control device for an optical memory device according to the second aspect of the present invention is capable of recording, erasing, or reproducing information in an optical memory that has a preformat section in which addresses and the like are recorded in advance and a data section in which arbitrary data can be recorded. In an automatic gain control device for an optical memory device, which is provided in an optical memory device that performs A first auto gain control section that adjusts the gain, and a second auto gain control section that adjusts the gain of the reproduction signal reproduced from the data section, and only the second auto gain control section A recorded area determining means for determining an area where information has been recorded during reproduction, and a holding means for holding the control voltage in an area where information is not recorded based on the determination by the recorded area determining means. It is.

In this way, in the second aspect, when the optical memory is divided into a preformat section and a data section, the data section usually has a recorded area and an unrecorded area, but the preformat section always has a recorded area and an unrecorded area. Since information such as addresses is recorded, playback is normally performed from the preformat section, considering that there is no need to judge recorded areas and unrecorded areas and to hold the auto gain control device. A first auto gain control section that adjusts the amplification degree of the reproduced signal and a second auto gain control section that adjusts the amplification degree of the reproduction signal reproduced from the data section are provided, and only the second auto gain control section is provided. The apparatus is further provided with a recorded area determining means for determining an area in which information has been recorded during reproduction, and a holding means for holding the control voltage in an area where information is not recorded based on the determination by the recorded area determining means. As a result, the recorded area determining means and holding means are not required in the first auto gain control section for the preformat section, which simplifies the structure of the first auto gain control section for the preformat section. be able to.

[Brief explanation of drawings]

1 to 32 and 39 to 45 show an embodiment of the present invention. FIG. 1 is a flowchart showing the procedure for holding control of the AGC voltage in the AGC amplifier. Figure 2 shows the AG in the preformat AGC amplifier.
FIG. 3 is an explanatory diagram showing a logic circuit that performs hold control of the C voltage. FIG. 3 is an explanatory diagram showing a logic circuit that performs hold control of the AGC voltage in the MO signal AGC amplifier. FIG. 4 is a circuit diagram showing a preformat AGC amplifier. FIG. 5 is a circuit diagram showing an AGC amplifier for MO signals. FIG. 6 is a circuit diagram showing a response speed changing/resetting circuit. FIG. 7(a) is a block diagram showing a preformat waveform processing section. FIG. 5B is a block diagram showing the MO waveform processing section. FIG. 8 is an explanatory diagram showing the relationship among the reproduction signal, VCA output signal, AGC voltage, etc. FIG. 9 is an explanatory diagram showing a schematic structure of a magneto-optical disk device. FIG. 10 is a block diagram showing the recording circuit. FIG. 11 is a block diagram showing the reproducing circuit. FIG. 12 is a block diagram showing the main parts of the controller. FIG. 13 is a block diagram showing a semiconductor laser drive circuit. FIG. 14 is an explanatory diagram showing switching timing during recording of high frequency superimposed switch signals, etc. FIG. 15 is an explanatory diagram showing switching timing during reproduction of a high frequency superimposed switch signal, etc. FIG. 16 is a block diagram showing the timing generation circuit. FIG. 17 is a block diagram showing the structure of a sector mark detection circuit. FIG. 18 is an explanatory diagram showing the sector mark detection procedure. FIG. 19 is an explanatory diagram showing waveforms of various parts in the timing generation circuit. FIG. 20 is a block diagram showing the structure of the signal processing circuit. FIG. 2l is an explanatory diagram showing waveforms of each part in the signal processing circuit. FIG. 22 is an explanatory diagram showing the relationship between marks, non-marks, and reproduced signals. FIG. 23 is an explanatory diagram showing a general configuration of a pulse group detection circuit. FIGS. 24 to 26 are explanatory diagrams showing specific examples of the pulse group detection circuit, respectively. FIG. 27 is an explanatory diagram showing another main structure of the pulse group detection circuit. FIGS. 28 and 29 are explanatory diagrams showing specific examples of the pulse group detection circuit corresponding to FIG. 27, respectively. FIG. 30 is an explanatory diagram showing the relationship between various signals and recorded areas and unrecorded areas. FIG. 31 is a block diagram showing the main parts of the controller. FIG. 32 is a block diagram showing the modulation circuit. FIG. 39 is an explanatory diagram showing the relationship between mark size and recording light amount. FIG. 40 is an explanatory diagram showing the relationship between mark size and recording pulse length. FIG. 41 is an explanatory diagram showing the relationship between the size of a mark and the amplitude of a reproduced signal. FIG. 42 is an explanatory diagram showing the test write procedure. FIG. 43 is a graph showing the relationship between the AGC voltage and the amplification degree. FIG. 44 is a graph showing the relationship between the P-P value of the signal amplitude and the AGC voltage. FIG. 45 is a graph showing the relationship between mark length and various characteristics. 33 to 38 and 46 to 48 show conventional examples. FIG. 33 is an explanation U'J showing the recording operation in the magneto-optical disk device. It is 1. FIG. 34 is an explanatory diagram showing the reproducing operation in the magneto-optical disk device. FIG. 35 is a schematic plan view of the magneto-optical disk. FIG. 36 is an enlarged view of the main part of FIG. 35. FIG. 37 is an explanatory diagram showing the reproduction processing system. FIG. 38(a) is an explanatory diagram showing the relationship between the polarities of two reproduced signals in the MO section. FIG. 38(b) is an explanatory diagram showing the relationship between the polarities of two reproduced signals in the preformat section. FIG. 46 is an explanatory diagram showing the relationship between reproduction signals, VCA output signals, etc. FIG. 47 is a perspective explanatory view showing the access operation. FIG. 48 is an explanatory diagram showing reproduction signal waveforms at the time of access and at the time of reproduction. l7 is a pulse group detection circuit (recorded area detection means), 65
75 is the AGC amplifier for preformat (first auto gain control section), and the AGC amplifier for MO signal (
91 is an inverter (first control means), 93 is a hold circuit (second control means or hold means), 101 is a response speed change/reset circuit (response speed change means), 1201 is a magneto-optical disk (optical memory), 3002 is an MO section (data section), 3
003 is a preformat section.

Claims (1)

[Claims] 1. An automatic optical memory device that is provided in an optical memory device that performs recording, erasing, or reproduction in an optical memory, and that adjusts the amplification degree based on a control voltage generated in accordance with the amplitude of a reproduction signal. An automatic gain control device for an optical memory device, characterized in that the gain control device includes a first control means for holding the control voltage during recording or erasing. 2. Recorded area determining means for determining an area where information has been recorded during reproduction; and second control means for holding the control voltage in an area where information is not recorded based on the determination by the recorded area determining means. 2. The automatic gain control device for an optical memory device according to claim 1, further comprising: an automatic gain control device for an optical memory device. 3. The auto gain control for an optical memory device according to claim 1 or 2, further comprising a response speed changing means for changing the response speed of the auto gain control device in multiple stages. Device. 4. Provided in an optical memory device for recording, erasing, or reproducing an optical memory having a preformat section in which addresses etc. are recorded in advance and a data section in which arbitrary data can be recorded,
Based on the control voltage generated according to the amplitude of the reproduced signal,
An automatic gain control device for an optical memory device that adjusts the degree of amplification, comprising: a first automatic gain control section that adjusts the gain of a reproduced signal reproduced from the preformat section; and a reproduction signal reproduced from the data section. a second auto gain control section that adjusts the gain of the second auto gain control section, and a recorded area determination means that determines an area in which information has been recorded during reproduction only in the second auto gain control section; An automatic gain control device for an optical memory device, further comprising a hold means for holding the control voltage in an area where information is not recorded based on a determination by the means.