JP2589824B2 - Automatic gain control device for optical memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control device provided in an optical memory device for recording, erasing or reproducing data in an optical memory and adjusting a gain according to the amplitude of a reproduced signal. It is.

[Conventional technology]

A conventional optical memory device will be described below with reference to a magneto-optical memory device that performs recording, erasing, and reproducing on a magneto-optical disk.

As shown in FIG. 33 (a), the magneto-optical disk is formed by forming a recording magnetic film 2805 on a disk substrate 2804. The recording magnetic film 2805 is formed so that the axis of easy magnetization is perpendicular to the film surface.
The direction of the magnetization indicated by the arrow in a predetermined direction (for example,
It is initialized so as to have the magnetization direction A) in FIG.

At the time of recording, a laser beam 2803 emitted from a semiconductor laser 2801 is condensed by an objective lens 2802 to a diameter of about 1 μm, and irradiates a recording magnetic film 2805. At this time, the intensity of the laser beam 2803 is controlled based on a recording signal 2807 (see FIG. 13B) corresponding to information to be recorded. The temperature of the part irradiated with the laser beam 2803 having high light intensity locally rises and exceeds the Curie temperature, and the coercive force of that part is significantly reduced. As a result, the direction of the magnetization at the portion where the coercive force is reduced is reversed to the same direction as the externally applied magnetic field 2806 applied simultaneously with the irradiation of the laser beam 2803 (the direction B of the magnetization in the figure). In this way, the recording signal
Information corresponding to 2807 is recorded on the recording magnetic film 2805. Hereinafter, a portion where the magnetization in the direction B is recorded as described above is referred to as a mark 2809, and a portion where the magnetization in the direction A is not recorded is referred to as a non-mark 2810.

Erasing of information recorded on the recording magnetic film 2805 is performed in the same manner as in recording by reversing the direction of the externally applied magnetic field 2806 from the direction of recording, and the direction of magnetization is changed to the original initialization direction (that is, FIG. It is executed by returning to the magnetization direction A) in the middle. As a result, the erased portion becomes a non-mark 2810.

In this example, an optical modulation method in which the laser beam 2803 is modulated according to the recording signal 2807 and recording is performed by applying an externally applied magnetic field 2806 having a constant intensity has been described. Alternatively, recording may be performed by a magnetic field modulation method in which recording is performed by modulating the direction of the externally applied magnetic field 2806 in accordance with the recording signal 2807 while keeping the constant.

The disk substrate 2804 is made of glass, plastic, or the like. As shown in FIG. 33 (a), address information indicating the address of a track or a sector has physical unevenness 28 in advance.
It is formed by engraving as 08.

Since the above address information is previously engraved in a fixed format, after that, recording and erasing operations cannot be performed. The portion engraved in advance as the physical unevenness 2808 is hereinafter referred to as a preformat unit 3003. On the other hand, each operation of recording and erasing of information is performed in a part other than the preformat unit 3003, and this part is referred to as an MO (magneto-optical) unit 3002.

Normally, the preformat unit 3003 and the MO unit 3002
As shown in the figure, they are alternately arranged on spiral or concentric tracks 3005. And the pre-format section
The 3003 and the MO unit 3002 constitute one sector 3004 as a pair. The magneto-optical disk 3001 has a large number of sectors 3004 each having address (address) information on a track 3005.
Each operation of recording, reproducing, and erasing information is performed for each sector 3004 unit.

In addition, as shown in FIG. 36, in the preformat portion 3003 on the track 3005, either the concave portion or the convex portion of the unevenness 2808 in FIG. 33 constitutes the mark 2811 and the other of the concave portion or the convex portion Constitute the non-mark 2812. Further, as described above, the mark 2809 by the MO (magneto-optical) signal and the non-mark 2910 therebetween are recorded in the MO section 3002.

Next, at the time of reproduction of the magneto-optical disk 3001, the light is emitted from the semiconductor laser 2801 as shown in FIG.
The laser beam 2803 condensed by the objective lens 2802 to a diameter of about 1 μm is irradiated on the recording magnetic film 2805. However, the laser beam 2803 is linearly polarized, and the light intensity of the laser beam 2803 is weaker than in each of the recording and erasing operations. The reflected light of the linearly polarized laser beam 2803 from the magneto-optical disk 3001 rotates its polarization plane due to the Faraday effect or the Kerr effect when passing or reflecting through the recording magnetic film 2805. The rotation direction of the mark 2809 and the rotation of the non-mark 2810 are opposite to each other. Reproduction is performed by detecting the difference in the polarization direction. As a result, for example, two types of reproduced signals S1 and S2 as shown in FIGS.

Next, the reproduction optical system for obtaining the reproduction signals S1 and S2 will be briefly described. As shown in FIG. 37, the reflected light 3201 from the magneto-optical disk 3001 is incident on a PBS (analyzer) 3202. The two detection lights 3210 and 3211 are guided to two photodetectors 3203 and 3204 for each polarization direction. And
The light detectors 3203 and 3204 convert the electric signals into electric signals that change according to the light intensity, and output the electric signals as reproduction signals S1 and S2.

As will be described in detail later, the pre-format unit 3003 and the MO unit
3002 signals can be separated and obtained.
Since the mark 2809 and the non-mark 2810 can be read separately from the signal, the information recorded on the recording magnetic film 2805 can be reproduced.

As shown in FIG. 38 (a), when the reflected light vector from the non-mark 2810 (magnetization direction A) in the MO unit 3002 is α, and the reflected light vector from the mark 2809 (magnetization direction B) is β, α and β are reflected light vectors rotated in opposite directions by the rotation angle of the polarization plane. Reflected light vector α,
β is the two polarization directions X in the analyzer (PBS) 3202,
Each is detected to Y. The two polarization directions X and Y are perpendicular to each other. Detected light vectors α _X , β by projecting the reflected light vectors α, β in the polarization directions X, Y, respectively
The magnitude of _Y corresponds to the reproduction signal S1 and the reproduction signal S2. Further, the detection light vectors α _X and β _Y correspond to the detection lights 3210 and 3211 in FIG. 37, respectively.

As is clear from FIG. 38 (a), the reproduction signal S1 has a high level corresponding to the non-mark 2810 and a low level corresponding to the mark 2809. On the other hand, the reproduction signal S2 is non-mark
The low level corresponds to 2810, the high level corresponds to the mark 2809, and has a polarity opposite to that of the reproduced signal S1. Then, the reproduction signals S1 and S2 are input to a differential amplifier in order to improve the S / N ratio, and are differentially amplified to reproduce information.

Next, based on FIG.
The reproduced signals S1 and S2 reproduced from 03 will be described. Since the recording / erasing operations are not performed in the preformat unit 3003, the magnetization direction is only A. Preformat section 30
In 03, marks 2811 and non-marks 2812 consisting of irregularities 2808
Causes diffraction of the laser beam. Therefore,
As shown in FIG. 38 (b), the reflected light vector has a long reflected light vector α (corresponding to reproduction of non-mark 2812) and a short reflected light vector γ (mark 2811
Corresponding to playback).

When this is projected on the polarization directions X and Y of an analyzer (PBS) 3202, analyzer vectors α _X and γ _Y are obtained, respectively. The magnitudes of the analyzer vectors α _X and γ _Y correspond to the reproduced signals S1 and S2. Both the reproduction signals S1 and S2 correspond to the high level for the non-mark 2812 due to the unevenness 2808 and the low level for the mark 2811. Therefore, the reproduction signal S1
S2 is the mark 2809 of magneto-optical recording shown in FIG.
Unlike the case of the non-mark 2810, the polarity is the same.

That is, as shown in FIGS. 34 (b) and (c), the reproduced signal S1
S2 has the same polarity in the preformat unit 3003, and is a signal whose polarity is inverted in the MO unit 3002. Therefore, if the reproduction signals S1 and S2 are added, only the signal of the preformat unit 3003 can be obtained, and only the signal of the MO unit 3002 can be obtained by differentially reproducing the reproduction signals S1 and S2. And the S / N ratio can be improved.

A differential signal or an addition signal based on the two types of reproduced signals S1 and S2 is an auto gain control amplifier (hereinafter, AGC).
It is conceivable to perform amplification while adjusting the degree of amplification so that the amplitude after amplification is substantially constant. The AGC amplifier is, for example, a voltage control amplifier,
An AGC voltage generator for generating a control voltage (hereinafter, referred to as an AGC voltage) for adjusting the amplification of the voltage control amplifier so that the amplitude of the output signal of the voltage control amplifier becomes substantially a predetermined level can be provided.

[Problems to be solved by the invention]

However, in the above-described magneto-optical memory device, immediately after the recording or erasing operation, the amplification of the AGC amplifier becomes excessively small, and the reproduction may not be performed properly.

That is, in FIG. 46, the sector indicated by A in FIG.
In 3004, while playing the preformat section 3003
Recording is performed on the MO unit 3002, reproduction is performed on the sector 3004 indicated by B, and pre-formatting unit 3003 is performed on the sector 3004 indicated by C.
And the information recorded in the MO unit 3002 is deleted.

In that case, in the sector 3004 of A, the semiconductor laser 2801
Since the light quantity in FIG. 33 rises to a high level corresponding to the above-mentioned recording light quantity, as shown in FIG.
The amplitude of the reproduction signals S1 and S2 (here, the signal based on the reflected light of the laser beam 2803 for recording (FIG. 27) reflected by the magneto-optical disk 3001) in the unit 3002 becomes extremely large. As a result, as shown in FIG. 3D, the AGC voltage starts to increase, and accordingly, the amplification degree of the voltage control amplifier starts to decrease. As shown in FIG. Levels gradually decrease.

However, after that, it comes to the sector 3004 indicated by B and further to C, and the preformat portion of the sector 3004 of BC
When performing 3002 regeneration, since the amplification degree of the voltage controlled amplifier remains decreased, the amplitude of the reproduced signal of the pre-format section 3002 after being amplified by a voltage controlled amplifier, as shown by B ₁ or C ₁ is It becomes extremely small and a reproduction error may occur.

Similarly, when erasing data in the sector 3004 indicated by C, the light amount of the semiconductor laser 2801 becomes larger than that during reproduction.
As shown in FIG. 13B, the amplitude of the reproduced signals S1 and S2 (here, the signal based on the reflected light of the erasing laser beam 2803 reflected by the magneto-optical disk 3001) increases, and as a result, the voltage control since the amplification degree of the amplifier is lowered, reduces the output signal level of the still voltage controlled amplifier during reproduction of the preformat portion 3002 of the sector 3004 shown by D (see _part D), it can not be performed accurately reproduced.

In the magneto-optical memory device, at the time of access, as described above, as shown in FIG. 47, a laser beam 2803 is provided with a track 3005 or a preformat unit 3003 provided in the form of a guide groove provided in a disk substrate 2804. Disk substrate indicated by arrow P or Q while traversing unevenness 2808 in
It moves in the radial direction of 2804. As a result, the amount of reflected light differs between the track 3005 and other portions of the portion of the unevenness 2808, so that the reproduction signal S1 shown in the portion A in FIG.
Or S2 is obtained. On the other hand, the reproduction signal S1 or S2 at the time of reproducing the information is as shown in the B section in FIG.

Thus, at the time of access, the amplitude of the reproduction signal S1 or S2 becomes larger or smaller than at the time of reproducing information. This depends on the depth and width of the guide groove. Therefore, the amplification degree of the AGC amplifier decreases or increases accordingly. As a result, a reproduction error may occur when reproducing information immediately after access. When the access speed is relatively low, a high-pass filter is provided in the processing system of the reproduced signal S1 or S2 to remove a vibration component caused by the track 3005 or the unevenness 2808 as shown in the part A of FIG. Therefore, a reproduction error immediately after access is less likely to occur, but it is usually preferable to make the access as fast as possible, so that a reproduction error due to a decrease or increase in the amplification degree of the AGC amplifier immediately after access is difficult to avoid. Things.

The above-described reproduction error immediately after recording / erasing or access can be reduced by increasing the response speed of the AGC amplifier to a change in the amplitude of the input signal. In the test write as described above, it is necessary to make the AGC voltage ((d)) follow the change in the amplitude of the MO signal (FIG. 42 (c)) in sector units. It is necessary to increase the response speed of the AGC amplifier as much as possible in order to implement it effectively.

However, when the response speed of the AGC amplifier is increased, for example, when a defect pulse occurs due to a damaged portion or dust on the magneto-optical disk 3001, the AGC amplifier
Since the amplification is immediately reduced by the amplifier in response to the defect pulse, a reproduction error is also likely to occur. The reason why the response speed of the AGC amplifier is originally set lower is to reduce the reproduction error caused by the defect pulse as described above.

As described above, when the response speed of the AGC amplifier is set to be lower or higher, a reproduction error is likely to occur for different reasons. Basically, it is preferable to set the response speed of the AGC amplifier low to reduce the influence of the defect pulse.
A reproduction error due to a response delay of the AGC amplifier cannot be avoided.

[Means for solving the problem]

An automatic gain control device for an optical memory device according to a first aspect of the present invention has the following features.
An automatic gain control device of an optical memory device provided in an optical memory device that performs recording, erasing, or reproducing on an optical memory and that controls an amplification degree based on a control voltage generated according to the amplitude of a reproduced signal. First control means for holding the control voltage at a time, a recorded area determination means for determining a recorded area of information during reproduction,
A second control means for holding the control voltage in an unrecorded area of information based on the determination by the recorded area determination means, wherein the first control means gives priority to the control by the second control means. It is characterized in that a voltage is held.

It is preferable that the automatic gain control device further includes a response speed changing unit that changes the response speed of the automatic gain control device in multiple stages.

Further, the automatic gain control device for an optical memory device according to the second aspect of the present invention provides a method for recording, erasing or reproducing data in an optical memory having a preformat portion in which addresses and the like are recorded in advance and a data portion in which arbitrary data can be recorded. Provided in an optical memory device for performing, based on a control voltage generated according to the amplitude of the reproduction signal, in the automatic gain control device of the optical memory device to adjust the gain,
A first auto gain control unit that adjusts a gain of a reproduction signal reproduced from the preformat unit; and a second auto gain control unit that adjusts a gain of a reproduction signal reproduced from the data unit; A recorded area determining means for determining a recorded area of information only in the second auto gain control section at the time of reproduction, and holding the control voltage in an unrecorded area of information based on the determination of the recorded area determining means. And holding means for performing the operation.

It is preferable that the automatic gain control device further includes a response speed changing unit that changes the response speed of the first auto gain control unit in multiple stages.

(Operation)

Since the automatic gain control device of the optical memory device according to the first aspect of the present invention holds the control voltage at the time of recording or erasing, the amplification degree of the auto gain control device at the time of recording or erasing starts recording or erasing. It will be kept at the previous value. Therefore,
Since the amplification at the start of reproduction immediately after the end of recording or erasure is the same as the amplification at the end of the previous reproduction, the reproduction signal can be amplified with an almost appropriate amplification even at the time of reproduction immediately after the end of recording or erasure. Become like This makes it possible to reduce a reproduction error immediately after the end of recording or erasing.

By the way, in an unrecorded area of information in the optical memory,
Since the amplitude of the reproduction signal becomes low, the amplification of the automatic gain control device increases to near the maximum value. In this case, when passing through an unrecorded area and approaching a recorded area, the amplification degree remains at an excessive level, so that normal reproduction becomes difficult. Therefore,
If a recorded area and an unrecorded area of information are determined at the time of reproduction, and the control voltage is held in the unrecorded area of the information, the amplification degree becomes equal to that of the previous recording when passing through the unrecorded area. Is maintained at the amplification level at the time of reproduction of the
Next, it becomes possible to amplify the reproduction signal with an almost appropriate amplification degree immediately after the recording signal reaches the recorded area.

Further, in the first aspect of the present invention, if a response speed changing means for changing the response speed in multiple stages is provided, for example, the control voltage (eg, the above-described AGC (Equivalent to a voltage), by increasing the response speed of the auto gain control device, and by not holding the control voltage during that time, for example, to reduce the amplitude of the reproduced signal at minute intervals, such as in sector units. Be able to respond to changes. On the other hand, when normal information is reproduced, by setting a low response speed, the influence of a defect pulse or the like can be reduced to reduce a reproduction error.

As described above, the optical memory may be divided into a preformat section and a data section, and an address or the like may be recorded in the preformat section in advance, while arbitrary data may be recorded in the data section. By the way, when the control voltage of the auto gain control device is held in the unrecorded area by determining the recorded area and the unrecorded area of the information as described above, the data area usually includes a recorded area and an unrecorded area. However, information such as an address is always recorded in the preformat portion. Therefore, in the preformat section, it is usually unnecessary to determine the recorded area and the unrecorded area and to hold the auto gain control device.

Therefore, as in the above-described second aspect, the first mode for adjusting the amplification degree of the reproduction signal reproduced from the preformat unit is used.
And a second auto gain control section for adjusting the amplification degree of a reproduction signal reproduced from the data section. Only the second auto gain control section is provided with an area in which information is recorded during reproduction. By providing a recorded area determining means for determining and a holding means for holding the control voltage in an unrecorded area of information based on the determination of the recorded area determining means, the first auto format for the pre-format section can be provided. Since the recorded area determination means and the hold means are not required in the gain control section, the configuration of the first auto gain control section for the preformat section can be simplified.

Further, in the second aspect of the present invention, if a response speed changing means for changing the response speed of the first auto gain control unit in multiple stages is provided, for example, the automatic gain control as in the above-described test write is performed. At the time of detecting the control voltage of the apparatus (corresponding to the above-mentioned AGC voltage) or the like, the response speed of the first auto gain control unit is increased to change the amplitude of the reproduced signal at minute intervals, for example, in sector units. Will be able to respond. On the other hand, when normal information is reproduced, by setting a low response speed, the influence of a defect pulse or the like can be reduced to reduce a reproduction error.

〔Example〕

One embodiment of the present invention will be described below with reference to FIGS. 1 to 32.

First, a configuration of a magneto-optical disk device for recording, reproducing, and erasing data on a magneto-optical disk 1201 as an example of an optical memory will be described.

As shown in FIG. 9, the magneto-optical disk 1201 is driven to rotate by a spindle motor 1202, and information is recorded / reproduced / erased by a laser beam 1204 emitted from an optical head 1203. At the time of recording or erasing, an external magnetic field is applied from the external magnetic field applying magnet 1205 simultaneously with the irradiation of the laser beam 1204. The direction of the external magnetic field during recording and erasing can be reversed, for example, by rotating the external magnetic field applying magnet 1205 by a motor (not shown) or the like. Further, an external magnetic field for recording / erasing may be obtained by using the external magnetic field applying magnet 1205 as an electromagnet.

At the time of recording, the semiconductor laser 2801 (the
FIG. 10) shows the driving current of the semiconductor laser from the recording circuit 1206.
1210 is input. The light intensity of the semiconductor laser 2801 is appropriately controlled by the semiconductor laser drive current 1210.

At the time of reproduction, the reproduction signal 1211 (two types of reproduction signals S1 as shown in FIG. 34) is sent from the optical head 1203 to the reproduction circuit 1207.
・ Consisting of S2) is output. The reproduction data 1212 reproduced by the reproduction circuit 1207 is sent to the controller 1208.

In the controller 1208, various control signals 1213 are timed based on the reproduction data 1212, and these control signals 1213 are sent to the recording circuit 1206 and the reproduction circuit 1207. Also, the magnetic field control signal from the controller 1208
1214 is transmitted to the external magnetic field applying magnet 1205, and the direction of the external magnetic field is controlled.

As shown in FIG. 10, the recording circuit 1206 is a modulation circuit 13
02, and the recording data 1311 sent from the controller 1208 (FIG. 9) is input to the modulation circuit 1302. In the modulation circuit 1302, the recording data 1311
Modulated data 1310 according to recording format by 1213
Is converted to This modulation is performed according to, for example, a 2,7 modulation method described later.

The modulation data 1310 is transmitted to the semiconductor laser drive circuit 1301, and based on the modulated data 1310, the semiconductor laser drive current 1210 is output from the semiconductor laser drive circuit 1301, and the optical head 203
Is transmitted to the semiconductor laser 2801 inside. At the same time, the control signal 1213 from the controller 1208 is input to the semiconductor laser drive circuit 1301, and the light intensity of the semiconductor laser 2801 is appropriately controlled according to the recording, reproducing, and erasing operations.

As shown in FIG. 11, the reproduction circuit 1207 includes a signal processing circuit 1401, and reproduction signals 1211 (reproduction signals S1 and S2) from the optical head 203 (FIG. 9) are input to the signal processing circuit 1401. , Where synchronization takes place. From the signal processing circuit 1401, synchronous data 1410 is sent to the demodulation circuit 1402, and at the same time, the sector mark signal 1411 is sent to the controller 1208.
The demodulation of the synchronization data 1410 is realized by performing a conversion reverse to that of the modulation circuit 1302 in FIG. Signal processing circuit 14
Various control signals 1213 are transmitted from the controller 1208 to the 01 and the demodulation circuit 1402. Demodulated reproduction data 1212 is output from the demodulation circuit 1402 to the controller 1208.

As shown in FIG. 12, the controller 1208 includes a timing generation circuit 1501. Signal processing circuit 1401 (No.
The sector mark signal 1411 from FIG. 11) is input to the timing generation circuit 1501, where the reference timing signal 1510 is generated at the timing of the sector unit and the control circuit 15
Transmitted to 02. Also, the reproduction data 1212 from the demodulation circuit 1402 (FIG. 11) is input to the control circuit 1502. The control circuit 1502 generates various control signals 1213 from the two types of input signals, and inputs and outputs information to and from an external device.

The modulation circuit 1302 in FIG. 10 performs modulation based on, for example, the modulation schemes shown in Table 1. This is the so-called 2,7
The input data (recording information) shown in the left column of Table 1 is converted into predetermined modulation data shown in the right column of FIG. The number of bits is set to be 2 to 7 bits. Then, for example, according to the sector format shown in FIG.
1310 is output to the semiconductor laser drive circuit 1301 in FIG.

In FIG. 14 (a), the pre-format unit 3003
Sector mark section 1701 for obtaining synchronization timing in sector units, and ID section including sector address (address) information
1702. As shown in FIG. 33, these are engraved on the magneto-optical disk 1201 by physical irregularities 2808 corresponding to marks 2811 and non-marks 2812 that cannot be recorded / erased.

The MO section 3002 as a data section includes a normal use range 1703 for recording, reproducing, and erasing information data, and a pair of gap sections 1704 and 1705 positioned before and after the normal use range. Then, the modulation data 1310 is recorded in the normal use range 1703. At this time, the recording is performed on the mark 2809 and the non-mark 2810 by the MO signal as shown in FIG. 33 or FIG.

The gaps 1704 and 1705 arranged between the preformat unit 3003 and the MO unit 3002 have a normal use range 17.
03 is a margin area for recording information. In other words, these gap portions 1704 and 1705 shift the recording start position and the recording end position back and forth due to a phase error or the like generated between the rotation of the spindle motor 1202 and the synchronization timing of the sector 3004. This is the expected area.

As shown in FIG. 13, the semiconductor laser drive circuit 1301
Has a recording / erasing light amount control circuit 1803, to which modulation data 1310 is input from a modulation circuit 1302 (FIG. 10) to a semiconductor laser driving circuit 1301. .

A reproduction light amount control signal 1810 is input from a controller 1208 (FIG. 9) to a reproduction light amount control circuit 1801 so that the reproduction light amount of the semiconductor laser 2801 in the optical head 1203 is appropriately controlled during reproduction.

Recording / erasing light amount control signal 1811 from controller 1208
Is input to the recording / erasing light amount control circuit 1803,
The light amount of the semiconductor laser 2801 corresponding to the erasing is controlled. Further, the high-frequency superposition switch signal 1812 from the controller 1208 is input to the high-frequency superposition circuit 1802, and based on this, an output signal 1816 that is turned on and off at high frequency is generated by the high-frequency superposition circuit 1802, and the adder 18
By superimposing on the output signal 1814 of the reproduction light amount control circuit 1801 at 05, the noise of the semiconductor laser 2801 caused by the return light from the magneto-optical disk 1201 is reduced. Note that the output signal 18 of the high-frequency superposition circuit 1802 is
16 is output to the addition circuit 1805 only during reproduction.

Reproduction light quantity control circuit 1801, recording / erasing light quantity control circuit 1803
And each output signal 1814 to 1816 of the high frequency superposition circuit 1802 is
The addition is performed by the addition circuit 1805, and the semiconductor laser drive current 1210 is input to the semiconductor laser 2801. The light amount (light intensity) of the semiconductor laser 2801 is converted by a photodetector 1806 in an optical head 1203 into an electric signal that changes according to the light intensity, and a light amount monitor signal 1813 is sent to a controller 1208 via a light amount monitor circuit 1804. It is to be transmitted. In the controller 1208, the reproduction light amount control signal 1810, the recording / erasing light amount control light amount
11 and a high frequency superposition switch signal 1812 are output. That is, the light intensity (light amount) of the semiconductor laser 2801 is controlled so as to be appropriate between the time of reproduction and the time of recording / erasing.

Next, the operations of recording and erasing information will be described.
As shown in FIG.
Becomes low level (“0”) in the normal use range 1703 (see FIG. 17A), and becomes high level (“1”) in other parts. That is, the normal use range 1703 in the MO unit 3002
, The high-frequency superposition by the high-frequency superposition circuit 1802 is turned off, and is turned on outside the normal use range 1703. Accordingly, the modulated data 1310 is recorded as an MO signal in the normal use range 1703 as shown in FIG.

At this time, as shown in FIG.
The light intensity level (light intensity) 1910 of the normal use range 1703 is high, and otherwise is low. That is, the sector synchronization timing is detected from the sector mark section 1701 in the pre-format section 3003, the address (address) information and the like are read from the ID section 1702, and the information is read from the MO section 3002 while confirming the predetermined address (address). Is recorded / erased.

On the other hand, at the time of reproducing the information recorded in the normal use range 1703, as shown in FIG.
The high-frequency superposition switch signal 1812 is at a high level (“1”) in both the 03 and the MO section 3002. Further, since no recording is performed, the modulated data 1310 as shown in FIG.
Is low level (“0”). Further, as shown in FIG. 11D, the light amount level 1910 is a low level. That is, the synchronization timing of the sector 3004 is detected from the sector mark portion 1701 in the pre-format portion 3003 (FIG.
The address (address) information and the like are read out from the 1702, and while the predetermined address (address) is sequentially confirmed, the MO
Information recorded as a signal is reproduced.

More specifically, as shown in FIG. 16, a timing generation circuit 1501 shown in FIG. 12 is a signal processing circuit 1401 (FIG. 11).
And a sector mark detection circuit 2101 to which a sector mark signal 1411 output from is input. The sector mark detection circuit 2101 detects the presence or absence of a sector mark, and outputs a sector mark detection signal 2110 based on the detection. The sector mark detection signal 2110 is transmitted to the counter 2102, the timer circuit 2104, and the determination circuit 2106.

The output signal 2111 of the counter 2102 and the timer circuit 2104
2112 is input to the switch circuit 2103, and one of the output signals 2111, 2112 is selected by the switch circuit 2103 and output as the reference timing signal 1510.

The reference timing signal 1510 is supplied to the data
07 is also input, and based on this, a data part determination signal 2116 described later is output. Another output signal 2113 is transmitted from the timer circuit 2104 to the window generation circuit 2105.
The output signal 2114 of the window generation circuit 2105 is
Entered in 06.

The determination circuit 2106 outputs a timing determination signal 2115 (described later) from the output signal 2114 and the sector mark detection signal 2110. The switch circuit 2103 selects one of the output signal 2111 of the counter 2102 and the output signal 2112 of the timer circuit 2104 according to the timing determination signal 2115. The reference timing signal 1510, the data part determination signal 2116 and the timing determination signal 2115 are respectively
(Figure 12). The control circuit 1502 controls various signals output from the timing generation circuit 1501.
Based on 1510, 2115, and 2116 and the reproduction data 1212, the various control signals 1213 described above are sent to the recording circuit 1206 and the reproduction circuit 1212.
07 (FIG. 9) to control the recording, reproduction and erasure of information.

As shown in FIG. 17, the sector mark detection circuit 2101
Includes a counter circuit 2201 and a signal processing circuit 1401 (eleventh
The sector mark signal 1411 output from FIG. 9 constitutes a counter circuit 2201, for example, nine counter Nos. 1 to N
Sent to o.9. Each output signal 221 of counter No.1 to No.9
1 to 2219 are transmitted to the determination circuit 2202, and the sector mark detection signal 21 based on the determination result in the determination circuit 2202.
10 is output. As described above, the sector mark detection circuit
Reference numeral 2101 denotes a sector mark portion 1701 (for example, FIG. 14A)
Is a circuit for detecting the synchronization timing necessary for performing the recording, reproducing and erasing operations in sector units.

The operation of the counters No. 1 to No. 9 in the counter circuit 2201 will be described with reference to FIG. Here, it is assumed that the pattern of the sector mark portion 1701 is composed of, for example, a mark 2811 and a non-mark 2812 as shown in FIG. In this example, as shown in FIG. 7A, a plurality of marks are arranged such that the ratio of the mark length to the non-mark length is in the order of 5: 3: 3: 7: 3: 3: 3: 3: 5. 2811 is engraved.
The sector mark signal 1411 obtained by reproducing the pattern of the mark 2811 and the non-mark 2812 has a low level (“0”) at the mark portion and a high level at the non-mark portion, as shown in FIG. The signal is converted into a binary signal having a level (“1”).

The sector mark signal 1411 corresponds to the above counter No. 1 to No. 9
, First, the counter No. 1 ((e) in the figure) counts the number of counter clocks 2310 corresponding to the mark length “5”. The counter clock 2310 has a higher frequency than the sector mark signal 1411 as shown in FIG. If the counted number is within the predetermined range, the first mark 2811 (mark length "5") has been correctly detected. Subsequently, a non-mark 2812 having a non-mark length “3” is similarly detected in the counter No. 2. As described above, the mark 2811 and the non-mark 2812 of the sector mark portion 1701 are sequentially detected, and finally, the counter No. 9 detects the length of the mark length “5”. 9 marks 2811 or non-marks 28 obtained as described above
Twelve detection signals 2211 to 2219 are sent to the judgment circuit 2202 (FIG. 17).

Then, it is determined whether or not all or a part of the detection results of the nine marks 2811 or non-marks 2812 match the pattern of the sector mark portion 1701, and the marks 2811 and non-marks 2812 are determined. Are determined. As a result, the sector mark detection signal 2110 becomes low level (“0”) only when it is determined that the sector mark portion 1701 is present. The sector mark detection signal 2110 obtained as described above can be used as synchronization timing in units of the sector 3004.

Next, waveforms of respective parts of the timing generation circuit 1501 will be described below with reference to FIG.

As shown in FIG.
As described above, when the sector mark section 1701 ((a) in the figure) in the preformat section 3003 is detected, the level becomes low, and the falling edge of the sector mark detection signal 2110 becomes the synchronization timing of the sector 3004. . Counter 2102
Sets the counter output signal 2111 to low level after a predetermined count has been counted from the falling edge of the sector mark detection signal 2110, as shown in FIG.

On the other hand, the count number of the timer circuit 2104 is set to be larger by the sector length of one sector 3004 by adding the count number of the counter 2102. Therefore,
As shown in FIG. 19 (d), the output signal of the timer circuit 2104
The timing of the falling edge of 2112 substantially coincides with the falling edge of the counter output signal 2111 of the next sector 3004.

Also, as shown in FIG.
The output signal 2114 of 05 is set to a low level with a predetermined window width near the falling edge of the sector mark detection signal 2110 in the next sector 3004 based on the falling edge of the sector mark detection signal 2110. . Timing determination signal which is the output signal of the determination circuit 2106
2115, when the output signal 2114 of the window generation circuit 2105 is at a low level and a falling edge of the sector mark detection signal 2110 exists, as shown by a solid line in FIG. Has become. On the other hand, if the falling edge of the sector mark detection signal 2110 does not exist, it becomes a low level (indicated by a dotted line in FIG. 7F). Therefore, the timing determination signal 2115 is
Is a signal for determining whether or not detection has been detected in a predetermined range or a detection error.

In the switch circuit 2103, the counter output signal 2111 is selected when the sector mark portion 1701 can be detected, and the timer circuit output signal 2112 is selected when the detection is incorrect. . As a result,
As shown in (g) of the figure, the reference timing signal 1510 can be reliably output by performing correction based on the timing of the immediately preceding sector 3004 even if a detection error occurs in the sector mark portion 1701. The reference timing signal 1510 thus obtained is transmitted to the data part determination circuit 2107.

The data part determination circuit 2107 is a kind of counter, and the output signal of the data part determination signal 2116 becomes low level in the normal use range 1703 in the MO part 3002 ((h) in the figure). That is, the data part determination signal 2116 can be used as a signal for determining the preformat part 3003 and the MO part 3002. The reference timing signal 15 thus obtained
10, timing determination signal 2115 and data part generation signal 2116
Is transmitted to the control circuit 1502 in FIG. In the control circuit 1502, the above signals 1510, 2115 and 2116
The various control signals 1213 described above are generated based on the above.

Next, the operation of the signal processing circuit 1401 shown in FIG. 11 will be described with reference to FIGS. 20 to 22.
Reproduction signal 1211 reproduced from 1201 (reproduction signals S1 and S2)
Is the buffer amplifier 25 in the signal processing circuit 1401 (FIG. 20).
Entered in 01. Output signal 2510 of buffer amplifier 2501
Are the MO waveform processing unit 2502 and the pre-format waveform processing unit 25
Transmitted to 03. MO waveform processing unit 2502 to MO unit 3002
While the MO binarized signal 2511 corresponding to the mark 2809 and the non-mark 2810 recorded as the MO signal is output, the preformat waveform processing unit 2503 outputs the preformat
ID binarized signal 2 corresponding to mark 2811 and non-mark 2812
512 is output. These binary signals 2511 and 2512 are input to the data synchronization unit 2504,
In L (PHASE LOCKED LOOP), synchronization data 2513 synchronized with the clock is generated and transmitted to the demodulation circuit 1402 (FIG. 11).

The preformat waveform processing section 2503 generates a sector mark signal 1411 and outputs the signal to the timing generation circuit 1501 (12th
Figure). In the signal processing control unit 2505,
Various control signals 2514 to 2517 between each unit in the signal processing circuit 1401
Is input and output. Also, various control signals 1213 are input / output to / from the controller 1208 in FIG.

FIG. 21 shows the waveform of each part of the signal processing circuit 1401. 21st
As shown in FIGS. (B) and (c), the reproduced signals S1 and S2 are MO waveform processing units.
At 2502, only the MO signal of the MO section 3002 is separated and further binarized to generate a MO binarized signal 2511 (FIG. 11D). Also, the reproduction signals S1 and S2 are added in a preformat waveform processing unit 2503 to separate only the information of the preformat unit 3003, and are further binarized.
A value signal 2512 and a sector mark signal 1411 are obtained (FIGS. 9E and 9G).

The reason that the MO unit 3002 and the preformat unit 3003 can be separated by differential and addition of the reproduction signals S1 and S2 is that, as shown in FIG. 38, the polarities of the reproduction signals S1 and S2 are opposite in the MO unit 3002, On the other hand, as shown in FIG. 39, the same is true in the preformat unit 3003. MO binary signal 2511
And the ID binarized signal 2512, as shown in FIG.
The data is converted into synchronization data 2513 synchronized with the clock in the data synchronization unit 2504.

FIG. 22 is a diagram for explaining the waveform of FIG. 21 in detail. For example, irregularities are generated based on the modulation data 1310 (FIG. 22 (a)) generated based on the modulation rule of Table 1 described above. 28
It is assumed that a mark 2811 (or 2809) and a non-mark 2812 (or 2810) are recorded at 08 (or MO signal) as shown in FIG. These marks 2811 (or 2809) and non-marks 2812 (or 2810) are reproduced by irradiation of the laser spot 2701. As shown in FIG.
S2 is a signal having a peak value at the center of the mark 2811 (or 2809).

The MO binarized signal 2511 or the ID binarized signal 2512 is a signal that detects this peak position, and its rising edge coincides with the peak position (see FIG. 3D). In the PLL in the data synchronization unit 2504, a synchronization clock is generated from the MO binarization signal 2511 or the ID binarization signal 2512, and synchronization data 2513 is obtained by synchronizing with the clock. As shown in FIG. 11E, the synchronization data 2513 is data obtained by faithfully reproducing the modulation data 1310.

FIG. 7A shows a main part of the preformat waveform processing section 2503. The above-described reproduced signals S1 and S2 are input to the addition amplifier 64 in the preformat waveform processing unit 2503, and as described above, by adding S1 and S2, only the information of the preformat unit 3003 in the reproduced signal is obtained. It is to be separated. The information of the preformat unit 3003 is input to the preformat AGC amplifier 65, where it is amplified according to the amplitude, then binarized in the binarization circuit 66, and output as the above-described ID binarization signal 2512. Is done.

FIG. 7 (b) shows a main part of the MO waveform processing section 2502, and the reproduction signals S1 and S2 are input to the differential amplifier 74 in the MO waveform processing section 2502, where the reproduced signals are transmitted as described above. , S1 and S2 are differentiated so that only the MO signal in the reproduced signal is separated. MO signal is AGC amplifier for MO signal 75
Here, after being amplified in accordance with the amplitude, it is binarized by the binarization circuit 76 and the MO binarized signal 2511 is output. The AGC voltage is output from the MO signal AGC amplifier 75 to the A / D converter 49 in the controller 1208 (see FIG. 31).

Next, the configuration of the preformat AGC amplifier 65 serving as a first auto gain control unit will be described in more detail. As shown in FIG. 4, the preformat AGC amplifier 65 mainly includes a clamp circuit 78, a comparator 79, an AGC voltage generation circuit 80, and a voltage control amplifier (hereinafter referred to as VCA) 77, An addition signal which is an output signal of the amplifier 64 is input to the VCA 77.

The amplification degree of VCA77 is AGC which is the output of AGC voltage generation circuit 80.
It changes according to the voltage, and as shown in FIG. 43, the amplification degree decreases as the AGC voltage increases.

The output of the VCA 77 is transmitted to the binarization circuit 66 (FIG. 7) and input to the clamp circuit 78. In the clamp circuit 78, the DC component in the output signal of the VCA 77 is cut, and the positive output of the AC component (corresponding to the peak-to-peak value) is reduced by the diode D in the circuit 78 in the forward direction. The voltage is clamped to the voltage value, and the negative output is not clamped.
To the inverting input terminal. In the comparator 79, the reference voltage V _0, which is applied to the non-inverting input terminal, an output voltage of the clamp circuit 78 is compared magnitude.

The output signal of the comparator 79 is input to one input terminal of the AND circuit 90, and the other input terminal of the AND circuit 90 is connected to the preformat hold timing signal 113 via an inverter 91 serving as a first control means. (To be described later) is input. And AND circuit 9
An output signal of 0 is input to the AGC voltage generation circuit 80 via the resistor 92.

In the above configuration, the preformat hold timing signal 113 is at a low level and the preformat A
The operation when the GC amplifier 65 does not hold the AGC voltage will be described first. At this time, the inverter 91 and the AND circuit 9
Since the input signal to 0 becomes high level, the output signal of the AND circuit 90 is determined by the input signal from the comparator 79 to the AND circuit 90.

Now, when the output amplitude of the clamping circuit 78 is greater than the reference voltage V _0, the output signal of the comparator 79 becomes high level, therefore, the output of the AND circuit 90 also becomes high level, the transistor 81 is turned on . Therefore, the capacitor 83 is charged by the power supply V _CC via the charging resistor 82,
The AGC voltage, which is the voltage across capacitor 83, increases. At this time, the charging time constant is determined by the charging resistor 82 and the capacitor.
Determined by 83. The AGC voltage generated at the connection point A between the charging resistor 82 and the capacitor 83 is used as a control voltage for adjusting the amplification degree.
The signal is fed back to the CA77, but if the AGC voltage increases as described above, the amplification of the VCA77 decreases.

On the other hand, when the output amplitude of the clamping circuit 78 is lower than the reference voltage V _0, the output signal of the comparator 79, therefore,
Since the output signal of the AND circuit 90 becomes low level and the transistor 81 turns off, the electric charge stored in the capacitor 83 is discharged via the discharge resistor 84. At this time, the discharge time constant is determined by the discharge resistor 84 and the capacitor 83. As the capacitor 83 discharges, the AGC voltage decreases and the VCA77
Has a large amplification degree.

As is clear from the above description, there is a relationship as shown in FIG. 44 between the peak-to-peak value (PP value) of the added signal of S1 and S2 and the AGC voltage. It can be seen that the AGC voltage monotonically increases with respect to the peak-to-peak value of the differential signal in the normal amplitude range shown in FIG. That is, the maximum value / minimum value of the AGC voltage corresponds to the maximum value / minimum value of the peak-to-peak value of the addition signal. Note that the above clamp circuit 78
May be a full-wave rectifier circuit.

Next, the operation when the preformat AGC amplifier 65 holds the AGC voltage will be described. However, the reason why the AGC voltage is held in the preformat AGC amplifier 65 is that the optical head 1203 (FIG. 9) is operated by the MO unit 3002 in each sector 3004 in a mode that requires holding at the time of recording / erasing described below. Only during the period when the optical head 1203 passes through the preformat section of each sector 3004.
When passing through the 3003, the AGC voltage hold is released because it is necessary to reproduce the address information and the like of the preformat unit 3003 even during recording or erasing.

Therefore, the AGC in the preformat AGC amplifier 65
One hold period of the voltage is a period during which the voltage passes through the MO unit 3002 of one sector 3004, and recording / erasing is performed in a plurality of sectors 3004.
, The pre-format unit 3003 and the MO unit 3003 of each sector 3004 alternately turn on (hold release) and hold the AGC voltage.

In the preformat AGC amplifier 65, when holding the AGC voltage, if the preformat hold timing signal 113 is set to the high level, the output signal of the inverter 91 is inverted from the high level to the low level. Accordingly, if the output signal of the AND circuit 90 is at a low level (that is, the output signal of the comparator 79 is at a low level), the output signal of the AND circuit 90 is maintained at a low level thereafter. That is, the comparator 79
If the output signal of the transistor 81 is at the high level), the signal is inverted to the low level. Therefore, if the transistor 81 has been turned off until then, the off state is maintained, and if the transistor 81 has been turned on so far, the transistor 81 is turned off.

Therefore, the preformat hold timing signal
When 113 is set to the high level, the electric charge accumulated in the capacitor 83 is discharged thereafter, but one hold period in the preformat AGC amplifier 65 is a short period passing through the MO unit 3002 of one sector 3004. Therefore, if the discharge time constant by the capacitor 83 and the discharge resistor 84 is set to be sufficiently large, the amount of change in the charge of the capacitor 83 during one hold period, that is, the amount of change in the AGC voltage is extremely small. Since it is slight, it can be considered that the AGC voltage is held at a substantially constant value during one hold period.

As described with reference to FIGS. 46 to 48, it is during recording / erasing and access that accurate reproduction becomes difficult due to fluctuations in the amplification degree of the AGC amplifier. Therefore, the preformat AGC amplifier 65 holds the AGC voltage at the time of recording / erasing and at the time of access (however, as described above,
(Only during the period of passing through the MO unit 3002 of each sector 3004).

Fig. 2 shows the AGC in the preformat AGC amplifier 65.
1 shows a logic circuit for controlling voltage hold timing.

This logic circuit is composed of an OR circuit 100. The OR circuit 100 has a recording / erasing timing signal 94 and an access timing signal 95.
Is input. The recording / erasing timing signal 94 is a high level signal during recording or erasing, and is a low level signal at other times. The access timing signal 95 is a high level signal at the time of accessing, and a low level signal at other times. Accordingly, the preformat hold timing signal 113 obtained as an output signal of the OR circuit 100 has a high level (“1”) at the time of recording / erasing or access, as is clear from Table 2 below. Otherwise, it goes low ("0").

Further, the AGC voltage detection timing signal 96 is a signal which is at a high level when an AGC voltage is detected by a test write or the like to be described later and is at a low level at other times.
Used as the C speed control signal 97.

The preformat AGC speed control signal 97 is a signal for switching the response speed of the preformat AGC amplifier 65 to, for example, two stages of high speed and low speed. As shown in Table 2, when the AGC voltage is detected, The pre-format AGC speed control signal 97 becomes high level ("1"), and the response speed of the pre-format AGC amplifier 65 is increased. On the other hand, when the AGC voltage is not detected, the pre-format AGC speed control signal 97 is set to the low level (“0”), and the response speed of the preformatting AGC amplifier 65 is reduced. Note that the symbol x in Table 2 indicates that either "1" or "0" may be used.

Next, a circuit for switching the response speed of the preformat AGC amplifier 65 between, for example, two stages of high speed and low speed will be described.

As shown in FIG. 6, this circuit serving as a response speed changing means is configured as a response speed changing / resetting circuit 101 also having an AGC voltage reset function. That is, the response speed change / reset circuit 101 is composed of a pair of open collectors 87 and 88 and a discharge resistor 89. The output of the open collector 88 is a charge resistor 82 and a capacitor 83 in the preformat AGC amplifier 65. Is connected to a connection point A.

The open collector 87 receives a preformat AGC speed control signal 97, while the open collector 88 receives a preformat AGC reset signal 102. The preformat AGC speed control signal 97 goes high when an AGC voltage is detected. At this time, the output of the open collector 87 becomes low level, and the discharge resistor 89 is connected in parallel with the discharge resistor 84 in FIG. As a result, the time required for discharging the capacitor 83 is reduced.

On the other hand, the preformat AGC reset signal 102 becomes high level when the system is activated or when the system is abnormal.
At this time, since the discharge resistor 84 is short-circuited, the discharge is completed instantaneously.

Next, a more specific configuration of the MO signal AGC amplifier 75 serving as a second auto gain control unit will be described. As shown in FIG. 5, the MO signal AGC amplifier 75
Are configured in the same manner as the preformat AGC amplifier 65. Here, members having the same functions are denoted by the same reference numerals, and description thereof is omitted.

In the MO signal AGC amplifier 75, the AGC voltage generated by the AGC voltage generation circuit 80 is applied to the hold circuit 93 and the analog switch 94.
And one of the contacts 94a. The hold circuit 93 has a role as a second control means in claim 1 and a function as hold means in claim 3 in the column of claims. For example, the hold circuit 93 is located in an A / D converter and a subsequent stage. The D / A converter is configured to hold the AGC voltage sampled at a predetermined timing thereafter.

The output signal of the hold circuit 93 is input to the other contact 94b of the analog switch 94. The hold circuit 93 and the analog switch 94 are supplied with a hold timing signal 103 for an MO signal, which will be described later, and the hold timing signal 103 for the MO signal is at a low level.
When the holding of the AGC voltage is not performed, the contacts 94a and 94b of the analog switch 94 are opened as shown in the figure, and the AGC voltage is directly fed back to the VCA 77.

The operations of the clamp circuit 78 and the AGC voltage generation circuit 80 when the AGC voltage is not held are the same as those of the preformat AGC amplifier 65 except that the input signal to the VCA 77 is a differential signal of S1 and S2. Since the operation is the same as that of the clamp circuit 78 and the AGC voltage generation circuit 80, the detailed description is omitted here.

On the other hand, as described later, when the AGC voltage is held during recording / erasing, etc., the contacts 94a and 9a of the analog switch 94
4b is closed and the held constant AGC voltage is VCA77
And the amplification degree of the VCA 77 is maintained at a constant value. Here, in the MO signal AGC amplifier 75, the holding of the AGC voltage is performed for both the preformat unit 3003 and the MO unit 3002 of each sector 3004.

The AGC amplifier 75 for the MO signal also has the A
A response speed change / reset circuit 101 similar to the GC amplifier 65 is provided. Also, as the hold circuit 93, the above-mentioned A /
Instead of having a D converter and a D / A converter,
An analog sample-and-hold circuit may be used.

Note that, instead of the hold circuit 93, a method of fixing the voltage at a constant voltage using an analog switch may be used. In this case, there is a slight deviation from the actual AGC voltage. Therefore, it is preferable to set the deviation so as to be as small as possible.

In the AGC amplifier 75 for the MO signal, as in the AGC amplifier 65 for the preformat, the A
In addition to holding the GC voltage, the AGC voltage is also held during the reproduction of the MO unit 3002 even in an unrecorded area where no information pulse group is detected.

As described above, this is because the MO signal AG
When the C-amplifier 75 is operated, the amplitude of the reproduced signal is almost zero level in the unrecorded area, so that the amplification increases near the maximum level, and then, when it is related to the recorded area,
This is because the degree of amplification may be excessive and accurate reproduction may not be performed.

On the other hand, since information such as an address is always recorded in the preformat unit 3002, the preformat AGC
The amplifier 65 does not control the hold / on of the AGC voltage based on the detection of the pulse group (recorded area). A circuit for detecting a pulse group will be described later in detail.

A logic circuit for switching between holding and turning on the AGC voltage in the MO signal AGC amplifier 75 includes a NOR circuit 1 as shown in FIG.
04 and an OR circuit 105 are provided. A pulse group detection signal 106 and an AGC voltage detection timing signal 96 are input to the NOR circuit 104. As described later, the pulse group detection signal 106
002 is a signal generated based on the discrimination result between the recorded area and the unrecorded area of the MO signal.
The signal is at a high level in a recorded area where a pulse group is detected by a signal, and is at a low level in an unrecorded area where a pulse group is not detected.

The output signal of the NOR circuit 104, the above-described recording / erasing timing signal 94, and the access timing signal 95 are input to the OR circuit 105, and the output signal of the OR circuit 105 is used as the MO signal hold timing signal 103. You. Also here, the AGC voltage detection timing signal 96 is used as it is for the MO signal A.
This is the GC speed control signal 107. In this case, the MO data hold timing signal and
The AGC speed control signal changes as shown in Table 3.

That is, the MO signal hold timing signal 103 is recorded and
At the time of erasing, at the time of access, and in the reproduction mode, the MO (data) section 3002 becomes high level during reproduction of the unrecorded area where the information pulse group is not detected.
The GC voltage is held at the value immediately before the start of recording / erasing.

Also, the MO signal hold timing signal 103 is also input to the inverter 91 (FIG. 5), whereby the capacitor 83 is not charged, and the output of the hold circuit 93 becomes the AGC voltage.

Here, the switching control of the hold / on of the AGC voltage in each of the AGC amplifiers 65 and 75 and the switching control of the response speed when the amplification degree is adjusted based on the AGC voltage will be described with reference to the flowchart of FIG. More specifically, first, it is determined whether or not recording / erasing is being performed (S1). If so, the AGC voltages of both AGC amplifiers 65 and 75 are held (S2).

On the other hand, if it is not at the time of recording / erasing at S1, it is determined whether or not it is at the time of access (S3).
The AGC voltage of the C amplifiers 65 and 75 is held (S2).

If it is not the time of access, it is subsequently determined whether or not it is the time of detection of an AGC voltage of a test write described later (S
4) If so, set the response speed to high (S
5) Turn on the AGC voltage of both AGC amplifiers 65 and 75 (S
6).

On the other hand, if the AGC voltage is not detected in S4, the remaining mode is the reproduction mode only, and thus the information recorded in the MO unit 3002 is currently being reproduced. In that case,
It is determined whether or not a pulse group based on the MO signal is detected (S7). If detected, the recorded area is being reproduced, so that the response speed is set to low (S7).
8) The AGC voltages of both AGC amplifiers 65 and 75 are turned on, and the amplification is adjusted based on the amplitude of the reproduced signal (S6).

On the other hand, if no pulse group due to the MO signal is detected in S7, it means that an unrecorded area in the MO unit 3002 is being reproduced, and only the AGC voltage of the AGC amplifier 75 for the MO signal is held (S2).

In FIG. 8, sector 3004 indicated by A (FIG. 8 (a))
The MO signal is recorded in the MO section 3002 in the sector 30 shown by B.
In 04, the MO signal recorded in the MO section 3002 is reproduced, and in the sector 3004 indicated by C, the MO signal recorded in the MO section 3002 is erased.

In that case, the MO signal 3003 of the sector 3004 of A
The amplitude of S2 ((b) in the figure) becomes excessive, but in the present embodiment, both AGC amplifiers 65 and 75 are used in the MO section 3002 of the sector 3004 of A.
AGC voltage of the next B sector 3004
Since the AGC voltage of the preformatting AGC amplifier 65 ((d) in the figure) was held at the value at the time of the end of the reproduction of the preformatting section 3003 of the sector 3004 of A at the time of the reproduction of the preformat section 3003 of FIG. as shown in B ₁ part of c), the amplification degree of the pre-formatted for the AGC amplifier 65 at the time of reproduction of the preformat portion 3003 of the sector 3004 of B becomes a proper value, the reproduction of the preformat portion 3003 of the sector 3004 of B Is performed smoothly.

Similarly, since the AGC voltage of both AGC amplifiers 65 and 75 is held in the sector C 3004 to be erased when the signal passes through the MO unit 3002, the reproduction of the preformat unit 3003 of the next sector 3004 D is properly performed. Will be

Also, in the sector 3004 of B to be reproduced, the MO unit 3002
Assuming that no pulse group due to the MO signal exists, the preformat AG
Since the AGC voltage of the C amplifier 65 is held, the reproduction of the preformat section 3003 of the next C sector 3004 is also properly performed.

Incidentally, the size of the mark 2809 in magneto-optical recording varies depending on recording conditions such as the recording light amount, the recording pulse length, and the externally applied magnetic field 2806. That is, as shown in FIGS. 39A and 39B, as the amplitude of the recording pulse, that is, the recording light amount increases, the size of the mark 2809 to be recorded increases (however, the recording pulse length is constant). FIG. 40 (a)
As shown in (b), even if the recording pulse length is increased in a state where the amplitude of the recording pulse is kept at a constant value, the size of the mark 2809 to be recorded increases almost in proportion to the recording pulse length.

As described above, if the size of the mark 2809 varies, an error in the reproduction data may occur. For example, in FIG. 41, under the recording condition in which the mark 2809 is recorded with the size shown by the solid line in FIG. 41A, the S / N ratio is the best as shown by the solid line in FIG. . On the other hand, when recording, whether the recording light amount (or recording pulse length) corresponding to the solid line is larger or conversely smaller,
Regardless of whether the size of the mark 2809 is too large or too small as shown by the dotted line in FIG. 7A, the amplitude (peak-peak value) of the reproduced signal is shown by the dotted line in FIG. (See, for example, JP-A-58-80138). Therefore, in order to obtain error-free reproduction data, it is necessary to always optimally control the recording conditions.

The optimum control of the recording condition is a condition in which the recording information having a predetermined fundamental frequency is experimentally recorded (test-written) in the magneto-optical memory while changing the recording light amount or the like, and the amplitude of the reproduction signal at the time of reproduction is maximized. It is known that the following recording is performed under the recording conditions at that time. In this case, a circuit for detecting the maximum amplitude, the envelope, the first and second harmonics, and the like is required in order to actually obtain the amplitude of the reproduced signal, and thus there is a problem that the circuit configuration is complicated.

Therefore, the magneto-optical memory device is an AGC amplifier 75 for the MO signal.
Is provided, by sampling the AGC voltage for controlling the amplification of the MO signal AGC amplifier 75,
It is conceivable to determine the amplitude of the reproduction signal. That is, under the recording condition where the amplitude of the reproduced signal is maximized, the MO signal AG
Since the amplification degree of the C amplifier can be considered to be almost the minimum level, the amplification degree (determined by the AGC voltage) of the MO signal AGC amplifier 75 is minimized by performing test writing under a plurality of recording conditions. If the recording condition is obtained, it can be determined that the recording condition is almost the optimum recording condition.

More specifically, referring to FIG. 42, for example, FIG.
The eight sectors 3004 indicated by A to H are used as recording areas for test writing, and a test is performed on each MO unit 3002 with a sequentially increasing recording light amount (or recording pulse length) as shown in FIG. Shall be written.

MO section in sector 3004 recorded as above
When the information of 3002 is reproduced, as shown in FIG. 42 (c),
For example, an MO signal composed of a differential signal of the reproduction signals S1 and S2 is obtained for each sector 3004. As shown in FIG. 43, between the AGC voltage and the amplification degree of the MO signal AGC amplifier 75, A
Since the amplification degree decreases as the GC voltage increases, the AGC voltage changes as shown in FIG. 42 (d) according to the amplitude of the MO signal of each sector 3004.

That is, as the amplitude of the MO signal increases, the AGC voltage increases, and accordingly, the degree of amplification of the MO signal AGC amplifier 75 decreases. Note that there is a relationship as shown in FIG. 44 between the peak-to-peak value (PP value) of the differential signal of S1 and S2 and the AGC voltage, and in the normal amplitude range in FIG. Is almost monotonically increasing as the peak-to-peak value of the differential signal increases.

The AGC voltage of each sector 3004 is sampled at the sample timing (for example, the rising edge of each pulse) shown in FIG. Then, the recording light amount (or recording pulse length) corresponding to the maximum value of the AGC voltage (corresponding to the position where the amplitude of the MO signal becomes maximum) is obtained, and thereafter, recording / erasing is performed using this recording light amount (or recording pulse length). Are performed.

In the above example, the AGC voltage of the MO signal AGC amplifier 75 obtained by reproducing the sectors E, F and G is at the same level, and the recording light amount (or recording pulse length) of the sector G is made larger than that. It can be seen that the AGC voltage decreases (that is, the amplitude of the MO signal decreases) even if the amplitude is reduced. Therefore, the optimum recording conditions are determined from the recording light amounts (or recording pulse lengths) of the sectors E, F and G.

Generally, when the recording conditions such as the recording light amount and the recording pulse length are changed, the recording mark length also changes, and the recording mark length corresponds to the optimum recording condition indicated by the broken line in FIG. 45, as shown in FIG. The AGC voltage becomes smaller and the S / N ratio is reduced when the length is longer than the length to be performed, or conversely, when the length is shorter. At this time, the bit jitter increases. For convenience of explanation,
When changing the recording conditions, the recording pulse length is fixed when changing the recording light amount, and the recording light amount is fixed when changing the recording pulse length.

In the above test light, for example, if the recording light amount is to be sequentially changed, the aforementioned light amount monitoring circuit 1804 is used.
The light quantity monitor signal 1813 is input to the processor 70 in the controller 1208 shown in FIG. 31 via (FIG. 13), and is stored in a storage element such as a RAM or an E ² PROM provided in the processor 70, for example. You.

Then, as shown in FIG. 42 (c), when the MO signals recorded in the sectors 3004 from A to H are sequentially reproduced,
The AGC voltage of the MO signal AGC amplifier 75 is sampled and stored in the storage element.

Then, an optimum recording condition when the AGC voltage is maximized is obtained, and thereafter, at the time of recording, a recording / erasing light amount control signal 1811 and a recording pulse length control signal corresponding to the above-mentioned optimum recording condition are output from the processor 70. Is done.

The recording / erasing light amount control signal 1811 is input to the recording / erasing light amount control circuit 1803 (FIG. 13), so that the light amount of the semiconductor laser 2801 corresponding to recording / erasing is controlled. On the other hand, the pulse length control signal is
02, and the modulation data is controlled based on this.

That is, as shown in FIG. 32, the recording data 1311 sent from the controller 1208 is input to the modulation unit 71 in the modulation circuit 1302. The modulation unit 71 performs modulation in synchronization with the timing signal, for example, according to the 2,7 modulation scheme as shown in Table 1. The modulated recording data 1311 is processed in the recording format section 72 in synchronization with the timing signal so as to conform to the recording format, and further in the recording pulse length control section 73 based on the above-described pulse length control signal. Is generated.

This modulation data 1310 is used for the semiconductor laser drive circuit shown in FIG.
The semiconductor laser drive circuit 1301 outputs the semiconductor laser drive current 1210 to the semiconductor laser drive circuit 1301, and transmits the semiconductor laser drive current 1210 to the semiconductor laser 2801 in the optical head 1203. Thus, the recording pulse length can be controlled.

Hereinafter, a pulse group detection circuit for detecting whether or not a pulse group due to the MO signal exists in the MO unit 3003 will be described.

That is, as shown in FIG. 23, the pulse group detection circuit 17
For example, a retriggerable pulse generator 16 includes a retriggerable pulse generator 16 which outputs an MO2 value, which is an output signal of a binarization circuit 76 that binarizes the MO signal amplified by the MO signal AGC amplifier 75. The conversion signal 2511 is input.

When a pulse group exists in the MO binarized signal 2511, the pulse group detection circuit 17 outputs the pulse group detection signal 106 (third
0 (see FIG. 7C) is set to a high level. Since the pulse group detection circuit 17 includes the retriggerable pulse generation circuit 16, if the next pulse is input within τ seconds after the input of the previous pulse in the MO binarized signal 2511, The pulse group detection signal 106 for a second is set to a high level.

FIG. 24 shows one configuration example of the retriggerable pulse generation circuit 16. Here, the retriggerable pulse generating circuit 16 is constituted by a one-shot multivibrator 18.
The time τ during which the pulse group detection signal 106 is set to the high level is set by the resistor R and the capacitor C. Specifically, τ
Is proportional to RC.

FIG. 25 is a configuration example using a shift register 19 as the retriggerable pulse generation circuit 16. Serial input terminal
IN is at the high level, and the clock input terminal CK has the frequency
Enter the clock f _c, the N-th output of the shift output terminal QN bar and a recorded area detection signal P. The MO binarization signal 2511 is input to the clear terminal CL. In this case, τ
= N × (1 / f _c ).

FIG. 26 shows an example in which a divide-by-N counter 20 is used as the retriggerable pulse generating circuit 16. The binarized MO signal 2511 is input to the clear terminal CL, the output of the output terminal OUT bar is used as the pulse group detection signal 106, and the pulse group detection signal 106 is ANDed.
The signal is also input to one input terminal of the circuit 21. Also, AND circuit 2
Clock frequency f _c is input to the 1 of the other input terminal, the output of the AND circuit 21 is inputted to the clock terminal CK of the divide-by-N counter 20. Also in this case, τ = N × (1 / f _c ).

FIG. 30 (a) shows an example of the output signal of the MO signal AGC amplifier 75, and FIG. 30 (b) shows the MO2 binarized by the binarization circuit 76.
An example of the binarized signal 2511 is shown in FIG.
5 shows an example of the pulse group detection signal 106 generated based on.

Here, when one pulse is present in the MO binarized signal 2511, the time τ during which the pulse group detection signal 106 is set to the high level is longer than the maximum pulse interval T _max between adjacent pulses in the MO binarized signal 106. It is set to be. As a result, as the pulse group detection signal 106 output from the pulse group detection circuit 17, as shown in FIG.
A signal substantially equal to the recorded area of the pulse group by the MO signal in the output signal of the GC amplifier 75 can be obtained.

 Next, a modified example of the pulse group detection circuit will be described.

This modification is based on the case where a defect pulse as shown by a dotted line S or T in FIG. 30 (a) exists in the unrecorded area of the pulse group by the MO signal, based on this defect pulse (c). The countermeasure is taken so that the pulse group detection signal 106 is not erroneously set to the high level as shown by the dotted line U or V in FIG.

That is, the pulse group detection circuit 17 in the modified example
As shown in Figure 27, an appropriate retriggerable pulse generator
22 and a leading pulse removing circuit 23. The leading pulse removing circuit 23 is a circuit for invalidating the output of the retrigable pulse generating circuit 22 for the leading M pulses in the MO binarized signal 2511.

FIG. 28 shows a specific configuration example of the leading pulse removing circuit 23. Here, an M-ary counter 24 is arranged as a leading pulse removing circuit 23 at a stage preceding the retriggerable pulse generating circuit 22,
The first M pulses in the binary signal 2511 are removed. Instead of the M-ary counter 24, an M shift register may be used.

FIG. 29 shows another configuration example of the leading pulse removing circuit 23.
Here, a shift register 25 as a leading pulse removal circuit 23 is disposed after the retriggerable pulse generation circuit 22,
Shift register output of retriggerable pulse generation circuit 22
25, and the MO binarized signal 2511 is input to the clock terminal CK of the shift register 25, and the M-th shift output QM is used as the pulse group detection signal 106 '.

Here, the timing control will be described with an example of M = 1, that is, the case where the output of the retriggerable pulse generation circuit 22 is invalidated for only the first pulse in the MO binarized signal 2511. .

As shown in FIG. 30 (a), if there is only one defect pulse in the unrecorded area of the MO signal, this defect pulse is invalidated by the leading pulse removing circuit 23, so that FIG. 30 (d) As shown in (1), the pulse group detection signal 106 'is not set to the high level based on the defect pulse.

In the recorded area of the pulse group by the MO signal,
The timing when the pulse group detection signal is set to the high level is 1
Although it is delayed by a pulse, for example, as a hold timing of the AGC voltage, a delay of about several pulses has no adverse effect. Therefore, the reliability of the operation of the AGC does not decrease.

In the above embodiment, both AGC amplifiers 6
Although the AGC voltage of 5.75 is held, as described above, it is not always necessary to hold the AGC voltage when the access speed is relatively low.

Further, in the above embodiment, the signals of the preformat unit 3003 and the MO unit 3002 are obtained by adding and differentiating the two types of reproduction signals S1 and S2. Is also good.

Further, in the above-described embodiment, the magneto-optical disk 1201 has been described as an example of the optical memory. However, other than that, a phase-change type optical disk on which information can be rewritten or desired information can be recorded only once. The present invention is also applicable to an auto gain control device for an optical memory device that performs recording or reproduction on a write-once optical disk or the like.

〔The invention's effect〕

As described above, the automatic gain control device of the optical memory device according to the first aspect of the present invention is provided in the optical memory device that performs recording, erasing, or reproduction on the optical memory, and the control voltage generated according to the amplitude of the reproduction signal. A first control means for holding the control voltage during recording or erasing, and a recorded area determination for determining a recorded area of information at the time of reproduction. Means, and second control means for holding the control voltage in an unrecorded area of the information based on the determination by the recorded area determination means.
The control means is configured to hold the control voltage in preference to the second means.

Thus, the control voltage is held at the time of recording or erasing, so that at the time of recording or erasing, the amplification degree of the automatic gain control device is maintained at the value before the start of recording or erasing. Therefore, the amplification at the start of reproduction immediately after the end of recording or erasing is the same as that at the end of the previous reproduction. Can be performed. Therefore, it is possible to reduce a reproduction error immediately after the end of recording or erasing.

By the way, in an unrecorded area of information in the optical memory,
Since the amplitude of the reproduction signal is low, if the unrecorded area exists continuously, the amplification of the automatic gain control device gradually increases to near the maximum value. In this case, when passing through an unrecorded area and approaching a recorded area, the amplification degree remains at an excessive level, so that normal reproduction becomes difficult.

Therefore, a recorded area determining means for determining a recording area of information at the time of reproduction and a second control means for holding the control voltage in an unrecorded area of information based on the determination of the recorded area determining means are added. , The first control means includes:
If the control voltage is held in preference to the control means, the amplitude is maintained as it was when the previous recorded area was reproduced when passing through the unrecorded area. Next, the reproduced signal can be amplified with a substantially appropriate amplification degree immediately after the recording area is approached.

Further, in the first aspect of the present invention, if a response speed changing means for changing the response speed in multiple stages is provided, for example, the control voltage (eg, the above-described AGC When the response speed of the automatic gain control device is increased at the time of detection of a voltage, etc., it is possible to cope with a change in the amplitude of the reproduction signal at a minute interval such as a sector unit.
On the other hand, when normal information is reproduced, by setting a low response speed, the influence of a defect pulse or the like can be reduced to reduce a reproduction error.

Further, the automatic gain control device of the optical memory device according to the second aspect of the present invention provides a method of recording, erasing or reproducing data in an optical memory having a preformat portion in which addresses and the like are recorded in advance and a data portion in which arbitrary data can be recorded In the automatic gain control device of the optical memory device, which is provided in the optical memory device for performing the control and adjusts the gain based on the control voltage generated according to the amplitude of the reproduced signal, the gain of the reproduced signal reproduced from the preformat unit is adjusted. And a second auto gain control section for adjusting the gain of a reproduction signal reproduced from the data section, and reproducing only the second auto gain control section. A recorded area determining means for determining a recorded area of information at Based on constant, an unrecorded area of the information is a configuration in which the holding means for holding the control voltage is provided.

As described above, in the second embodiment, when the optical memory is divided into the preformat section and the data section, the data section includes:
Normally, there are a recorded area and an unrecorded area. However, since information such as an address is always recorded in the preformat section, the preformat section usually determines the recorded area and the unrecorded area. In view of the fact that it is not necessary to hold the auto gain control device, a first auto gain control unit that adjusts the amplification degree of the reproduction signal reproduced from the preformat unit, and the amplification degree of the reproduction signal reproduced from the data unit A second automatic gain control unit for adjusting, a recorded area determination unit for determining a recorded area of information only at the time of reproduction only in the second auto gain control unit, and based on the determination of the recorded area determination unit,
A holding means for holding the control voltage in an unrecorded area of information is provided.

As a result, the recorded area determining means and the holding means are not required in the first auto gain control section for the preformat section, so that the configuration of the first auto gain control section for the preformat section is simplified. Can be.

Further, in the second aspect of the present invention, if a response speed changing means for changing the response speed of the first auto gain control unit in multiple stages is provided, for example, the automatic gain control as in the above-described test write is performed. By increasing the response speed of the first auto gain control unit when detecting the control voltage of the apparatus, for example, it is possible to cope with a change in the amplitude of the reproduced signal at minute intervals such as in units of sectors. On the other hand, when normal information is reproduced, by setting a low response speed, the influence of a defect pulse or the like can be reduced to reduce a reproduction error.

[Brief description of the drawings]

FIGS. 1 to 32 and FIGS. 39 to 45 show an embodiment of the present invention. FIG. 1 is a flowchart showing a procedure of AGC voltage hold control in the AGC amplifier. FIG. 2 is an explanatory diagram showing a logic circuit for performing AGC voltage hold control in the preformat AGC amplifier. FIG. 3 is an explanatory diagram showing a logic circuit for performing AGC voltage hold control in the MO signal AGC amplifier. FIG. 4 is a circuit diagram showing a preformat AGC amplifier. FIG. 5 is a circuit diagram showing an AGC amplifier for MO signals. FIG. 6 is a circuit diagram showing a response speed changing and resetting circuit. FIG. 7A is a block diagram showing a preformat waveform processing unit. FIG. 1B is a block diagram showing the MO waveform processing unit. FIG. 8 is an explanatory diagram showing a relationship among a reproduction signal, a VCA output signal, an AGC voltage, and the like. FIG. 9 is an explanatory diagram showing a schematic configuration of a magneto-optical disk device. FIG. 10 is a block diagram showing a recording circuit. FIG. 11 is a block diagram showing a reproducing circuit. FIG. 12 is a block diagram showing a main part of the controller. FIG. 13 is a block diagram showing a semiconductor laser drive circuit. FIG. 14 is an explanatory diagram showing switching timing at the time of recording of a high-frequency superposition switch signal and the like. FIG. 15 is an explanatory diagram showing switching timing at the time of reproducing a high-frequency superimposed switch signal and the like. FIG. 16 is a block diagram showing a timing generation circuit. FIG. 17 is a block diagram showing a configuration of a sector mark detection circuit. FIG. 18 is an explanatory diagram showing a procedure for detecting a sector mark. FIG. 19 is an explanatory diagram showing waveforms at various parts in the timing generation circuit. FIG. 20 is a block diagram showing a configuration of a signal processing circuit. FIG. 21 is an explanatory diagram showing waveforms at various parts in the signal processing circuit. FIG. 22 is an explanatory diagram showing a relationship between a mark and a non-mark and a reproduction signal and the like. FIG. 23 is an explanatory diagram showing a general configuration of a pulse group detection circuit. 24 to 26 are explanatory diagrams each showing a specific example of the pulse group detection circuit. FIG. 27 is an explanatory diagram showing another most preferred configuration of the pulse group detection circuit. 28 and 29 are explanatory diagrams each showing a specific example of the pulse group detection circuit corresponding to FIG. 27. FIG. 30 is an explanatory diagram showing the relationship between various signals and a recorded area and an unrecorded area. FIG. 31 is a block diagram showing a main part of the controller. FIG. 32 is a block diagram showing a modulation circuit. FIG. 39 is an explanatory diagram showing a relationship between a mark size and a recording light amount. FIG. 40 is an explanatory diagram showing the relationship between the mark size and the recording pulse length. FIG. 41 is an explanatory diagram showing the relationship between the size of a mark and the amplitude of a reproduced signal. FIG. 42 is an explanatory view showing the procedure of the test light. FIG. 43 is a graph showing the relationship between the AGC voltage and the degree of amplification. FIG. 44 is a graph showing the relationship between the PP value of the signal amplitude and the AGC voltage. FIG. 45 is a graph showing the relationship between the mark length and various characteristics. FIGS. 33 to 38 and 46 to 48 show a conventional example. FIG. 33 is an explanatory diagram showing a recording operation in the magneto-optical disk device. FIG. 34 is an explanatory diagram showing a reproducing operation in the magneto-optical disk device. FIG. 35 is a schematic plan view of a magneto-optical disk. FIG. 36 is an enlarged view of a main part of FIG. FIG. 37 is an explanatory diagram showing a reproduction processing system. FIG. 38 (a) is an explanatory diagram showing the relationship between the polarities of two reproduced signals in the MO section. FIG. 38 (b) is an explanatory diagram showing the relationship between the polarities of two reproduced signals in the preformat section. FIG. 46 is an explanatory diagram showing a relationship between a reproduced signal and a VCA output signal and the like. FIG. 47 is a perspective view showing an access operation. FIG. 48 is an explanatory diagram showing a reproduction signal waveform at the time of access and at the time of reproduction. 17 is a pulse group detection circuit (recorded area detection means), 65 is an AGC amplifier for preformat (first auto gain control unit), 75 is an AGC amplifier for MO signal (second auto gain control unit), 91 is Inverter (first control means), 93 is a hold circuit (second control means or hold means), 101 is a response speed change / reset circuit (response speed change means), 1201 is a magneto-optical disk (optical memory), and 3002 is
The MO section (data section) and 3003 are a preformat section.

Claims (4)

(57) [Claims] 1. An automatic gain control device for an optical memory device, provided in an optical memory device for recording, erasing or reproducing data in an optical memory, wherein the amplification degree is adjusted based on a control voltage generated according to the amplitude of a reproduced signal. A first control means for holding the control voltage at the time of recording or erasing; a recorded area determining means for determining a recorded area of information at the time of reproduction; and a non-recording of information based on the determination of the recorded area determining means. And a second control means for holding the control voltage in a region, wherein the first control means holds the control voltage in preference to the second control means. Automatic gain control device for the device. 2. An automatic gain control device for an optical memory device according to claim 1, further comprising a response speed changing means for changing a response speed of said automatic gain control device in multiple stages. 3. An optical memory device for recording, erasing or reproducing data in an optical memory having a pre-format part in which an address or the like is recorded in advance and a data part in which arbitrary data can be recorded, according to the amplitude of a reproduced signal. An auto gain control device for an optical memory device that adjusts an amplification degree based on a generated control voltage, wherein a first auto gain control unit for adjusting a gain of a reproduction signal reproduced from the preformat unit; A second auto gain control section for adjusting a gain of a reproduction signal reproduced from the data section, and a recorded area determination for determining a recorded area of information at the time of reproduction only in the second auto gain control section Means for holding the control voltage in an unrecorded area of information based on the determination by the recorded area determination means. And an automatic gain control device for the optical memory device. 4. The automatic gain control device for an optical memory device according to claim 3, further comprising a response speed changing means for changing the response speed of the first auto gain control unit in multiple stages.