JPH03102641A - Automatic gain controller for optical memory device - Google Patents

Abstract

PURPOSE:To always apply reproduction properly by discriminating whether a signal is a data recorded or a defect pulse with a reproduction signal state discrimination means. CONSTITUTION:A reproduction signal state discrimination means 105 consists of a shift register making up of plural D flip-flops 106 and a pattern comparator circuit 107 compares a signal corresponding to plural consecutive bits in a synchronizing data 2513 outputted from output terminals O with a pattern of a VFO mark. Since the reproduction signal state discrimination means 105 discriminating whether or not a reproduction signal is a recorded data is provided in this way, whether a recorded area of current information is reproduced or an unrecorded area is reproduced is discriminated and when an information pulse group exists, whether it is a recorded data or a defect pulse is also discriminated. Thus, the reproduction of the information in the recorded area is always implemented properly.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic gain control device that is installed in an optical memory device that performs recording, erasing, or reproduction in an optical memory, and that adjusts the gain according to the amplitude of a reproduced signal. It is.

[Conventional technology]

Conventional optical memory devices will be described below, taking as an example a magneto-optical memory device that performs recording, erasing, and reproduction on a magneto-optical disk.

As shown in FIG. 34(a), the magneto-optical disk has a recording magnetic Jfl2805 film formed on a disk substrate 2804. The recording magnetic film 2805 is formed so that the axis of easy magnetization is perpendicular to the film surface, and the direction of magnetization shown by the arrow in the recording magnetic film 2805 is predetermined (for example, in the same figure). It is initialized so that the direction of magnetization is A).

During recording, a laser beam 2803 emitted from a semiconductor laser 2801 is focused by an objective lens 2802 to a diameter of about 1 μm, and is irradiated onto a recording magnetic film 2805.

At that time, a recording signal 2807 corresponding to the information to be recorded
The strength of the light intensity of the laser beam 2803 is controlled based on the following (see FIG. 2(b)). The temperature of the region irradiated with the high-intensity laser beam 2803 locally increases to exceed the Curie temperature, and the coercive force of that region decreases significantly. As a result, the direction of magnetization in the region where the coercive force has decreased is reversed to the same direction as the externally applied magnetic field 2806 applied simultaneously with the irradiation of the laser beam 2803 (direction of magnetization B in the figure). In this way, information corresponding to the recording signal 2807 is recorded on the recording magnetic film 2805. Below, mark 2 is the part where the magnetization in direction B is recorded as described above.
809, and a portion where magnetization in the other direction 8 is recorded is referred to as a non-mark 2810.

Erasing information recorded on the recording magnetic film 2805 is performed in the same manner as during recording by reversing the direction of the externally applied magnetic field 2806 from that during recording, and changing the direction of magnetization to the original initializing direction (i.e., This is carried out by returning the magnetization direction A). As a result, the erased portion is a non-mark 281
It becomes 0.

Note that in this example, the laser beam 2803 is used as the recording signal 280.
Externally applied magnetic field 2806 of constant strength modulated according to 7
In addition to this, there is a magnetic field modulation method in which the intensity of the laser beam 2803 is kept constant and the direction of the externally applied magnetic field 2806 is modulated according to the recording signal 2807. You may record it.

The disk substrate 2804 is made of glass or plastic, and as shown in FIG. 34(a), address information indicating the addresses of tracks and sectors is carved in advance as physical irregularities 2808. There is.

Since the above address information is inscribed in advance in a certain format, recording and erasing operations cannot be performed thereafter. The portion carved in advance as physical unevenness 2808 will be referred to as a preformat portion 3003 hereinafter. On the other hand, each operation of recording and erasing information is performed in a portion other than the format section 3003, and this section is referred to as an MO (magneto-optical) section 3002. Usually, the preformat section 3003 and the MO section 3002 are arranged alternately on spiral or concentric tracks 3005, as shown in FIG. The preformat section 3003 and the MO section 3002 form one sector 30 as a pair.
It consists of 04.

The magneto-optical disk 3001 has a large number of sectors 3 on a track 3005, each of which is assigned address information.
004, and each operation of recording, reproducing, and erasing information is performed in units of 3004 sectors.

Further, as shown in FIG. 37, in the preformat section 3003 on the track 3005, either the concave part or the convex part of the concavo-convex part 2808 in FIG.
and the other of the concave part or the convex part is a non-mark 2
It consists of 8l2.

Furthermore, as mentioned above, the MO section 3002 has an MO (magneto-optical)
Signal mark 2809 and non-mark 2910 in between
will be recorded.

Next, when reproducing the magneto-optical disk 3001, as shown in FIG. 8 0 5
is irradiated. However, the light intensity of the laser beam 2803 is made weaker than during each recording and erasing operation. When the reflected light of the linearly polarized laser beam 2803 from the magneto-optical disk 3001 passes through or is reflected by the recording magnetic film 2805, its plane of polarization is rotated by the Faraday effect or the Kerr effect. This direction of rotation is between mark 2809 and non-mark 28
10, they rotate in opposite directions. Reproduction is performed by detecting this difference in polarization direction. As a result, for example, two types of reproduction signals S1 and S2 as shown in FIGS. 3(b) and (c) are generated.

Next, to briefly explain the reproduction optical system for obtaining the above-mentioned reproduction signals S1 and S2, as shown in FIG.
(Analyzer) 3202 and two detected light beams 3210
・3211 has two photodetectors 3 for each polarization direction
Guided by 203/3204. And photodetector 320
3 and 3204, the signals are converted into electrical signals that vary depending on the light intensity, and output as reproduced signals S1 and S2. As will be detailed later, the above reproduced signals S1 and S2
By adding and operating , the preformat section 3
003 and the signal of the MO section 3002 can be obtained separately, and furthermore, the mark 2809 and the non-mark 2810 can be read out separately from the signal of the MO section 3002, so that the information recorded on the recording magnetic film 2805 can be reproduced. It can be performed. As shown in FIG. 39, if the reflected light vector from the non-mark 2810 (magnetization direction A) in the MO section 3002 is α, and the reflected light vector from the mark 2809 (la orientation B) is β, then α and β is a reflected light vector rotated in opposite directions by the rotation angle of the plane of polarization. The reflected light vectors α and β are respectively detected in two polarization directions XSY by an analyzer CPBS) 3202. These two polarization directions X and Y are perpendicular to each other. The magnitudes of detected light vectors ακ and β7, which are obtained by projecting the reflected light vectors α and β in the polarization directions X and Y, respectively, correspond to the reproduced signal S1 and the reproduced signal S2. Furthermore, the detection light vector α
8 and β9 correspond to detected light beams 3210 and 3211 in FIG. 38, respectively.

As is clear from FIG. 39, the reproduced signal S1 corresponds to the non-mark 2810 at a high level and corresponds to the mark 2809 at a low level. On the other hand, the reproduced signal S2 has a low level corresponding to the non-mark 2810 and a high level corresponding to the mark 2809, and has a polarity opposite to that of the reproduced signal S1. The reproduced signals 31-32 are
In order to improve the S/N ratio, the signal is input to a differential amplifier, where it is amplified differentially and the information is reproduced. Next, based on FIG.
The reproduced signals S1 and S2 reproduced from the following will be described. Since recording and erasing operations are not performed in the preformat section 3003, the direction of magnetization is only A. In the brief format section 3003, a mark 281 consisting of unevenness 2808
1 and the shape of the non-mark 2812 cause diffraction of the laser beam. Therefore, as shown in FIG. 40, the reflected light vector becomes a long reflected light vector α (corresponding to the reproduction of the non-mark 28l2) and a short reflected light vector T (corresponding to the reproduction of the mark 2811) depending on the unevenness 2808. Become.

By projecting this onto the polarization directions X and Y of the analyzer (PBS) 3202, analyzer vectors α8 and γ are obtained, respectively. The magnitude of the analyzer vector α8, γ is the reproduced signal S1・
Compatible with S2. Both reproduced signals S1 and S2 are
The non-mark 2812 due to the unevenness 2808 corresponds to a high level, and the mark 2811 corresponds to a low level. Therefore, unlike the case of the magneto-optical recording mark 2809 and non-mark 28lO shown in FIG. 39, the reproduced signals S1 and S2 have the same polarity. That is, Fig. 35 (
b) As shown in (C), the reproduced signals S1 and S2 have the same polarity in the BRI format section 3003, and the MO
In the section 3002, the signals are inverted in polarity.

Therefore, by adding the reproduced signals S1 and S2, only the signal of the BR format section 3003 is obtained, and the reproduced signal Sl-
32 makes it possible to obtain only the signal of the MO section 3002, and in this way, it is possible to improve the S/N ratio.

The differential signal or addition signal from the above two types of reproduced signals S1 and S2 is output to an auto gain control amplifier (hereinafter referred to as A).
It is conceivable to amplify the signal using a GC amplifier (referred to as a GC amplifier) while adjusting the degree of amplification so that the amplitude after amplification is approximately constant. The above AGC amplifier includes, for example, a voltage control amplifier (hereinafter referred to as vCA) 11 whose amplification degree changes based on a control voltage (hereinafter referred to as AGC voltage), as shown by reference numeral 10 in FIG. Signal level detection circuit 12 that generates a voltage according to the level of the signal output by VCA II
and V detected by this signal level detection circuit 12.
A is output from the operational amplifier 13 which outputs the AGC voltage proportional to the difference between the output signal level of the CAII and a preset reference signal level.
By inputting the GC voltage to the VCA II, the level of the reproduced signal is feedback-controlled and kept almost constant.

[Problem that the invention seeks to solve]

However, in the above magneto-optical disk 3001, information consisting of an MO signal is not necessarily recorded in the MO section 3002 of all sectors 3004, and there are usually some MO sections 3004 in which no information is recorded. .

In that case, when the current playback position is the sector 3004 in which no information is recorded, the AGC amplifier 10
In response to a low-level reproduction signal that does not include the pulse group consisting of the O signal, the amplification degree of the VCA II becomes excessive. In that case, when the reproduction position approaches the sector 3004 where information is recorded and the reproduction signal containing the information pulse group by the MO signal begins to be input to the VCA II, the amplification degree does not immediately reach the reproduction signal level. I can't follow.

That is, the reproduced signal containing the pulse signal (Fig. 42(a)
For example, immediately after the input
As shown in the figure, the output signal level of VCA II increases significantly. As a result, a problem arises in which a normal reproduction signal cannot be obtained until the amplification degree follows the reproduction signal level and reaches an appropriate amplification degree.

On the other hand, if the surface of the magneto-optical disk 3001 is scratched or has dust attached to it, the VC may appear in the unrecorded area of the reproduced signal as shown in FIG. 43(a).
A defective pulse 41 may be included in the input signal of AII. When the AGC amplifier IO responds to this defect pulse 41, the amplification degree of VCA II becomes too small, but by the time the too small amplification degree returns to the proper amplification degree, it takes longer than when the amplification degree becomes too large. , which takes a longer time.

Therefore, after the defect pulse 41 is generated,
As shown by ■ in the same figure (b), VCA
The output signal level of II will drop significantly, and a normal reproduction signal will no longer be obtained.

Moreover, the MO section 3 on which information is not recorded on the magneto-optical disk 3001
In order to suppress fluctuations in the amplification degree of the AGC amplifier 10 caused by the presence of 002, a pulse group detection circuit is provided in the MO section 3002 to detect whether or not an information pulse group is present. In the unrecorded area where the information pulse group does not exist, the AGC voltage immediately before entering the unrecorded area is held to keep the amplification degree of VCA II constant, and then the recorded area where the information pulse group exists is reached. At times, it may be possible to release the hold on the AGC voltage.

According to this method, irregular fluctuations in the amplification degree of the AGC amplifier 10 due to the presence of unrecorded areas can be substantially suppressed.

However, in that case, the defective pulse 41 described above may be erroneously determined to be an information pulse group, and the hold on the AGC voltage may be released. In particular, if the amplification degree is set to be maximum when the AGC amplifier 10 is reset, the AGC amplifier 10 may respond to the defect pulse 4l immediately after the AGC amplifier 10 is reset or immediately after the magneto-optical disk drive itself is started. The quality of the product is particularly high.

In that case, depending on the amplitude of the defect pulse 41, the AG
The amplification degree of C amplifier 10 fluctuates, and the defective pulse 4
Since the amplification degree is fixed at the point when the MO signal ends, problems are likely to occur in the reproduction of information by the MO signal when the next recorded area is reached. In particular, Defect Vals 4
1 has a large amplitude, the amplification degree of the AGC amplifier 10 is fixed at an extremely small value when the defect pulse 41 ends, so even when the next recorded area is reached,
There is a possibility that recorded information cannot be reproduced due to insufficient amplification. In such a case, the amplification degree continues to be fixed at the extremely small value at the end of the defect pulse 4l, so information cannot be reproduced unless the AGC amplifier 1o or the magneto-optical disk device itself is reset. The condition continues.

As described above, if the pulse group detection circuit is used, the AGC
Although the reliability of the amplifier 10 can be improved to some extent, it is difficult to provide a complete countermeasure against the defective pulse 41 and the like.

Note that, in general, optical memories such as magneto-optical disks are characterized in that the above-mentioned defective pulses occur more frequently than magnetic disks. Therefore, it is necessary to take special measures to prevent errors in reproduced information caused by defective pulses.

[Means to solve the problem]

In order to solve the above-mentioned problems, an automatic gain control device for an optical memory device according to the present invention is provided in an optical memory device that performs recording, reproduction, or erasing in an optical memory, and adjusts the degree of amplification according to the amplitude of a reproduced signal. In an automatic gain control device, a reproduced signal state determining means determines whether the reproduced signal represents recorded data based on the reproduced signal state, and the reproduced signal is recorded by the reproduced signal state determining means. control means for causing the automatic gain control device to adjust the amplification degree when it is determined that the reproduced signal represents the recorded data, and for fixing the amplification degree when it is determined that the reproduced signal does not represent the recorded data. It is characterized by the fact that it is equipped with

[For production]

According to the above structure, since the reproduced signal state determining means is provided to determine whether the reproduced signal is recorded data, the reproduced signal state determining means determines whether the recorded area of information is currently being reproduced or not. It becomes possible to determine whether the information pulse group is being recorded or whether an unrecorded area is being reproduced, and it can also be determined whether the information pulse group is recorded data or a defective pulse when it exists. . Therefore, based on the determination result of the reproduced signal condition determination means, the amplification degree is adjusted by the automatic gain control device only in the area where information has been recorded, and in the unrecorded area or when a defective pulse occurs, the amplification degree is adjusted from the previous recording. By fixing the value to the value at the end of the recorded area, it becomes possible to always properly reproduce information in the recorded area.

Note that the reproduction signal state determination means determines the data portion by, for example, detecting a certain pattern in the case where a certain pattern is recorded together with the data in the optical memory in order to synchronize the data reproduction of the optical memory, or If the data is modulated according to a certain modulation rule, it is determined whether the information contained in the reproduced signal is data by detecting whether it conforms to the above modulation rule, or If an error detection code is added to the data, a method such as detecting the location where the data is recorded by detecting the error detection code may be used.

[Embodiment 1] An embodiment of the present invention will be described below based on FIGS. 1 to 33.

First, a magneto-optical disk 1201 as an example of optical memory
A magneto-optical disk device comprising an optical memory device for recording, reproducing and erasing information will be described below.

As shown in FIG. 10, a magneto-optical disk 120l is rotationally driven by a spindle motor 1202, and data is recorded, reproduced, and erased by a laser beam 1204 emitted from an optical head 1203. During recording or erasing, an external magnetic field is applied from an external magnetic field applying magnet 1205 at the same time as the laser beam 1204 is irradiated. Note that the direction of the external magnetic field during recording and erasing can be reversed, for example, by rotating the external magnetic field applying magnet 1205 with a motor or the like (not shown). In addition, the external magnetic field applying magnet 1205 is an electromagnet to perform recording and recording.
The direction of the external magnetic field may be reversed during erasing.

During recording, the semiconductor laser 280 in the optical head 1203
1 (see FIG. 11), a semiconductor laser drive current 1210 is input from the recording circuit 1206. The light intensity of the semiconductor laser 2801 is appropriately controlled by the semiconductor laser drive current 1210.

Also, during playback, the playback circuit 12 is connected from the optical head 12o3.
A reproduced signal 1211 (consisting of two types of reproduced signals S1 and S2 as shown in FIG. 35) is output to 07. Reproduction data 1212 reproduced by reproduction circuit 1207 is sent to controller 1208.

The controller 1208 determines the timing of various control signals 1213 based on the reproduction data 1212, and sends these control signals 12l3 to the recording circuit 1206 and the reproduction circuit 1207. Further, a magnetic field control signal 1214 is transmitted from the controller 1208 to the external magnetic field applying magnet 1205, and the direction of the external magnetic field is controlled.

As shown in FIG. 11, the recording circuit 1206 includes a modulation circuit 1302, and a controller 1208 (FIG. 10).
The recording data 1311 sent from the controller is input to the modulation circuit 1302. In the modulation circuit 1302,
Recorded data 1311 is converted into modulated data 1310 according to the recording format by a control signal 1213. This modulation is performed, for example, according to 2,7 modulation method 2, which will be described later.

Modulation data 1310 is transmitted to semiconductor laser drive circuit l301
Based on this, the semiconductor laser drive circuit 13
01 to the semiconductor laser drive voltage ffll 2 1 0
is output, and the semiconductor laser 280 in the optical head 1203
transmitted to l. At the same time, the control signal 12 from the controller 1208 is sent to the semiconductor laser drive circuit 1301.
13 is input, and the light intensity of the semiconductor laser 2801 is appropriately controlled according to each recording, reproducing, and erasing operation.

Further, as shown in FIG. 12, the reproducing circuit 1207 includes a signal processing circuit 1401, and the optical head 1203 (10th
Reproduction signal 1211 from (Fig.) (Reproduction signal S1/32)
is input to the signal processing circuit 1401, where synchronization is achieved. From the signal processing circuit engineer 401, synchronization data l41
0 is sent to the demodulation circuit 1402, and at the same time, a sector mark signal 141l is sent to the controller l208. Demodulation of the synchronous data 1410 is performed by the modulation circuit 1302 in FIG.
This is achieved by performing the opposite transformation. The controller 1 is connected to the signal processing circuit 1401 and the demodulation circuit 14o2.
Various control signals 1213 are transmitted from 208 . Demodulated reproduced data 12l2 is output from the demodulation circuit 1402 to the controller 120B.

As shown in FIG. 13, the controller 1208 includes a timing generation circuit 1501. Sector mark signal l41 from signal processing circuit 1401 (Fig. 12)
1 is manually inputted to a timing generation circuit 150l, where a reference timing signal 151o is generated at the timing of each sector and transmitted to the control circuit 1502. Also, reproduced data 1 from the demodulation circuit 1402 (Fig. 12)
212 is input to the control circuit 15o2. The control circuit 15o2 generates various control signals 1213 from the above two types of input signals, and also inputs and outputs information to and from external devices.

The modulation circuit 13o2 in FIG. 11 performs modulation based on the modulation method shown in Table 1, for example.

This is the so-called 2.7 modulation method,
The input data (recorded information) shown in the left column of Table 1 is converted into the predetermined modulation data shown in the right column of the same figure. At this time, in the modulation data, the number of consecutive '0' bits is 2 to 7 bits. For example, the first
According to the sector format shown in FIG. 5(a), modulated data 1310 is outputted to the semiconductor laser drive circuit 1301 in FIG. 11 with appropriate timing.

In Table 1, FIG. 15(a), the briformat portion 3003
consists of a sector mark section 1701 for obtaining synchronization timing in units of sectors, and an ID section 1702 containing sector address information. These are the 34th
As shown in figure (a), mark 2 that cannot be recorded or erased
Physical unevenness 2 corresponding to 811 and non-mark 2812
808 is engraved on the magneto-optical disk l201. The MO section 3002 as a data section consists of a data section 1703 for recording, reproducing, and erasing information data, and a pair of gap sections 1704 and 1705 located before and after the data section 1703.

Then, the modulation data 1310 is recorded in the data section 1703. The recording at this time is a mark 2809 and a non-mark 2 by the MO signal, as shown in FIG. 34(a).
810. In addition, the briformat section 3003
and the above-mentioned gap portion 1 disposed between the MO portion 3002
704 and 1705 are free areas for recording information in the data section 1703. In other words, these gap parts 1
704 and 1705 are areas in which the recording start position and recording end position shift back and forth due to the phase error that occurs between the rotation of the spindle motor 1202 and the synchronized timing of the sector 3004 unit, so this is taken into account. be.

As shown in FIG. 14, the semiconductor laser drive circuit 13
01 includes a recording/erasing light amount control circuit 1803, and this recording/erasing light amount control circuit 1803 includes a modulation circuit 1302.
From (FIG. 11), modulation data 1310 is input to the semiconductor laser drive circuit 1301. Further, a reproduction light amount control signal 1810 is input from the controller 1208 (FIG. 10) to the reproduction light amount control circuit 1801, and the semiconductor laser 2801 in the optical head 1203 is inputted during reproduction.
The reproduction light amount is appropriately controlled.

Recording/erasing light amount control signal 1 from controller 1208
811 is input to a recording/erasing light amount control circuit 1803, and the light amount of the semiconductor laser 2801 corresponding to recording and erasing is controlled. Furthermore, the high frequency superposition switch signal 1812 from the controller 1208 is input to the high frequency superposition circuit 1802, and based on this, the high frequency superposition circuit 1802 generates an output signal 1816 that is turned on and off at high frequency, and the adder 1805 generates an output signal 1816 that is turned on and off at high frequency. By being superimposed on the output signal 1814 of the reproduction light amount control circuit 1801, the noise of the semiconductor laser 2801 caused by the return light from the magneto-optical disk 1201 is reduced. Note that the output signal 1816 of the high frequency superimposing circuit 1802 is output to the adding circuit 1805 only during reproduction.

Reproducing light amount control circuit 1801, recording/erasing light amount control circuit 1
803 and each output signal 18 of the high frequency superimposition circuit 1802
14 to 1816 are added by an adding circuit 1805, and a semiconductor laser drive current 1210 is input to the semiconductor laser 2801. The light amount (light intensity) of the semiconductor laser 2801 is
A photodetector 1806 in the optical head 1203 converts the light into an electrical signal that changes according to the intensity of the light, and a light amount monitor signal 1813 is transmitted to the controller 1208 via a light amount monitor circuit 1804. In the controller 1208, based on the light amount monitor signal 1813, the above-mentioned reproduction light amount control signal 1810, recording/erasing light amount control signal 181l and high frequency superimposition switch signal 1 are transmitted.
812 is output. In other words, the light intensity (amount of light) of the semiconductor laser 2801 is controlled to be appropriate during reproduction and during recording/erasing.

Next, to explain each operation of recording and erasing information, the 15th
As shown in Figure (b), the high frequency superimposed switch signal 181
2 is at a low level ('0'') in the normal use range 1703 (see (a) in the same figure), and is at a high level ('1') at other parts. That is, the MO section 300
High frequency superimposition circuit 180 in data section 1703 in 2
2 is turned off, and turned on except for the data section 1703. Along with this, as shown in FIG.
703, it is recorded as an MO signal. At this time, as shown in FIG. 4(d), the light amount level (light intensity) 1910 of the semiconductor laser 2801 becomes a high level in the data portion 1703, and becomes a low level in other areas. In other words, sector synchronization timing is detected from the sector mark section 1701 in the flash formatting section 3003, address information etc. are read out from the ID section 1702, and a predetermined address (
Information is recorded and erased in the MO section 3002 while checking the address).

On the other hand, when reproducing information recorded in the data section 1703, as shown in FIG. 16(b), the preformat section 1703
The high frequency superimposed switch signal 1812 is at a high level (“l”) in both the MO section 3003 and the MO section 3002. Further, since no recording is performed, the modulated data l310 is at a low level ("O") as shown in FIG.

Furthermore, as shown in FIG. 2(d), the light amount level 1910 is a low level. In other words, the briformat section 3003
The synchronization timing of the sector 3004 is detected from the sector mark section 1701 (in (a) of the same figure), and the address (address) information etc. is read out from the ID section 1702, and while checking the predetermined address (address) one after another, the MO section 3002 to MO
Information recorded as a signal is reproduced.

More specifically, as shown in FIG. 17, the timing generation circuit 1501 in FIG. 13 is a signal processing circuit 1401 (
The sector mark detection circuit 2101 is provided with a sector mark detection circuit 2101 to which a sector mark signal 1411 outputted from the circuit shown in FIG. 12 is input. The sector mark detection circuit 210t detects the presence or absence of a sector mark, and outputs a sector mark detection signal 2110 based on the detection. Sector mark detection signal 211
0 is transmitted to the counter 2102, timer circuit 2104, and determination circuit 2106, respectively.

The output signals 2111 and 2112 of the counter 2102 and the timer circuit 2104 are respectively input to the switch circuit 2103, and the switch circuit 2103 selects one of the output signals 2111 and 2112 and outputs it as the reference timing signal 1510.

This reference timing signal 1510 is also input to the data portion determination circuit 2107, and based on this, a data portion determination signal 2116, which will be described later, is output. Timer circuit 210
4, another output signal 2113 is transmitted to the window generation circuit 2105. The output signal 2114 of the window generation circuit 2105 is input to the determination circuit 2106.

The determination circuit 2106 generates a timing determination signal 211 from the output signal 2114 and the sector mark detection signal 2110.
5 (described later) is output. Timing judgment signal 2115
Therefore, in the switch circuit 2l03, the counter 2102
Either the output signal 21l1 of the timer circuit 2104 or the output signal 2112 of the timer circuit 2104 is selected. The reference timing signal 1510, the data section determination signal 2116, and the timing determination signal 2115 are each supplied to the control circuit 15.
02 (Figure 13). Control circuit 1
502, based on the various signals 1510, 2115, 2116 outputted from these timing generation circuits 1501 and the reproduction data 1212, the various control signals 1213 described above are transmitted to the recording circuit 1206 and the reproduction circuit 1207 (
(Fig. 10), and each control of recording, reproduction, and erasure of information is performed.

As shown in FIG. 18, the sector mark detection circuit 21
01 includes a counter circuit 2201 and a signal processing circuit 14
Sector mark signal 1 output from 01 (Figure 12)
411 monitors the counter circuit 2201, for example,
9 counter numbers. 1~NO. 9. Counter No. 1~No. 9 output signals 2211 to 221
9 are respectively transmitted to a determination circuit 2202, and a sector mark detection signal 2110 is output based on the determination result of the determination circuit 2202. As described above, the sector mark detection circuit 2101 detects the sector mark portion 1701 (for example,
Detection of Fig. 15(a)), recording/playback/recording/playback in sector units
This circuit obtains the synchronization timing necessary to perform each erase operation.

The operations of counters No. 1 to No. 9 in the counter circuit 2201 will be explained based on FIG. 19. Here, the pattern of the sector mark portion 1701 is, for example, a mark 2811 and a non-mark 28 as shown in FIG.
12. In this example, as shown in Figure (a), multiple marks are created so that the ratio of mark length and non-mark length is in the order of 5:3:3:7:3:3:3:3:5. 2811 is engraved.

The sector mark signal l411 obtained by reproducing the pattern of marks 2811 and non-marks 28l2 is shown in FIG.
As shown in , for example, the low level (゛0
”), and is converted into a binary signal with a high level (“'1”) in the non-marked portion.

The sector mark signal 1411 is the counter No. 1-N.
o. When each input is made to counter No.9, first, counter No.9 is input.
1 (see (e) in the figure) counts the number of clocks of the counter clock 2310 corresponding to the mark length "5". The counter clock 2310 has a higher frequency than the sector mark signal 1411, as shown in FIG. 2(d). If this count is within a predetermined range, it means that the first mark 2811 (mark length u5'') has been detected accurately.

Next, counter No. 2, a non-mark 2812 with a non-mark length of "3" is detected in the same way. In this way, the mark 2811 and the non-mark 2812 of the sector mark part 1701 are detected in sequence, and finally the mark length of "5" is detected.
Counter No. 9 detects. The detection signals 2211 to 2219 of the nine marks 28l1 or non-marks 2812 obtained as described above are sent to the determination circuit 2202 (FIG. 18).

Then, these nine marks 2811 or non-marks 281
It is determined whether or not all or part of the detection results for 2 match the pattern of the sector mark portion 1701.
2 is determined. As a result, the sector mark portion 17
Only when it is determined that it is 0l, the sector mark detection signal 21lO becomes low level ("0"). The sector mark detection signal 2110 obtained as described above can be used as synchronization timing for each sector 3004.

Next, based on FIG. 20, the timing generation circuit 1501
The waveforms of each part of will be explained below.

As shown in FIG. 2(b), the sector mark detection signal 211
0 becomes low level when detecting the sector mark section 1701 ((a) in the figure) in the format section 3003, and this sector mark detection signal 211o
The falling edge of is the synchronization timing of sector 3004. The counter 2102 receives the sector mark detection signal 2.
After counting a predetermined number of counts from the falling edge of 110, the counter output signal 2 is output as shown in FIG.
Set 111 to low level.

On the other hand, the count number of the timer circuit 2104 is calculated by adding the count number of the counter 2102 to one sector 300.
It is set to be larger by the sector length of 4.

Therefore, as shown in FIG. 20(d), the timer circuit 21
The falling edge of the o4 output signal 21l2 almost coincides in timing with the falling edge of the counter output signal 2l11 of the next sector 3004.

Further, as shown in FIG. 2(e), the window generation circuit 21
The output signal 2114 of 05 is the sector mark detection signal 21
Based on the falling edge of 10, the next sector 3004
The sector mark detection signal 2110 becomes low level with a predetermined window width near the falling edge. If a falling edge of the sector mark detection signal 2110 exists when the output signal 2114 of the window generation circuit 2105 is at a low level, the timing determination signal 2115, which is the output signal of the determination circuit 2106, will change to the solid line in FIG. As shown in , the level has reached a high level. On the other hand, sector mark detection signal 2
If there is no falling edge of 110, the signal becomes low level (indicated by the dotted line in FIG. 3(f)). Therefore, the timing determination signal 2115 is a signal that determines whether the sector mark portion 1701 was detected within a predetermined range or whether there was a detection error.

In the switch circuit 2103, the sector mark section 17
If 0l is detected, the counter output signal 21l1
is selected, and if there is a detection error, the timer circuit output signal 2112 is selected.

As a result, as shown in FIG. 3(g), even if a detection error occurs in the sector mark section 1701, the reference tie signal 1510 can be reliably corrected based on the timing of the previous sector 3004. Can be output. The reference timing signal 1510 obtained in this way is transmitted to the data part determination circuit 2107.

The data section determination circuit 2107 is a type of counter, and its output signal, the data section determination signal 2116, is the MO section 3
It becomes a low level in the normal use range 1703 of 002 ((h) in the same figure). In other words, the data section determination signal 2116
can be used as a signal for distinguishing between the BR format section 3003 and the MO section 3002. The reference timing signal 1510 and timing determination signal 2 obtained in this way
115 and data portion generation signal 2116 are transmitted to control circuit 1502 in FIG. In the control circuit 1502, the above signals 1510, 2115 and 2
The various control signals 1213 described above are generated based on the signal 116.

Next, the operation of the signal processing circuit 1401 in FIG. 12 will be explained based on FIGS. 21 to 23. The reproduction signal 1211 (
The reproduced signals S1 and S2) are input to a buffer amplifier 2501 in the signal processing circuit 1401, as shown in FIG. The output signal 2510 of the buffer amplifier 2501 is transmitted to the MO waveform processing section 2502 and the BR format waveform processing section 2503.

From the MO waveform processing unit 2502, marks 2809 and non-marks 281 recorded as MO signals are sent to the MO unit 3002.
While the MOZ value signal 2511 corresponding to 0 is output, the preformat waveform processing section 2503 outputs the mark 2811 and non-mark 28 of the preformat section 3003.
An ID binary signal 2512 corresponding to 12 is output.

These binary signals 251l and 2512 are input to the data synchronization unit 2504, and the P in the data synchronization unit 2504
L L (P8ASE LOCKE!CD LOOP)
, synchronized data 2513 synchronized with the clock is detected and transmitted to the demodulation circuit 1402 (FIG. 12).

Further, the sector mark signal l411 is generated in the flash format waveform processing section 2503, and the sector mark signal l411 is generated in the timing generation circuit 15.
01 (Figure 13).

{The K processing control unit 2505 sends various control signals 2514 to 2517 between each unit in the signal processing circuit 1401.
is input and output. Further, various control signals 1213 are input/output to/from the controller 120 in FIG.

FIG. 22 shows waveforms of each part of the signal processing circuit 1401.

As shown in (b) and (c) of the same figure, the reproduced signals S1 and S2 are differentially generated in the MO waveform processing section 2502, and only the MO signal of the MO section 3002 is separated, and further binarized, and the MO binary signal 2511 ((d) in the same figure). In addition, the reproduced signals S1 and S2 are processed by the preformat waveform processing section 2503.
, only the information in the preformat section 3003 is separated, and further binarized to produce an ID binary signal 2.
512 and sector mark signal 1411 are obtained (same figure (
e) and (g)).

MO section 30 by differential and addition of reproduced signals S1 and S2.
The reason why the preformat section 3003 and the preformat section 3003 can be separated is that the polarities of the reproduced signals S1 and S2 are reversed in the MO section 3002, as shown in FIG. This is because the portion 3003 is the same. The MO binary signal 2511 and the ID binary signal 2512 are each converted into synchronized data 2513 synchronized with a clock in a data synchronization section 2504, as shown in FIG. 22(f).

FIG. 23 explains the waveform of FIG. 22 in detail. For example, the waveform of FIG. 22 is shown in FIG. It is assumed that a mark 2811 (or 2809) and a non-mark 2812 (or 2810) are recorded as shown in FIG. These marks 2811 (
or 2809) and non-7-ku 2812 (or 2 8 1
0) The reproduced signals s1 and s2 are reproduced by the irradiation of the halo laser spot 2701, and as shown in FIG. The MOZ value signal 2511 or the ID binary signal 2512 is a signal that has detected this peak position, and its rising edge coincides with the peak position (see (d) in the same figure). In the PLL in the data synchronization unit 2504, MO2
A synchronous clock is generated from the digitized signal 2511 or the ID binary signal 2512, and synchronous data 2513 is obtained by synchronizing with this clock. As shown in FIG. 4(e), the synchronization data 25l3 is data obtained by faithfully reproducing the modulation data iaio.

FIG. 24 shows the main parts of the BR format waveform processing section 2503. The above-mentioned reproduced signals S1 and S2 are input to the summing amplifier 64 in the BR format waveform processing section 2503, where, as described above, S1 and S2 are added, so that only the information of the BR format section 3003 in the reproduced signal is input. are now separated. The information of this BR format unit 3003 is input to the BR format AGc amplifier 65, where it is amplified with an amplification degree that is approximately inversely proportional to the amplitude so that the amplitude after amplification is approximately constant, and then binarized. The signal is binarized in the circuit 66 and output as an IDZ digitized signal 2512.

Further, FIG. 25 shows the main part of the MO waveform processing section 2502, and the reproduced signal SL-32 is transmitted to the MO waveform processing section 250.
2, where, as mentioned above,
By differentially connecting S1 and S2, the MO in the reproduced signal
Only the signal is separated. The MO signal is
The signal is input to the MO signal AGC amplifier 75, where it is amplified according to the amplitude, and then binarized by the binarization circuit 76, and the MOZ digitized signal 2511 is output. This M.O.
Based on the Z-valued signal 2511, data recorded in the MO section 3002 is recognized.

Next, the test light will be explained.

Mark 28 by MO signal recorded in MO section 3002
The magnitude of 09 changes depending on recording conditions such as the recording light amount, recording pulse length, and externally applied magnetic field 2806.

That is, as shown in FIGS. 26(a) and 26(b), as the amplitude of the recording pulse, that is, the amount of recording light increases, the size of the recorded mark 2809 increases (however, the length of the recording pulse is constant). Furthermore, as shown in FIGS. 27(a) and 27(b), even if the recording pulse length is increased while the amplitude of the recording pulse is held constant, the mark recorded is almost proportional to the recording pulse length. The size of 2809 increases.

As described above, if the sizes of the marks 2809 vary, playback errors may occur. For example, the second
In FIG. 8, under recording conditions in which marks 2809 were recorded with the size shown by the solid line in FIG. 8(a), the S/N ratio was the best as shown by the reproduced signal shown by the solid line in FIG. 8(b). On the other hand, when recording, the size of the mark 28o9 is larger or smaller than the recording light amount (or recording pulse length) corresponding to the solid line. It can be seen that if the amplitude is too large or too small, the amplitude (peak-to-peak value) of the reproduced signal becomes small, as shown by the dotted line in FIG. ). Therefore, in order to obtain error-free reproduced data, it is necessary to optimally control the recording conditions.

Therefore, in order to optimize the recording conditions, the magneto-optical disk 1
It is possible to test record (test write) 201 while sequentially changing the recording conditions to find the conditions that maximize the amplitude of the reproduced signal during reproduction, and then perform subsequent recordings under the recording conditions at that time.

For example, as shown in FIG. 29, recording is performed in eight sectors 3004 of A to H (FIG. 29(a)) while sequentially changing the recording light amount or recording pulse length as shown in FIG. 29(b). At that time, for example, if the recording light intensity is to be changed sequentially, the light intensity monitor signal 1813 is input to the processor 70 in the controller 1208 whose main part is shown in FIG. For example, RAM or E provided in the processor 70
” It is stored in a storage element such as FROM.

After that, as shown in FIG. 29(C), sectors 300 of A-H
The MO signals recorded in 4 are sequentially played back. At this time, for example, each sector 3 at the sample timing shown in Ce) of the same figure.
004, the AGC voltage of the MO signal AGC amplifier 75 (
(d)) of the same figure is sampled and stored in the above-mentioned storage element.

By the way, as shown in FIG. 31, in the MO signal AGC amplifier 75 (described in detail below), in the normal amplitude range of the MO signal consisting of the differential signals S1 and S2, as the amplitude of the MO signal increases, There is a relationship in which the AGC voltage increases, and as shown in FIG. 32, there is a relationship in which the amplification degree of the MO signal ACC amplifier 75 decreases as the AGC voltage increases. Therefore, if the optimal recording condition is the recording condition in which the amplitude of the MO signal before amplification by the MO signal AGC amplifier 75 is maximized (the recording condition in which the degree of amplification is minimized), then the recording condition in which the AGC voltage is maximized is corresponds to the optimal recording condition.

Therefore, the optimum recording condition is determined from the AGC voltage recorded for each sector 3004, and thereafter, during recording, the recording/erasing light amount control signal 18 corresponding to the above-mentioned optimum recording condition is used.
11 and the recording pulse length control signal is sent to the processor 70 (third
Figure 0).

The recording/erasing light amount control signal 1811 is input to the aforementioned recording/erasing light amount control circuit 1803 (FIG. 14), so that the light amount of the semiconductor laser 2801 corresponding to recording and erasing is controlled.

On the other hand, the pulse length control signal is transmitted to the modulation circuit 1302 (11th
(Fig.), and modulation data is controlled based on this.

More specifically, the modulation circuit 1302 has a configuration as shown in FIG. 33, and record data 131l sent from the controller 1208 (FIG. 10) is input to the modulation section 71 in the modulation circuit 1302. The modulation section 71 performs modulation in synchronization with the timing signal, for example, according to the 2.7 modulation method as shown in Table 1. Modulated recording data 1
311 is processed in a recording format unit 72 in synchronization with the timing signal to match the recording format, and further in a recording pulse length control unit 73, modulated data 1310 is generated based on the above-mentioned pulse length control signal. . This modulation data 1310 is output to the semiconductor laser drive circuit 1301 in FIG. transmitted. In this way, the recording pulse length can be controlled.

Next, the structure of the MO signal AGC amplifier 75 as an automatic gain control device will be explained in more detail. Third
As shown in the figure, the MO signal AGC amplifier 75 is mainly connected to a clamp circuit 78, a comparator 79, an AGC voltage generation circuit 80, and a voltage control amplifier (VCA) 77. A differential signal is input to the VCA 77.

The VCA 77 (7) output is sent to the binarization circuit 76 (Fig. 25).
and is also input to the clamp circuit 78. In the clamp circuit 78, the DC component in the output signal of the VCA 77 is cut, and the positive peak of the AC component (corresponding to the peak-to-peak value) is reduced by the forward drop of the diode D by the diode D in the clamp circuit 78. The voltage value is clamped, and the peak in the negative direction is transmitted as it is to the inverting input terminal of the subsequent comparator 79 without being clamped. Note that the clamp circuit 78 may be a full-wave rectifier circuit.

The comparator 79 compares the reference voltage vo applied to the non-inverting input terminal with the output voltage of the clamp circuit 78. The output signal of the comparator 79 is input to one input terminal of an AND circuit 90, and the hold timing signal 113 is input to the other input terminal of the AND circuit 90 via an inverter 91.

The output signal of the AND circuit 90 is then input to the AGC voltage generation circuit 80 via the resistor 92.

The AGC voltage generated by the AGC voltage generation circuit 80 is applied to the hold circuit 93 and one contact 94 of the analog switch 94.
It is designed to be input to a. Hold circuit 93
has a role as a control means, and is composed of, for example, an A/D converter and a D/A converter located at the subsequent stage, although not specifically shown. When holding, the AGC voltage is sampled and held at a predetermined timing by the A/D converter, and thereafter the held AGC voltage value is converted to analog by the D/A converter, and the other contact 94b of the analog switch 94 is It is designed to be supplied to Note that the hold circuit 93 may be, for example, an analog sample and hold circuit.

A hold timing signal 113 is supplied to the hold circuit 93 and the analog switch 94 from a reproduced signal state determination circuit 105, which will be described in detail later.When this hold timing signal 113 is at a low level,
When the AGC voltage in the C amplifier 75 is not held, the contact 94 of the analog switch 94 is closed as shown in the figure.
A and 94b are opened and the AGC voltage is directly passed to the VCA.
Returned in 1977. On the other hand, the hold timing signal 11
3 becomes high level, the AGC voltage is held in the hold circuit 93, and the contacts 94a and 94b of the analog switch 94 are closed, and the held constant AGC voltage is fed back to the VCA 77 via the contact 94b. At the same time, the potential of capacitor 83 is kept constant.

In the above arrangement, the operation when the hold timing signal 113 is at a low level and the MO signal AGC amplifier 75 does not hold the AGC voltage will be described first.

At this time, the input signal from the inverter 91 to the AND circuit 90 is at a high level, so the output signal of the AND circuit 90 is determined by the manual signal from the converter 79 to the AND circuit 90.

Now, when the output amplitude of the clamp circuit 78 exceeds the reference voltage v0, the output signal of the comparator 79 becomes high level, and therefore the output of the AND circuit 9o also becomes high level, so that the transistor 8l is turned on. Therefore,
The capacitor 83 is charged by the power supply VCC via the charging resistor 82, and the voltage across the capacitor 83 is AGC.
The voltage increases. At this time, the charging time constant is the charging resistance 8
2 and capacitor 83. The AGC voltage generated at the connection point A between the charging resistor 82 and the capacitor 83 is fed back to the VCA 77 as a control voltage for adjusting the amplification degree.
As described above, as the AGC voltage increases, the amplification degree of the VCA 77 decreases.

On the other hand, the output amplitude of the clamp circuit 78 is the reference voltage ■. If the output signal does not exceed the current value, the output signal of the comparator 79 and therefore the output signal of the AND circuit 90 becomes low level, and the transistor 81 is turned off, so that the charge stored in the capacitor 83 is discharged via the discharge resistor 84. Ru. At this time, the discharge time constant is determined by the discharge resistor 84 and the capacitor 83. As the capacitor 83 discharges, the AGC voltage decreases and the amplification degree of the VCA 77 increases.

As is clear from the above explanation, there is a relationship as shown in Figure 31 between the peak-to-peak value (P-P value) of the differential signal of s1 and s2 and the AGC voltage. It can be seen that in the normal amplitude range shown, the AGC voltage increases monotonically with respect to the peak-to-peak value of the differential signal. That is, the maximum and minimum values of the AGC voltage correspond to the maximum and minimum values of the peak-to-peak values of the differential signal.

Also, the amplification degree of VCA77 changes according to the AGC voltage,
As shown in FIG. 32, as the AGC voltage increases, the amplification degree decreases.

Next, the operation when holding the AGC voltage in the MO signal AGC amplifier 75 will be described. The reproduction signal state determination circuit 105 determines that the hold timing signal 113 is set to a low level when, for example, a VFO mark, which will be described later, is detected in the MO section 3002, or in other words, when data is being recorded in the MO section 3002. When the AGC voltage is not held and the VFO mark is not detected,
The hold timing signal 113 is set to high level and A
GC voltage is held.

That is, the AGC voltage is held in the MO signal AGC amplifier 75 because the VF
From when the O mark is detected once until it is detected again,
This section roughly corresponds to an area where no data is recorded. When holding the AGC voltage in the MO signal AGC amplifier 75, when the hold timing signal 113 is set to high level, the contacts 94a and 9 of the analog switch 94
4b is closed, the constant AGC voltage held in the hold circuit 93 is fed back to the VCA 77, and the VCA
77 amplification until the next VFO mark is detected.
It is held at a constant value. Further, when the AGC voltage in the MO signal AGC amplifier 75 is held, the output signal of the inverter 91 is inverted from high level to low level. Accordingly, if the output signal of the AND circuit 90 has been at a low level (that is, the output signal of the comparator 79 has been at a low level), it will remain at a low level from now on, and the output signal of the AND circuit 90 will remain at a high level until then ( That is, if the output signal of the comparator 79 is high level, it is inverted to low level, so if the transistor 81 was previously off, it remains off, and if the transistor 81 was previously on, it is switched off.

Therefore, when holding the AGC voltage in the MO signal AGC amplifier 75, the capacitor 83 is connected to the hold circuit 93.
is applied, and the potential at point A is held at the AGC voltage. Next, a circuit for switching the response speed of the MO signal AGC amplifier 75 into two stages, for example, high speed and low speed, will be described.

As shown in FIG. 4, this circuit is designed as a response speed changing/resetting circuit 101 which also has an AGC voltage reset function. That is, the response speed change/reset circuit 101 is composed of a pair of oven collectors 87 and 88 and a discharge resistor 89.
The output of is connected to the connection point A between the charging resistor 82 and the capacitor 83 in the MO signal AGC amplifier 75.

An AGC speed control signal 97 is input to the open collector 87, and an AGC reset signal 98 is input to the open collector 88. Said AGC
The speed control signal 97 is the AG signal at the time of the above-mentioned test write.
It becomes high level when it is necessary to increase the response speed of the MO signal AGC amplifier 75, such as when detecting the C voltage. At this time, the output of the open collector 87 becomes low level, and a discharge resistor 89 is connected in parallel with the discharge resistor 84 in FIG. As a result, the time required for discharging the capacitor 83 is shortened.

On the other hand, the AGC reset signal 98 becomes high level when the magneto-optical disk device is started up or when an abnormality occurs. At this time, the discharge resistor 84 is short-circuited, so that the discharge is instantaneously completed.

Next, a more specific structure of the reproduced signal state determination circuit 105 will be explained.

The reproduced signal state determination circuit 105 detects the magneto-optical disk 120.
This is to determine whether data based on the MO signal exists in the MO section 3002 of No. 1. Specifically, for example, by detecting a VFO mark that is recorded at the same time when data is recorded in the MO section 3002, and which is also erased at the same time when the recorded data is erased, the MO section 3002
It is determined whether data exists in 002. That is, if a VFO mark is detected in the MO section 3002, it is determined that data is recorded in that MO section 3002, and if a VFO mark is not detected, it is determined that data is not recorded in that MO section 3002. It is determined that there is no such thing.

The above vFO mark is, for example, (010010010
...oo1o: However, the number of consecutive bits is 12 bytes), etc.), and when there is a change in the rotation of the magneto-optical disk l201 by the spindle motor 1202, the data synchronization part is displayed on the VFO mark. 25
This is recorded together with data for the purpose of locking the PLL in 04 (FIG. 21) and ensuring data reproduction.

FIG. 2 shows a specific example of the reproduced signal state determination circuit 105 when detecting an area where data has been recorded based on the VFO mark. That is, the reproduced signal state determination circuit 105 is composed of a shift register in which a plurality of D flip-flops 106 are connected, and synchronization data from the data synchronization unit 2504 in FIG. 2513 is input, and the clock input terminal CK of each D flip-flop 106 receives synchronous data 2.
513 in the data synchronization unit 2504.
A clock generated at L is input, and the synchronization data 25l3 is shifted by l bits each time the clock is input.

Then, a signal corresponding to a plurality of consecutive bits in the synchronization data 2513 outputted from the output terminal O of each D flip-flop 106 is output to the pattern comparison circuit 107 at a voltage of V
When it is compared with the FO mark pattern and matches the VFO mark pattern, it is assumed that the VFO mark has been detected, and the pattern detection signal 102, which is the output signal of the pattern comparison circuit 107, is set to a high level. . In addition, in this embodiment, since it is detected whether or not the VF0 mark is recorded in the MO section 3002,
In the pattern comparison circuit 107, the synchronization data 251
The M◯ binary signal 25l1 included in the signal 3 is compared with the pattern of the VFO mark.

As described above, when data is recorded in the MO section 3002 of each sector 3004, a pattern detection signal is sent at the position where the VFO mark of each sector 3004 is recorded, as shown in FIG. 102 becomes a high level.

Note that a signal obtained by inverting the pattern detection signal 102 becomes the above-mentioned hold timing signal 113.

In addition, in this embodiment, AGC by detecting the VFO mark, etc.
Voltage hold control was applied only to the MO signal AGC amplifier 75, but if similar control is applied to the preformat AGC amplifier 65, for example, a VFO mark may also be formed on the preformant section 3003. After that, the preformat section 3 as shown in the same figure (C) is created.
Based on the pattern detection signal indicating that the VFO mark has been detected at 003, it is possible to control the holding or ON switching of the pre-format AGC amplifier 65.

Furthermore, the MO section 300 in the reproduced signal state determination circuit 105
For example, to determine whether data is recorded in 2.
If the data recorded in the MO section 3002 is modulated according to a certain modulation rule such as the above-mentioned 2, MA modulation, the MO binary signal 2511 in the synchronization data 2513
By determining whether or not the data represented by follows the modulation rule, the MO section 3002 detects the presence or absence of the data, and if the data is present, determines whether it is normal data or a defective pulse. be able to.

Furthermore, when recording a synchronization signal, CRC, additional code for error detection, etc. together with the data of the MO section 3002,
It may be determined whether or not data is recorded in the MO section 3002 based on whether or not these synchronization signals or additional codes for error detection are present, or whether or not there is an error in the reproduced data. ．． Furthermore, the above-described methods for detecting multiple data portions may be combined and implemented. Hereinafter, according to the flowchart in Fig. 1, the MO signal A
The procedure for holding control of the AGC voltage in the GC amplifier 75 will be described once again. First, detecting a specific pattern such as the FO mark, and detecting whether the data string to be reproduced conforms to modulation rules such as 2, 7 modulation, etc. detection or CRC
Alternatively, the MO unit 3002 detects whether or not the reproduced data is in error using an additional code for error detection.
It is detected whether data is recorded in (S1).

Next, based on the above detection result, it is determined whether or not data is recorded in the MO section 3002 (S2). If data is recorded, the AGC voltage at that point is stored in the hold circuit 9.
3 and hold it (S3). Then, based on the held AGC voltage, the MO signal AG
Controls the amplification degree of the VCA 77 in the C amplifier 75 (s
4) Amplification is performed by the VCA 77 at a constant amplification degree corresponding to the held AGC voltage (S5).

On the other hand, if no data is recorded in the MO section 3002 in S2, the AGC voltage held in the area where the previous data has been recorded is held as is without sampling the AGCt pressure in the hold circuit 93 (S6). .

In the above embodiment, if no data is recorded, the AGC voltage is held as it is. You may also perform processing such as

Also, by charging and discharging the capacitor 83, analog AG
I showed an example of performing C. In addition to the above hold circuit 9
Input the output of the A/D converter in 3 to the processor,
After digital processing (filter etc.), the D/A
It is also possible to perform so-called digital ACC in which the converter feeds back to the CA77. In this case, the above AGC
Holding or turning on is done digitally.

[Example 2] Next, a second embodiment will be explained.

The second embodiment combines the above-described determination of the reproduced signal state based on the VFO mark and the like and the determination of the data recorded area by detection of a pulse group. That is, as mentioned above, the reason why the MO signal AGC amplifier 75 is more likely to respond to defective pulses, etc.
This is immediately after the AGC voltage of No. 5 is reset, or immediately after the magneto-optical disk device itself is started.

Therefore, in this embodiment, the MO signal AGC amplifier 75
The amplification degree of the MO signal AGC amplifier 75 is increased by detecting the recorded data area based on the VF○ mark etc. only immediately after resetting or starting the magneto-optical disk device, and reproducing the detected data. After it is set to an appropriate value, the AGC voltage is controlled to be held or turned on (state in which no hold is performed) by detecting a group of pulses.

Note that the determination of the reproduced signal state based on the detection of the VFO mark, etc. can be performed in the same manner as in the first embodiment, so the following will be described below.
A specific example of a pulse group detection circuit will be described.

As shown in FIG. 7, this pulse group detection circuit 31 has a one-shot multi-vibrator 32, and the trigger input terminal T of the one-shot multi-vibrator 32 is connected to the MO
M○ is the output signal of the binarization circuit 76 (FIG. 25) that binarizes the MO signal amplified by the signal AGC amplifier 75.
Binarized signal 2511 (or data synchronization unit 25 in FIG. 2l)
The MO binary signal 2511) in the synchronized data 2513 synchronized at 04 is input. The one-shot multivibrator 32 has a time constant T determined by the resistor 33 and the capacitor 34 when a trigger signal is input, in other words, when a 1-bit signal "'1" is present in the MO binary signal 251l. A negative logic pulse signal having a time width of , is generated and is input to the reset terminal R of the timer circuit 35. Further, this one-shot multi-bye break 32 is configured such that when the next trigger signal is input within time TI, the time T. The output signal is maintained at a low level until the time elapses.

The timer circuit 35 outputs a high-level signal when the signal input to the reset terminal R maintains a low level for a time T2, and immediately outputs a high-level signal when the signal input to the reset terminal R becomes high level. The signal is returned to low level. The output signal of this timer circuit 35 is used as a pulse group detection signal 36.

The operation of the above pulse group detection circuit 31 will be explained as follows.
When an unrecorded area in which no data is recorded in the MO section 3002 is being reproduced, for example, as shown in FIG.
As shown in FIG. 2, the differential signal input to the MO signal AGC amplifier 75 does not include any pulse signals. Therefore, as shown in the same figure (b), the AGC amplifier 75 for MO signal
The signal that is amplified and output is a low level signal.

Therefore, when the output signal of the MO signal AGC amplifier 75 is binarized by the binarization circuit 76, the MO binarization signal 2511 which is the output signal of the binarization circuit 76 ((C) in the same figure)
is constantly at a low level.

At this time, as shown in FIG. 3D, the output signal of the one-shot multi-by-break 32 remains at high level, and the pulse group detection signal 36, which is the output signal of the timer circuit 35, remains at low level.

In addition, when a defective pulse 4l occurs in the differential signal as shown by the dotted line in the data unrecorded area,
The output signal of the one-shot multi-vibrator 32 remains at a low level for a time T1, and when the defect pulse 41 continues, the output signal of the one-shot multi-vibrator 32 remains at a low level.

However, as described above, the pulse group detection signal 36, which is the output signal of the timer circuit 35, becomes high level only when the output signal of the one-shot multi-by-break 32 remains low level for a period of time T2 or more. Since the time T2 is set to be sufficiently longer than the time during which the output signal of the one-siggot multivibrator 32 becomes low level due to the normal defect pulse 4l,
There is a very small risk that the pulse group detection signal 36 will become high level due to the defective pulse 41.

Next, when the playback position approaches the recorded area where data is recorded in the MO section 3002, the AG for MO signal
A differential signal including a pulse group is input to the C amplifier 75, and the MO signal AGC amplifier 75 amplifies and outputs this differential signal. The output signal of this MO signal AGC amplifier 75 is binarized by a binarization circuit 76, and the MOZ digitized signal 2
511 is manually inputted to the one-sigid multivibrator 32.

The output of the one-shit multi-by-break 32 switches to low level when the first pulse sent from the binarization circuit 76 rises. Then, when further pulses are input continuously from the binarization circuit 76 within the time T1, the output of the one-shot multi-by-flake 32 continues until the time T, elapses after the last pulse sent rises. is maintained at a low level.

The timer circuit 35 operates after the output of the one-shot multi-by-break 32 becomes low level, that is,
After time T2 has elapsed since the first pulse in the pulse group included in the reproduced signal rises, the pulse group detection signal 36 is set to high level, and at the same time the output of the one-shot multivibrator 32 returns to high level, the pulse group detection signal is set to high level. 36 is set to low level.

In this embodiment, based on the pulse group detection signal 36 and the pattern detection signal 102 described in the first embodiment,
A hold timing signal 113 for holding or turning on the AGC voltage of the MO signal AGC amplifier 75 is monitored by the circuit shown in FIG.

That is, this hold timing generation circuit 42 includes an RS flip-flop 43 and an AND circuit 44, and
For example, the set terminal S of the flip-flop 43 has V
While the pattern detection signal 102 (see Fig. 2), which is set to high level upon detection of the FO mark, is input, the recess
The above-mentioned AGC reset signal 98 is input to the terminal R. The AGC reset signal 98 is M
This signal becomes high level when the AGC voltage in the O signal AGC amplifier T5 is reset.

The output signal of the RS flip-flop 43 is sent to an AND circuit 44.
The pulse group detection signal 36 is input to one input terminal of the AND circuit 44 via an inverter 45 to the other input terminal of the AND circuit 44 . The output signal of the AND circuit 44 is then used as the hold timing signal 113.

In the hold timing control circuit 42 described above, the MO
When resetting the AGC voltage in the signal AGC amplifier 75, the AGC reset signal 98 goes high, so the output signal of the RS flip-flop 43 goes low. The output signal becomes low level. Therefore, when resetting the AGC voltage or starting up the magneto-optical disk device, the hold timing signal 113 becomes low level regardless of the level of the pulse group detection signal 36, so the AGC voltage is not held in the MO signal AGC amplifier 75. do not have.

As a result, even if the MO signal AGC amplifier 75 responds to the defect pulse 41 at the time of resetting the AGC voltage, which is likely to respond to the defect pulse 41, or at the startup of the magneto-optical disk device, the amplification at that time is extremely low. The degree is never held. Next, after resetting the AGC voltage or starting up the magneto-optical disk device, data based on the MO signal is detected by detecting a VFO mark or the like, and when the pattern detection signal 102 becomes high level, the output signal of the RS flip-flop 43 is becomes high level. RS flip flop 4
When the output signal No. 3 becomes high level, the level of the hold timing signal 113 is thereafter inverted in accordance with the pulse group detection signal 36.

That is, in the recorded area of data where a pulse group is detected (the pulse group detection signal 36 is at a high level), the hold timing signal 113 is at a low level and the AGC voltage is not held; In the unrecorded area of data that will not be recorded (the pulse group detection signal 36 is low level), the hold timing signal 113 becomes high level, and the AGC voltage of the MO signal AGC amplifier 75 returns to the value at the end of the immediately previous recorded area. The amplification level is held at a constant value until the next recorded area. Note that once the MO signal AGC amplifier 75 responds to the regular data recorded in the MO section 3002, the amplification level becomes an appropriate level, so from then on, the <AG
By simply holding the C voltage or switching it on, the MO
The data in section 3002 can be reproduced almost properly.

Hereinafter, the AGC voltage hold control in the second embodiment will be explained once again with reference to the flowchart of FIG.

If the MO signal AGC amplifier 75 is reset (or the magneto-optical disk device is started) (Sl), AGC voltage ho) LtF is not performed (S2), and the playback signal state is determined by detecting the vFO mark, etc. Detection is performed (S3).

Then, it is determined whether the reproduced MO signal corresponds to the recorded data (S4), and if it is not the recorded data, the process returns to S2 and the state where the AGC voltage is not held is maintained. do.

On the other hand, if the data is recorded, then the AGC voltage is controlled to be held or turned on (state B where it is not held) based on the detection of the pulse group (S5). More specifically, it is determined whether the area is a recorded area based on the detection of the pulse group (s6), and if it is a recorded area, the AGC voltage of the MO signal AGC amplifier 75 is turned on and the area is not recorded. Amplification is performed according to the amplitude of the recorded data (37), and if it is not a recorded area, the AGC voltage is held to maintain the amplification degree at the end of the immediately previous recorded area (S8).

Note that in the above embodiment, M in each sector 3004
Although only the O portion 3002 is configured to determine whether or not data is recorded using the VF○ mark or the like or by detecting a pulse group, the same applies to the BR format portion 3003, for example. The determination may be made, and the AGC voltage in the pre-format AGC amplifier 65 may be controlled to be held or turned on based on the determination result.

Further, in the above embodiment (FIG. 6), an example was shown in which the reproduction state is determined only once, but the reliability is not limited to this, and reliability can be further improved by performing the determination multiple times. I can do it.

Further, in the above embodiment, by differentially adding the two reproduced signals s1 and S2, the preformat section 300
3 and MO section 3002, but such precautions are not essential.

Furthermore, in the above embodiment, a case has been described in which the track 1205 of the magneto-optical disk 120l is divided into a plurality of sectors 3004 each consisting of a preformat section 3003 and an MO section 3002, but the present invention is applicable to other sectors. Magneto-optical disk 1201 formatted with
It can also be applied when recording and reproducing data.

Furthermore, the present invention applies not only to magneto-optical disks but also to so-called
The present invention can also be applied to recording/reproduction on a phase-change optical disc as a rewritable optical disc or a write-once optical disc on which desired recording can be performed only once.

〔Effect of the invention〕

As described above, the auto gain control device for an optical memory device according to the present invention is provided in an optical memory device that performs recording, playback, or erasing in an optical memory, and is an auto gain control device that adjusts the degree of amplification according to the amplitude of a reproduced signal. a reproduction signal state determination means for determining whether the reproduction signal represents recorded data based on the reproduction signal state; and a reproduction signal state determination means for determining whether the reproduction signal represents the recorded data. control means that causes the automatic gain control device to adjust the amplification degree when it is determined that the reproduced signal does not represent the recorded data; and a control means that fixes the amplification degree when it is determined that the reproduced signal does not represent the recorded data. It is. Thereby, the reproduction signal state determination means can determine whether the recorded area of information is currently being reproduced or the unrecorded area is being reproduced;
Furthermore, when an information pulse group exists, it can be determined whether it is recorded data or a defective pulse. Therefore, based on the determination result of the reproduced signal condition determination means, the amplification degree is adjusted by the automatic gain control device only in the area where data has been recorded, and in the unrecorded area or when a defective pulse occurs, the amplification degree is adjusted from the previous recording. By fixing the value to the value at the end of the recorded area, it becomes possible to always properly reproduce information in the recorded area.

Note that the reproduced signal state determining means determines the area where data has been recorded, for example, when a certain pattern (such as a VFO mark) is recorded together with data in the optical memory in order to synchronize the reproduction of the optical memory, this pattern is detected. Or, if the data is modulated according to a certain modulation rule, it can be determined whether the data contained in the reproduced signal conforms to the above modulation rule or not. A method may be used to determine whether or not the data is recorded, or to detect the location where the data is recorded by detecting the error detection code if an error detection code is added to the data.

[Brief explanation of drawings]

1 to 5 show a first embodiment of the present invention. FIG. 1 is a flowchart showing the procedure for holding control of the AGC voltage in the MO signal AGC amplifier. FIG. 2 is an explanatory diagram showing the internal structure of the reproduced signal state determination circuit. FIG. 3 is a circuit diagram showing an AGC amplifier for MO signals. FIG. 4 is an explanatory diagram showing the response speed control and reset circuit. FIG. 5 is an explanatory diagram showing the waveform of the pattern detection signal. 6 to 9 show a second embodiment of the present invention. FIG. 6 is a flowchart showing the procedure for holding control of the AGC voltage in the MO signal AGC amplifier. FIG. 7 is an explanatory diagram showing the pulse group detection circuit. FIG. 8 is an explanatory diagram showing waveforms of various parts in the pulse group detection circuit. FIG. 9 is a circuit diagram showing a hold timing control circuit. FIG. 10 to FIG. 33 are drawings showing a structure common to the first and second embodiments. FIG. 10 is an explanatory diagram showing the overall structure of the magneto-optical disk device. FIG. 11 is a block diagram showing the recording circuit. FIG. 12 is a block diagram showing 11 paths of regeneration. FIG. 13 is a block diagram showing the main parts of the controller. Figure 14 is a block diagram showing the semiconductor laser drive circuit. FIG. 15 is an explanatory diagram showing switching timing during recording of a high frequency superimposed switch signal, etc. FIG. 16 is an explanatory diagram showing switching timing during reproduction of a high frequency superimposed switch signal, etc. FIG. 17 is a block diagram showing the timing generation circuit. FIG. 18 is a block diagram showing the structure of a sector mark detection circuit. FIG. 19 is an explanatory diagram showing the sector mark detection procedure. FIG. 20 is an explanatory diagram showing waveforms of various parts in the timing generation circuit. FIG. 21 is a block diagram showing the structure of the signal processing circuit. FIG. 22 is an explanatory diagram showing waveforms of each part in the signal processing circuit. FIG. 23 is an explanatory diagram showing the relationship between marks, non-marks, and reproduced signals. FIG. 24 is a block diagram illustrating the structure of the BR format waveform processing section. FIG. 25 is a block diagram showing the structure of the MO waveform processing section. FIGS. 26(a) and 26(b) are explanatory diagrams showing the relationship between the recording light amount and the mark size. FIGS. 27(a) and 27(b) are explanatory diagrams showing the relationship between recording pulse length and mark size. FIGS. 28(a) and 28(b) are explanatory diagrams showing the relationship between the size of a mark and the amplitude of a reproduced signal. FIG. 29 is an explanatory diagram showing the test write procedure. FIG. 30 is a block diagram showing the main parts of the controller. FIG. 31 is a graph showing the relationship between the peak-to-peak value of the differential signal and the AGC voltage. FIG. 32 is a graph showing the relationship between AGC voltage and amplification degree. FIG. 33 is a block diagram showing the structure of the modulation circuit. 34 to 43 show conventional examples. FIG. 34 is an explanatory diagram showing the recording operation in the magneto-optical disk device. FIG. 35 is an explanatory diagram showing the reproducing operation in the magneto-optical disk device. Figure 36 is a schematic plan view of the magneto-optical disk. 37th
The figure is an enlarged view of the main part of FIG. 36. FIG. 38 is an explanatory diagram showing the reproduction processing system. FIG. 39 is an explanatory diagram showing the relationship between the polarities of two reproduced signals in the MO section. FIG. 40 is an explanatory diagram showing the relationship between the polarities of two reproduced signals in the preformat section. FIG. 41 is a circuit diagram showing the AGC amplifier. FIG. 42 and FIG. 43 are explanatory diagrams showing the relationship between the input signal and output signal of the VCA, respectively. 75 is an AGC amplifier for MO signal (auto gain control device), 93 is a hold circuit (control means), 105
is a reproduction signal state determination circuit (reproduction signal state determination means), 1
201 is a magneto-optical disk (optical memory).

Claims (1)

[Claims] 1. In an automatic gain control device that is installed in an optical memory device that performs recording, playback, or erasing in an optical memory and adjusts the degree of amplification according to the amplitude of a playback signal, the playback signal is adjusted based on the playback signal state. a reproduced signal state determining means for determining whether or not the reproduced signal represents recorded data; and an automatic gain control function when the reproduced signal state determining means determines that the reproduced signal represents recorded data. An automatic gain control for an optical memory device, comprising a control means for causing the device to adjust the amplification degree and fixing the amplification degree when it is determined that the reproduced signal does not represent recorded data. Device.