JPH0294921A - Bit error correcting circuit - Google Patents

Abstract

PURPOSE:To correct a bit error with the minimum parity bits by defining undefined data, which cannot be defined in an identification circuit, as correct data by a parity operation using the parity bits. CONSTITUTION:An identification circuit 2 outputs an 'H' signal when the input data is recognized as 'high' and outputs 'L' data to an output terminal 25 when the above-mentioned data is recognized as either 'medium' or 'low'. Further, when the data is recognized as 'medium', the identification circuit 2 simultaneously outputs an 'H' pulse as the undefined data from a detecting terminal 24. Further, in an error correcting circuit 5, 'H' or 'L' definition for the undefined data is executed from a parity counted result in a parity arithmetic circuit 4, and an error in an undefined bit is corrected when the data is outputted from a data memory 3. Thus, the error can be corrected with the minimum parity bits without adding any special additional bit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a wireless device that transmits digital signals;
In particular, the present invention relates to a circuit that detects and corrects bit errors in data.

[Prior Art] Conventionally, in order to correct bit errors in this type of wireless device, a large number of parity bits are inserted in addition to information bits, and data errors occurring in the transmission path are detected and corrected. Ta.

[Problem to be solved by the invention]

The above-described conventional bit error correction requires a large number of parity pits in order to detect and correct errors in information bits, resulting in an increase in data redundancy.

An object of the present invention is to provide a bit error correction circuit that can correct bit errors with a small number of parity pits.

[Means to solve the problem]

The bit error correction circuit of the present invention distinguishes manually entered digital data into three values: "high", "medium", and "'low", and outputs identification data corresponding to "high" and "low" at the same time. an identification circuit that outputs uncertain data when identifying a medium, a data memory that stores the output data of this identification circuit, a parity calculation circuit that counts the parity of this output data, and the data memory and parity The apparatus includes an error correction circuit that determines the uncertain data as data corresponding to either "high" or "low" using the output data from the arithmetic circuit and the uncertain data from the identification circuit.

[Effect]

With the above configuration, uncertain data that cannot be determined by the identification circuit can be determined as correct data by parity calculation using parity bits, and bit error correction can be realized with a small number of parity bits.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In the figure, ■ is the data input terminal of the receiving section after passing through the transmission path, and 2 is the voltage value of the input data, which is set to high (H).
, medium (M), and low (L); 3 is a data memory that stores one frame of the identified data; 4 is an arithmetic circuit for counting the parity of the identified data. , 5 is an error correction circuit that corrects the data in the memory 3 based on the results of the identification circuit 2 and the arithmetic circuit 4, and 6 is a data output terminal.

As shown in FIG. 2, the identification circuit has different threshold voltages VLhl+
Voltage comparator 21 set to th+ > V2),
22 are connected in parallel, and their outputs are outputted to the uncertain data detection terminal 24 through the OR gate (exclusive OR) 23. Further, the output of the voltage comparator 21 is output to the identification data output terminal 25.

Next, the circuit operation in this embodiment will be explained.

Data input to the data input terminal 1 is voltage-compared by voltage comparators 21 and 22. At this time, with the threshold voltage VLhl+V2 of the comparators 21 and 22, as shown in FIG. 3, if the data input voltage is
"High" when > VLh+ " When v > v thz"
When V tht < V < V Lh+, the identification circuit recognizes it as "medium".

When the input data is recognized as "high", it outputs a "H" signal, and when the input data is recognized as "medium" or "low", it outputs a signal of "L". is output to the output terminal 25. Also, when the data is recognized as “medium”, it is also recognized as “H+” as uncertain data.
A + pulse is output from the detection terminal 24.

Further, the data outputted from the output terminal 25 is stored in the data memory 3 once and sent to the error correction circuit 5 in l frame units. At the same time, uncertain data output from the output terminal 11 is also sent to the error correction circuit 5. Then, the error correction circuit 5 recognizes the position of the uncertain bit in one frame data. FIG. 4 shows an example in which one undefined bit occurs in one frame.

On the other hand, one parity bit is added at the end of one frame, and the parity calculation circuit 4 detects whether there is a data error in one frame by comparing the result of counting the number of HIIs in the data with the parity bit. do.

Then, in the error correction circuit 5, when one piece of uncertain data is detected in the frame (1), from the parity counting result in the parity calculation circuit 4, the uncertain data is "11", L
is determined by the error correction circuit 5. Since the position of the uncertain bit is recognized by the timing of the uncertain bit detection pulse, error correction of the uncertain bit is performed in step 5 when outputting data from the data memory, and the error-corrected data is sent to the output terminal. It is output sequentially from 6 onwards.

FIG. 5 is a diagram showing the error improvement effect in this embodiment. Assuming that Gaussian noise is mixed into the transmission path, a voltage is input to the identification circuit with a probability of P (L) + P fl + 1 for original data "L" or "H". If the voltage discrimination is binary, the threshold is V/
2 is optimal, and the field effect discrimination error probability in this case is the combined area of A (lower right diagonal line) and B (upper right diagonal line) in the figure.

On the other hand, when the voltage identification is ternary as in the present invention, if it is within 1 bit per frame, errors in the BF4 region are corrected, and data identification errors are only possible in the A region. Thereby, highly accurate error correction can be performed with the smallest parity pit.

[Effects of the Invention] As explained above, the present invention identifies input digital data into three values, outputs uncertain data, and determines this uncertain data based on data from a parity calculation circuit. Since error correction is performed, there is an effect that error correction can be performed with the minimum parity bit without adding special additional focus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram of a level identification circuit, FIG. 3 is a diagram showing the relationship between input data and the dark value voltage of a voltage comparator, and FIG. FIG. 4 is a diagram showing the configuration of one frame, and FIG. 5 is a diagram showing the probability of data identification errors. 1...Data input terminal, 2...Level identification circuit, 3
...Data memory, 4.Parity calculation circuit, 5.
...Error correction circuit, 6...Data output terminal, 21.
22... Voltage comparator, 23... EOR gate, 24... Uncertain data detection terminal, 25... Identification data output terminal. Fig. 1 Fig. 3 Fig. 4 Fig. 2 Fig. 5 51 Ki 2+, 22 Hakubaku 6 Combatou 2 0 ■2 capture V Sen 1V X:')shihe)shi

Claims (1)

[Claims] 1. Set the input digital data as “high”, “medium” or “low”
an identification circuit that identifies three values and outputs identification data corresponding to "high" and "low" and at the same time outputs uncertain data when identifying "medium"; and data that stores the output data of this identification circuit. A memory, a parity arithmetic circuit that counts the parity of this output data, and output data from the data memory, parity arithmetic circuit, and uncertain data from the identification circuit to convert the uncertain data into "high" and "low" levels. A bit error correction circuit comprising: an error correction circuit that determines data corresponding to any of the bits.