KR940012367A - Error Detection and Correction Device of Biphase Code - Google Patents

Abstract

The present invention relates to an apparatus for detecting and correcting errors that deviate from the specification of the biphase code recorded on the laser disk. The present invention does not meet the specifications due to dust or scratches during use or storage of the laser disk or during production. It is an object of the present invention to provide an apparatus for detecting an error of a biphaser code that deviates from the IEC standard due to coding of a biphaser code and correcting the generated error.

According to the IEC standard, all biphaser codes consist of a total of 24 bits (6 addresses), and the first word must always be “8” or “F”. Especially in the case of program status code, the second and third words are “BA” or “ DC ”, but if it is out of this error. Therefore, it consists of means for determining whether the total number of bits of the biphaser code matches the prescribed value, and means for determining whether the value of the first word of the code matches the prescribed value. Means for determining whether the values of the and third words match the specified values, and detecting whether an error has occurred in the fifth and sixth words of the hamming coded code, and correcting the error when 1-bit error occurs. In the event of an error exceeding a bit, means for outputting an error generation signal is added.

Description

Error Detection and Correction Device of Biphase Code

As this is a public information case, the full text was not included.

1 is a block diagram showing an apparatus of the present invention;

3 is a configuration diagram of the biphaser code detecting means shown in FIG.

4 is a block diagram of the code bit detection means shown in FIG.

Claims (6)

In an error detecting apparatus of a laser disk using device, a system clock signal and a biphaser code coded on a laser disc are input, and a bit counter pulse corresponding to the number of bits of the code and the code are detected to output a logic signal for each word. A biphaser code detecting means (10), a code bit number discriminating means (12) for judging whether or not the value of counting said bit counter coincides with a prescribed total number of bits of said code, and logic of the first word of said word And a first word discriminating means (14) for determining whether the signal value is a prescribed value. 4. The bit counter counting means (12) according to claim 1, characterized in that the code bit count determining means (12) is a bit counter (60) for counting the number of pulses of the bit counter signal in synchronization with the system clock signal, and the lower first predetermined bit among the output signals of the bit counter. An inverter 62 for inverting?, And a value of a bit formed by the upper second predetermined bit output of the bit counter and the first predetermined bit output of the inverter coincides with the total number of bits of the prescribed biphaser code And a logic element (64) for discriminating whether or not it is. 2. The first word discrimination means (14) according to claim 1, wherein the first word discrimination means (14) comprises an F discrimination portion (70) for determining whether the first word is "F ₍₁₆₎ " and an eight discrimination portion for determining whether "8 ₍₁₆₎ ". 72 and an error signal generator 74 for outputting an error signal when the value of the two words is input as the input of the output of the two discriminators, and is not "F ₍₁₆₎ " or "8 ₍₁₆₎ ". A biphasic code error detection device, characterized in that. In the error detection apparatus of a laser disc using apparatus, when the biphaser code is a program status code, a bit counter pulse number corresponding to the number of bits of the code and the code are received by receiving a system clock signal and a biphaser code coded on the laser disc. Detection means for outputting a logic signal for each word and outputting a logic signal for each word, and code bit number discrimination means (12) for discriminating whether or not the value of counting the bit counter pulse coincides with the total number of bits of the code. And first word discriminating means 14 for determining whether the logical signal value of the first word of the word is a prescribed value, and a second for discriminating whether the code values of the second and third words of the word coincide with the prescribed value. When the error signal is output due to the discrepancy between the second / third word discrimination means 18 and the second / third word discrimination means as a result of discrimination, it is always an error. Outputs a call, otherwise determines the code values of the fifth and sixth words of the word, and if there is no error, sets the code values of the two words and, if there is a 1-bit error, the error correction And a hamming decoding means (20) for outputting a code value of the two words and an error signal in the case of an error exceeding 1 bit. The second / third ad discriminating means (18) according to claim 4, further comprising: a BA discriminating unit (76) for determining whether the values of the second and third words are "B ₍₁₆₎ ""A ₍₁₆₎ "; The DC discrimination unit 78 for determining whether it is “D ₍₁₆₎ ” or “C ₍₁₆₎ ”, and the outputs of the BA discrimination unit and the DC discrimination unit are input, and the value of the second and third words is “B ₍₁₆₎ ” _. A non-pager code error detection and correction device, characterized in that it comprises an error signal generator (80) for generating an error signal if it is not "A ₍₁₆₎ " or "D ₍₁₆₎ " or "C ₍₁₆₎ ". 5. The method of claim 4, wherein the hamming decoding means 20 receives the code value of the fifth word and the sixth word to generate a syndrome and the syndrome generating unit 100, and detects whether the syndrome value is the mode "0" The syndrome error detection unit 102, the even parity discrimination unit 104 for determining whether the sum of all code values of the fifth and sixth words are even, the syndrome error detection unit 102 and the even parity discrimination unit ( A 1-bit error discrimination unit 106 that determines whether an error of the fifth and sixth word values has occurred only one bit using the output of 104, and the second / third word discrimination means output an error signal. An error signal generating unit 108 which outputs an error generation signal only when one or more of the fifth and sixth word errors occur, and an error when only one bit of the fifth and sixth words occurs. Error detecting bit The error detection unit 110 and the error code of the fifth and sixth words corresponding to the error occurrence bits detected by the error bit detection unit 110 are corrected and output, and the remaining code values are output as they are. Bi-pager code error detection and correction device, characterized in that consisting of a government (112). ※ Note: The disclosure is based on the initial application.