JP3151844B2 - Playback data detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproduction data detection system, and more particularly to a bit error correction system utilizing a state transition which is suitable for a digital VTR, an optical disk device and the like.

[0002]

2. Description of the Related Art Generally, in a digital VTR, a digital optical disk recording device, or the like, when discriminating and judging reproduced digital data, a threshold voltage is determined for each bit, and if a reproduction voltage level exceeds the threshold voltage. A method of determining "H" and "L" unless the reproduction voltage level exceeds the threshold voltage is used.

In some digital optical disk devices, a detection method called partial response (1, 1) + Viterbi decoding is used.

FIG. 10 shows a partial response (1, 1).
FIG. 11 is a block diagram of the + Viterbi decoding method, and FIG. 11 is a timing chart in FIG. On the recording side, the signal is subjected to NRZ / NRZI conversion by the precoder D, and on the reproduction side, a partial response (1, 1) is detected. The partial response (1, 1) detection is a method for detecting the reproduced data by using the correlation between the reproduced codes, and the reproduced equalized output signal is set to "..001100" for the recording signal "1". In this method, the level is detected using three values. After the detection of the partial response (1, 1), Viterbi decoding is performed. 12 and 13 show a state transition diagram and a trellis diagram in two-state Viterbi decoding. In the Viterbi decoding method, the reproduction state is set to two states S0 and S1, and -1 is input in the state S0.
Then, the state transits to the state S0, the output data is set to 0, and the state
When 0 is input in S0, transition to state S1 and output data
Is set to 1 and transitions to state S0 when 0 is input in state S1.
When the output data is set to 1 and 1 is input in the state S1
The state data is shifted to the state S1, and the output data is set to 0. When there is an input that violates the rule of the state transition, the violation state is detected and the original state is determined to perform the bit error correction, and the random error is corrected. This is a method for improving the error rate for

[0005] Assuming noise and Gaussian distribution, as shown in FIG. 14, the distribution of the signal plus noise, to become a normal distribution of the signal level and the mean value, the state S _i
When the data that is to be _{j in the above} is reproduced, the probability P _ij of receiving data having a level between the level “y _k ” and the level “y _k + Δy” is P ₁₁ , P ₀₁ : the level 0 is defined as the average value. Normal distribution P ₁₀ : Normal distribution with level 1 as the average value P ₀₀ : Normal distribution with level -1 as the average value, calculate the area enclosed by the level “y _k ” and the level “y _k + Δy”. This can be shown by FIG. 14 showing the normal distribution of probabilities and the following equation.

[0006]

Here, the length of the metric can be represented by the negative logarithm of the probability. Therefore, the product of the probabilities can be represented by the sum of the negative logarithms of the probabilities, that is, the sum of the metric lengths.

[0008]

In the future, in order to discuss the relative value of the length, not the absolute value of the metric, a constant value is added to the sum of the logarithmic values, multiplied by a constant value, and then compared.

[0010]

Here, at time n, sample values are represented by y _n ,
Let the path metrics of state S1 and state S0 be m
_n (S1) and _mn (S0),

[0012]

[0013]

[0014]

When the reproduced data is y and -1≤y≤1, y + 0.5 and -y + 0.5 are calculated from the input data, and the merged data is set to 0, and the path metric m (S1) -m
Path metric m when (S0) is greater than y + 0.5
(S1) and the path metric m (S0), the path cytometry <br/> click m the (S0) path metric m (S0) + y + 0 .
5 is assumed. Path metric m (S1) as merge 1
Pa when -m where (S0) is between y + 0.5 and y-0.5
Scan metric m to (S1) and the path metric m (S0), the path metric m (S0) path metric m (S
1). As the merge 2, the path metric m (S
1) -m (S0) is y-0.5 less than the time path cytometry <br/> click m (S1) of path metric m (S1) -y + 0.
5 and the path metric m (S0) is set to the path metric m
(S1).

Then, the paths are merged, and the most probable path is determined from the merged point toward the past. In communication engineering, such a path determination method is called a Viterbi decoding method. Here, since merge 1 does not merge at the immediately preceding time, even if the path shape at time n is determined,
At that point alone, no output value is obtained without merging. However, when merge 0 or merge 2 occurs, the paths are merged and a corresponding output sequence is obtained. FIG.
It is a figure showing an example of the path merge in state Viterbi decoding. When the paths are merged, output data is obtained by setting the output to 0 for the states S0 → S0 and S1 → S1, and setting the output to 1 for the states S0 → S1, S1 → S0.

[0017]

The above-described conventional bit-by-bit determination, which is generally used, utilizes the characteristics of digital recording, and has the advantage that the logic is simple and the circuit is simple. I have. However, when errors occur in the reproduction voltage slightly exceeding the threshold, all of these directly lead to bit errors. In addition, although an error that has occurred once is corrected by the error correction circuit block, there is a disadvantage that it cannot be corrected by the identification and reproduction circuit block.

In the partial response (1,1) detection + two-state Viterbi decoding method using the inter-code correlation of the reproduced signal, bit error correction is performed using the correlation due to the ternary value of the reproduced signal. In a code conversion system in which continuous non-sign inversion bits on the recording side are suppressed to a minimum of 2 and converted into channel bits for recording, continuous non-sign inversion bits on the recording side are minimum in a range of 2. The error rate is improved by bit error correction compared to the judgment for each bit, but it cannot be said that the original recorded code is fully used, There is room for further improving the bit error rate.

[0019]

According to the present invention, there is provided a reproduction data detection system for converting a data bit into a channel bit by recording a non-inverted bit that is continuous on the recording side at a minimum of 2 bits. On the other hand, the reproduction side converts the reproduction signal into a binary value by detecting a partial response (1, 1) using intersymbol correlation and determines the level, and then sets the reproduction state to four states S0, S1, S2, and S3. The state S0
When -1 is input, the state shifts to the state S0 and the output data is set to 0. When 1 is input in the state S0, the state S1 is input.
And the output data is set to 1. When 1 is input in the state S1, the state changes to the state S2 and the output data is set to 1.
When -1 is input in the state S2, the state shifts to the state S3 and the output data is set to 0. When 1 is input in the state S2, the state shifts to the state S2 and the output data is set to 1. When 1 is input, the state transitions to the state S0, the output data is set to 0, the most probable state transition is estimated according to the rules of this state transition, and the trellis diagram is determined. Is performed.

The input data is y and -1≤y
When ≤1, the reproduction state is set to four of S0, S1, S2, and S3.
The reciprocal of the probability of taking one of the states is called a metric, and a metric m (S
2) is smaller than metric m (S1) and metric m
When (S0) is smaller than metric m (S3), the metric m (S3) is metric m (S2) + y, the metric m (S2) is metric m (S2) -y, and the metric m (S1) is metric m. (S0) -y, the metric m (S0) is set to the metric m (S0) + y, and as the merge 1, the metric m (S2) is smaller than the metric m (S1).
0) is greater than or equal to the metric m (S3), the metric m (S3) is added to the metric m (S2) +
y, the metric m (S2) is replaced by the metric m (S
2) -y, the metric m (S1) is the metric m (S0) -y, the metric m (S0) is the metric m (S3) + y, and as the merge 2, the metric m (S2) is the metric m (S2). S1) is greater than or equal to the metric m (S0) and the metric m (S0)
3) When smaller than the above, the metric m (S3) is the metric m (S2) + y, the metric m (S2) is the metric m (S1) -y, and the metric m (S1) is the metric m (S0) -y , The metric m (S
0) is the metric m (S0) + y, and as a merge 3, the metric m (S2) is the metric m (S0) + y.
1) When the metric m (S0) is greater than or equal to and the metric m (S3) is greater than or equal to the metric m (S3), the metric m (S3) is set to the metric m (S2) + y, and the metric m (S2) is set to the metric m ( S1) -y, the metric m (S1) is replaced with the metric m (S0) -y,
The metric m (S0) is replaced by the metric m (S3)
+ Y, and when the transition pattern of these states changes from (the merge 0 to the merge 1) → the merge 1 → (the merge 0 to the merge 1), the path merges with the state S2, and the (the merge 0 Or the merge 2) →
When the transition from the merge 2 to the merge 0 to the merge 2 is made, the path is merged into the state S0, the state up to that point is determined, and the output to the states S0 and S3 is set to "0". Output "1" for states S1 and S2
Is realized by calculating the output data.

[0021]

The present invention is directed to a code conversion system in which data bits are converted to channel bits with the number of consecutive non-inverted bits being kept at a minimum of 2 on the recording side and recorded. The reproduction signal is converted into binary using the correlation between the codes that the sign inversion bit is at least 2 and the level is determined. Then, the reproduction state is set to four states S0, S1, S2, and S3. The input level is limited to a certain range, and when there is an input that violates the rules of this state transition, the state of the violation is detected, the bit error is corrected by judging the original state, and the error rate for random errors Can be improved. Also, state S
It is possible to realize a circuit that determines merge based on the magnitudes of values of S2 and S1 and S0 and S3, determines path merge of S2 to S0, and obtains output data depending on the subsequent state.
This has the effect of performing bit error correction and improving the bit error rate for random errors.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are a state transition diagram and a trellis diagram of a recording code having a minimum of two consecutive non-inverted bits, respectively, showing one embodiment of the present invention. As shown in the drawing, in the present embodiment, the reproduction state is set to four states S0, S1, S2, and S3. When -1 is input in state S0, the state transits to state S0, the output data is set to 0, and the output data is set to 0. State S1 when 1 is input
And the output data is set to 1. When 1 is input in the state S1, the state changes to the state S2 and the output data is set to 1 and the state S2
When -1 is input, the state transits to the state S3 and the output data becomes 0.
When 1 is input in the state S2, the state shifts to the state S2, the output data is set to 1, and when -1 is input in the state S3, the state S
The output data is changed to 0 and the output data is set to 0. When there is an input that violates the rule of this state transition, the state of the violation is detected, the original state is determined, and the bit error correction is performed. Improve error rate.

Calculation is performed using the derivation method of the equations described with reference to FIGS. Assuming noise and Gaussian distribution, as shown in FIG. 14, the distribution of the signal plus noise, to become a normal distribution of the signal level and the average value, when to transition from the state S _i to state S _j, the level " y _k ″ to level ″ y
_The probability P of receiving data having a level between _k + Δy ″
_{ij is, P 00, P 23, P} 30: normal distribution P _01, P _12, P ₂₂ to average the level-1: In a normal distribution of the average value level 1, level "y _k" level " It is sufficient to calculate the area enclosed by y _k + Δy ″, which can be shown by FIG. 14 showing the normal distribution of the probability and the following equation. By grouping the above equations in the same way as [0008] to [0010], the following branch metric is obtained.

[0025] The branch metric 1 _00, 1 _01, 1 _12, 1
_22, 1 _23, 1 _{30, 1 00 = y n 1 01} = -y n 1 12 = -y n 1 22 = -y n 1 23 = y n 1 30 = y n

## EQU1 ##

Here, at time n, the sample value is y _n , and the normalized metrics of the states S3, S2, S1, S0 are m _n
(S3), _mn (S2), _mn (S1), _mn (S0)
Then

[0028]

[0029]

[0030]

[0031]

[0032]

When the reproduction data is y and -1≤y≤1, merge is determined from the input data. As the merge 0, when the metric m (S2) is smaller than the metric m (S1) and the metric m (S0) is smaller than the metric m (S3), the metric m (S3) is changed to the metric m (S3).
2) + y, metric m (S2) is converted to metric m (S
2) -y, metric m (S1) is converted to metric m (S
0) -y, metric m (S0) is replaced by metric m (S
0) + y, and the metric m (S2) is smaller than the metric m (S1) as the merge 1 and the metric m (S0)
Is greater than or equal to metric m (S3), metric m (S3) is calculated as metric m (S2) + y, metric m
(S2) is calculated as metric m (S2) -y, metric m
(S1) is calculated as metric m (S0) -y, metric m
Let (S0) be metric m (S3) + y, and as merge 2, metric m (S2) is greater than or equal to metric m (S1) and metric m (S0) is metric m
When smaller than (S3), metric m (S3) is metric m (S2) + y, metric m (S2) is metric m (S1) -y, and metric m (S1) is metric m
(S0) -y, metric m (S0) is metric m
(S0) + y, and a metric m (S
When 2) is greater than or equal to metric m (S1) and metric m (S0) is greater than or equal to metric m (S3), metric m (S3) is replaced by metric m (S2) +
y, metric m (S2) is converted to metric m (S1) −
y, metric m (S1) is converted to metric m (S0) −
y, metric m (S0) is converted to metric m (S3) + y
And

Thereafter, when one of the following (1) and (2) occurs, the paths are merged, and a corresponding output sequence is obtained. FIG. 3 is a diagram showing an example of path merging in a recording code in which consecutive non-sign inversion bits are at least two.

(1) When three consecutive states are (Merge 0 or Merge 1) → Merge 1 → (Merge 0 or Merge 1), the path merges with the state S2.

(2) When three consecutive states are (merge 0 to merge 2) → merge 2 → (merge 0 to merge 2), the path is merged into state S0.

A state is obtained by merging the paths. That is, the output is set to 0 for the states S0 and S2, and the state S
By setting the output to 1 for S1 and S3, output data is obtained and bit error correction for random errors can be performed.

Next, a specific implementation method of the embodiment described with reference to FIGS. 1 and 2 will be described with reference to FIGS. FIGS. 4, 5, 6, and 7 are block diagrams showing an example of a condition operation circuit, an M operation circuit, a path margin operation circuit, and a path memory circuit in the present embodiment. FIG.
9 (a), 9 (b) and 9 (c) are circuit diagrams showing an example of
FIG. 8 is a diagram showing a circuit of FB2 and FB3 in FIG. 7 and a transition from metric 1 to metric 2 and data output in each merge.

The condition operation circuit shown in FIG. 4 A / D-converts data by 4 bits and inputs the data from ADI3 to ADI0.
CK is a bit clock. In this circuit, y,
Calculate -y. In M arithmetic circuit shown in FIG. 5, m _n (S
1) to _mn (S3) are calculated, and merging is determined. Here, since the value of m _n is the relative value is important, m _n (S0)
= 0, and _mn (S1) to _mn (S3) are each _mn
The relative value to (S0) is calculated. In the path merge operation circuit shown in FIG. 6, when (Merge 0, 2) → Merge 2 → (Merge 0, 2) appears, PMERGE 1, 0 = 10
And this becomes S0 merge, and when (merge 0, 1) → merge 1 → (merge 0, 1) appears, PMERGE
1,0 = 11, which is an S2 merge. Path memory circuit shown in FIG. 7, FB shown in FIG. 8, FB shown in FIG.
2, FB3, MERGE1,0 and PMERGE1,
Enter 0 to detect how the state changes. That is, when PMERGE = 10, the path is merged into state S0, and when PMERGE is 11, the path is merged into state S2. Also,
At 00, a merge is detected and past states are determined in order from the present as described in the embodiment of FIG. The operation is performed in this manner, and MGE1,0 output merge, and MET
1,0 outputs a state, and PMG1,0 outputs a path merge. Since the output data is "1" for the states S1 and S2, the exclusive OR of METRK1 and METRK0 is obtained.

[0040]

As described above, the present invention is directed to a code conversion system for converting data bits into channel bits and recording the data bits with the number of consecutive non-inverted bits on the recording side kept at a minimum of 2. The reproduction signal is converted into binary using the correlation between the codes that the consecutive non-sign inversion bits are at least 2 on the reproduction side, and the level is determined.
There are four states of 0, S1, S2, and S3, the input level in each state is limited to a certain range, and when there is an input that violates this state transition rule, the state of the violation is detected, and the original state is determined. Since the bit error correction is performed by the determination, there is an effect of improving the error rate for random errors. State S2 and S1, state S0
And the value of S3 to determine the merge, determine the path merge from state S2 to state S0, and implement a circuit that obtains output data, thereby performing bit error correction and improving the error rate for random errors. It has the effect that it can be done.

[Brief description of the drawings]

FIG. 1 is a state transition diagram of a recording code in which consecutive non-inverted bits are at least two, showing one embodiment of the present invention.

FIG. 2 is a trellis diagram of a recording code having a minimum of two consecutive non-sign inversion bits according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a path merge of a recording code having a minimum of two consecutive non-sign inversion bits according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating an example of a conditional operation circuit according to the embodiment.

FIG. 5 is a block diagram illustrating an example of an M operation circuit according to the present embodiment.

FIG. 6 is a block diagram illustrating an example of a path merge operation circuit according to the present embodiment.

FIG. 7 is a block diagram illustrating an example of a path memory circuit according to the present embodiment.

FIG. 8 is a circuit showing an example of FB1 in FIG. 7;

9 (a), (b) and (c) show F in FIG.
It is a figure which shows the transition of metric 1-> metric 2 in the circuit of B2, FB3, and each merge, and data output.

FIG. 10 is a block diagram of a partial response (1, 1) + Viterbi decoding method.

FIG. 11 is a timing chart in FIG.

FIG. 12 is a state transition diagram in two-state Viterbi decoding.

FIG. 13 is a trellis diagram in two-state Viterbi decoding.

FIG. 14 is a diagram showing a probability of reproducing data.

FIG. 15 is a diagram illustrating an example of a path merge in two-state Viterbi decoding.

[Explanation of symbols]

 S0-S3 state

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/18 H03M 13/00-13/53

Claims (2)

(57) [Claims] 1. A code conversion method in which a data bit is converted to a channel bit with the number of consecutive non-inverted bits kept at a minimum of 2 on a recording side and recorded on the recording side. After detecting the partial response (1, 1), the reproduced signal is converted into a binary value and the level is determined.
The reproduction state is set to four states S0, S1, S2, and S3. When -1 is input in the state S0, the state transits to the state S0, the output data is set to 0, and when 1 is input in the state S0, the state S1 is set. The output data is set to 1 and the state S1
When inputting 1 in step S2, the state shifts to the state S2 and the output data is set to 1. When -1 is input in the state S2, the state S3 is input.
And the output data is set to 0, and when 1 is input in the state S2, the state changes to the state S2 and the output data is set to 1.
When -1 is input in the state S3, the state transitions to the state S0, the output data is set to 0, and the most probable state transition is estimated according to the rules of the state transition to determine a trellis diagram, thereby detecting a reproduced signal. A reproduction data detection method wherein bit error correction is performed at the time of (1). 2. When the input data is y and −1 ≦ y ≦ 1, the reproduction state is set to four states S0, S1, S2, and S3, and the reciprocal of the probability of taking one state is defined as a metric. When the metric m (S2) is smaller than the metric m (S1) and the metric m (S0) is smaller than the metric m (S3) as the merge 0, the metric m
(S3) is metric m (S2) + y, metric m (S2) is metric m (S2) -y, metric m (S1) is metric m (S0) -y, and metric m (S0) is metric m (S0) + y, and when the metric m (S2) is smaller than the metric m (S1) and the metric m (S0) is larger than or equal to the metric m (S3) as the merge 1, the metric m (S3) is The metric m (S2) + y, the metric m (S2) is replaced by the metric m (S2) -y,
The metric m (S1) is replaced by the metric m (S0)
−y, the metric m (S0) is replaced by the metric m (S
3) + y, and the metric m (S
2) is larger than or equal to the metric m (S1) and the metric m (S0) is smaller than the metric m (S3), the metric m (S3) is set to the metric m (S2) + y, and the metric m (S2) ) Is the metric m (S1) -y, the metric m (S1) is the metric m (S0) -y, the metric m (S0) is the metric m (S0) + y, and the metric m (S2 ) Is greater than or equal to the metric m (S1) and the metric m (S0) is greater than or equal to the metric m (S3).
(S3) is metric m (S2) + y, metric m (S2) is metric m (S1) -y, metric m (S1) is metric m (S0) -y, and metric m (S0) is metric m (S0) -y. The metric is m (S3) + y, and when the transition pattern of these states changes from (the merge 0 to the merge 1) → the merge 1 → (the merge 0 to the merge 1), the path merges with the state S2. , (Merge 0 to Merge 2) → Merge 2 → (Merge 0 to Merge 2), the path merges with the state S0, and the state up to that point is determined. A reproduction data detection method wherein output data is calculated by setting an output to "0" for S3 and an output to "1" for the states S1 and S2.