JPH0279027A - Polycrystalline silicon thin film transistor - Google Patents
Polycrystalline silicon thin film transistorInfo
- Publication number
- JPH0279027A JPH0279027A JP63229989A JP22998988A JPH0279027A JP H0279027 A JPH0279027 A JP H0279027A JP 63229989 A JP63229989 A JP 63229989A JP 22998988 A JP22998988 A JP 22998988A JP H0279027 A JPH0279027 A JP H0279027A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- insulating film
- thin film
- silicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 40
- 239000010409 thin film Substances 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims description 76
- 239000003990 capacitor Substances 0.000 claims description 21
- 230000014759 maintenance of location Effects 0.000 claims description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 14
- 239000001257 hydrogen Substances 0.000 claims description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 4
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 238000000034 method Methods 0.000 description 9
- 238000005984 hydrogenation reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000004031 devitrification Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は液晶表示パネル用の多結晶シリコン薄膜トラン
ジスタ（以下ＴＰＴと略記する）に係り。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to polycrystalline silicon thin film transistors (hereinafter abbreviated as TPT) for liquid crystal display panels.
特に電荷保持用キャパシタ部の透明電極を失透させるこ
となく多結晶シリコン膜を選択的に水素化する構造及び
その製造方法に関する。In particular, the present invention relates to a structure for selectively hydrogenating a polycrystalline silicon film without devitrification of a transparent electrode in a charge retention capacitor portion, and a method for manufacturing the same.
近年、アクティブマトリクス方式液晶デイスプレィがフ
ラットパネルデイスプレィの大面積化に適した方法とし
て注目されている。なかでも、薄膜半導体に多結晶シリ
コンを用いる多結晶シリコンＴＰＴは、キャリヤ移動度
が高く高速動作が可能なため周辺回路を内蔵できること
、また安定性に優れている等多くの利点があり、安価な
ガラス基板上に特性の良好な多結晶シリコンＴＰＴを形
成する技術研究が活発に行なりれ°〔いる・第２図及び
第３図を用いて従来構造を説明する。In recent years, active matrix liquid crystal displays have attracted attention as a method suitable for increasing the area of flat panel displays. Among these, polycrystalline silicon TPT, which uses polycrystalline silicon as a thin film semiconductor, has many advantages such as high carrier mobility, high-speed operation, the ability to incorporate peripheral circuits, and excellent stability. Technical research for forming polycrystalline silicon TPT with good characteristics on a glass substrate is actively being carried out.The conventional structure will be explained using FIGS. 2 and 3.
この従来構造については、特開昭５８−１３０５６１中
第３図及び第４図と同じものである。第２図は、一画素
に相当する多結晶シリコンＴＰＴの等価回路を示す、第
２図中２０１及び２０１′はｉ行、ｉ十１行目のゲート
配線、２ｏ２はデータ線を、２０３はｉ行ｊ列目のスイ
ッチング用ＴＰＴを、２０４は電荷保持用キャパシタを
、２０５は液晶表示体に相当するキャパシタを示す。電
荷保持用キャパシタは、多結晶シリコンＴＰＴのオフ電
流の経時変化及び液晶抵抗の低下等により派生する画像
表示のむらを補償し、画質の良好なデイスプレィを得る
ためのものである。第３図は第２図に示した等価回路よ
り成る多結晶シリコンＴＰＴの断面構造図である。This conventional structure is the same as that shown in FIGS. 3 and 4 of Japanese Patent Application Laid-Open No. 58-130561. FIG. 2 shows an equivalent circuit of a polycrystalline silicon TPT corresponding to one pixel. In FIG. The switching TPT in the j-th row and column, 204 a charge holding capacitor, and 205 a capacitor corresponding to a liquid crystal display. The charge retention capacitor is used to compensate for unevenness in image display caused by changes over time in the off-state current of the polycrystalline silicon TPT, a decrease in liquid crystal resistance, etc., and to obtain a display with good image quality. FIG. 3 is a cross-sectional structural diagram of a polycrystalline silicon TPT consisting of the equivalent circuit shown in FIG. 2.
第３図中３１２は、スイッチング用ＴＦＴ部、３１３
ｆｔ、電荷保持用キャパシタ部を示す。３０１は透明基
板、３０２，３０４は下地Ｓ ｉ Ｏｘ膜３０３は下部
ＴＴＯ（酸化インジウムスズ）膜、３０５は多結晶シリ
コン膜（チャネル部） 、３０６はゲート酸化膜、３０
７はゲート電極、３０８は不純物をドープした多結晶シ
リコン膜から成るソース・ドレイン領域、３０９は層間
絶縁膜（Ｓ ｉ Ｏｚ膜）、３１０はＡＱ電極、３１１
はＩＴＯ膜から成る画素電極を示す。In FIG. 3, 312 is a switching TFT section, 313
ft indicates a charge holding capacitor section. 301 is a transparent substrate, 302 and 304 are base SiOx films, 303 is a lower TTO (indium tin oxide) film, 305 is a polycrystalline silicon film (channel part), 306 is a gate oxide film, 30
7 is a gate electrode, 308 is a source/drain region made of a polycrystalline silicon film doped with impurities, 309 is an interlayer insulating film (SiOz film), 310 is an AQ electrode, 311
indicates a pixel electrode made of an ITO film.
多結晶シリコンＴ Ｐ Ｔの特性を向上させるためには
半道体膜である多結晶シリコン膜中の欠陥準位密度を低
減することが重要となる。欠陥準位密度を低減する有力
な手段として、多結晶シリコン膜中に水素原子を導入し
てＳ ｉ Ｈ結合を作ることにより、膜中のダングリン
グボンドを封止する方法（水素化処理）がとられている
。水素化を行うことにより、多結晶シリコンＴＰＴのし
きい電圧、電界効果移動度、ＯＦＦ電流特性を大幅に改
善することができる。水素原子を導入する方法として、
通常多結晶シリコン膜を水素プラズマ中にさらして水素
化する方法がとられている。In order to improve the characteristics of polycrystalline silicon TPT, it is important to reduce the density of defect levels in the polycrystalline silicon film, which is a semicircular film. As an effective means of reducing defect level density, there is a method (hydrogenation treatment) of sealing dangling bonds in a polycrystalline silicon film by introducing hydrogen atoms into the film to create S i H bonds. It is taken. By performing hydrogenation, the threshold voltage, field effect mobility, and OFF current characteristics of polycrystalline silicon TPT can be significantly improved. As a method of introducing hydrogen atoms,
Usually, a method is used in which a polycrystalline silicon film is hydrogenated by exposing it to hydrogen plasma.
しかしながら、電荷保持用キャパシタを付加した多結晶
シリコンＴＰＴにおいては、電荷保持用キャパシタ部の
下部透明電極が通常酸化インジウム、酸化スズ、ＩＴＯ
膜等の金属酸化物から成り、これらの金属酸化物は水素
化処理時の水素プラズマ雰囲気により還元させ、変質し
てしまい透明導電膜としての特性が得られなくな°って
しまい５問題であった。However, in polycrystalline silicon TPT with a charge retention capacitor added, the lower transparent electrode of the charge retention capacitor is usually made of indium oxide, tin oxide, or ITO.
These metal oxides are reduced in the hydrogen plasma atmosphere during hydrogenation treatment, resulting in deterioration and the properties of a transparent conductive film can no longer be obtained. Ta.
上述の様に、電荷保持用キャパシタを付加した多結晶シ
リコンＴＰＴの水素化を行う際には、ＩＴＯ膜等から成
る下部透明電極が還元され、変質してしまうという問題
があった１本発明の目的は、電荷保持用キャパシタ部の
下部透明電極を変質させることなく多結晶シリコン膜を
選択的に水素化する、多結晶シリコンＴＰＴの製造方法
を提供することにある。As mentioned above, when hydrogenating polycrystalline silicon TPT with a charge retention capacitor added, there is a problem in that the lower transparent electrode made of an ITO film or the like is reduced and deteriorated. An object of the present invention is to provide a method for manufacturing a polycrystalline silicon TPT in which a polycrystalline silicon film is selectively hydrogenated without altering the lower transparent electrode of a charge retention capacitor portion.
上記問題点を解決する一手段として特開昭５９−９９６
２及び特開昭６２−８４５６３が挙げられる。いずれも
ＩＴＯ膜上に金属膜又は透明絶縁膜から成る保護膜を形
成して、プラズマＣＶＤ法でアモルファスシリコン膜及
びゲート絶縁膜を形成する際の水素プラズマ雰囲気から
該ＩＴＯ膜を保護する手段である。しかしながら、これ
らの手段ではＩＴＯ膜の保護膜を形成する工程が必要と
なる。一方、プラズマＣＶＤ法で被着形成した窒化シリ
コン膜は膜中に多くの活性水素が残留しており、熱処理
により水素が拡散して水素化が行なわれることが知られ
ティる。 （ＩＥＥＥ ＥＬＥＣＴＲＯＮ ＤＥＶＩ
ＣＥ ＬＥＴＴＥＲ３゜ＥＤＬ−５，（１１）Ｐ、４６
８〜（１９８４））。As a means to solve the above problems, JP-A-59-996
2 and JP-A No. 62-84563. In either case, a protective film made of a metal film or a transparent insulating film is formed on the ITO film to protect the ITO film from a hydrogen plasma atmosphere when forming an amorphous silicon film and a gate insulating film by plasma CVD. . However, these methods require a step of forming a protective film for the ITO film. On the other hand, it is known that a silicon nitride film deposited by plasma CVD has a large amount of active hydrogen remaining in the film, and hydrogen is diffused and hydrogenated by heat treatment. (IEEE ELECTRON DEVI
CE LETTER3゜EDL-5, (11)P, 46
8-(1984)).
よって、上記問題点は上述の知見より、電荷保持用キャ
パシタを付加した多結晶シリコンＴＰＴにおいて、窒化
シリコン膜等膜中に活性水素を含む檜縁膜を積極的に水
素化に利用し、ＴＰＴ構造及び製造方法を工夫すること
により達成される。Therefore, based on the above-mentioned knowledge, the above problem can be solved by actively utilizing a cylindrical film containing active hydrogen in a film such as a silicon nitride film for hydrogenation in a polycrystalline silicon TPT with a charge retention capacitor added, and improving the TPT structure. This can be achieved by devising the manufacturing method.
具体的には多結晶シリコンＴＰＴのゲート電極形成後、
ｌＩ中に活性水素を含む絶縁膜を形成し、電荷保持用キ
ャパシタ部の該絶縁膜を除去した後下部透明電極を形成
し、次いで熱処理する構造とすることにより達成される
。Specifically, after forming the gate electrode of polycrystalline silicon TPT,
This is achieved by forming an insulating film containing active hydrogen in the lI, removing the insulating film from the charge holding capacitor portion, forming a lower transparent electrode, and then performing heat treatment.
膜中に活性水素を含む絶縁膜を電荷保持キャパシタ以外
の部分に選択的に被着形成し、膜中の水素を熱拡散させ
て水素化を行うため、電荷保持キャパシタ部の下部透明
電極が水素プラズマ雰囲気にさらされない。よって、電
荷保持用キャパシタを付加した多結晶シリコンＴＰＴに
おいても、ＩＴＯ膜等から成る下部透明電極を変質させ
ることなく、多結晶シリコン膜を選択的に水素化するこ
とができる。An insulating film containing active hydrogen is selectively deposited on parts other than the charge retention capacitor, and the hydrogen in the film is thermally diffused to perform hydrogenation. Not exposed to plasma atmosphere. Therefore, even in a polycrystalline silicon TPT to which a charge retention capacitor is added, the polycrystalline silicon film can be selectively hydrogenated without altering the lower transparent electrode made of an ITO film or the like.
以下、本発明の詳細な説明する。第１図は本発明による
多結晶シリコンＴＰＴの一画素分の製造工程ごとの断面
構造図を示す、第１図（ｅ）が完成図であり、第１＠（
ｇ）中１１１がスイッチング用ＴＦＴ部１１２が電荷保
持用キャパシタ部である。まず第１図（ａ）のにように
ガラス基板１０１上にＣＶＤ法により多結晶シリコン膜
１０２を形成し、ホト・エツチングにより島状に加工す
る次に第１図（ｂ）の様にゲート酸化膜１０３、ゲート
電極となる多結晶シリコン膜１０４をそれぞれＣＶＤ法
で形成し、ホト・エツチングによりゲート酸化膜、ゲー
ト電極形状を形成する。次いで、イオン打ち込み、熱拡
散等によって不純物をドーブレ・ソース・ドレイン領域
１０５を形成する０本実施例においては、ゲート酸化膜
をＣＶＤ法で形成しているが、第３図に示した従来構造
の様に多結晶シリコン膜１０２を熱酸化して形成しても
よい。次に第１図（ｃ）の様に活性水素を含む窒化シリ
コン膜１０６をプラズマＣＶＤ法で全面に形成後１．ホ
ト・エツチングにょ°り電荷保持用キャパシタ部１１２
の部分だけ窒化シリコン膜１０６を除去する０次に、第
１図（ｄ）のようにスパッタ法でＩＴＯ膜１０７を形成
し、ホト・エツチングにより下部透明電極形状を形成す
る。次に第１図（ｅ）のように、層間絶縁膜としてＣＶ
Ｄ法により形成したＰＳＧ膜１０８を全面に形成する０
次に第１図（ｆ）のようにホト・エツチングによりソー
ス・ドレイン領域１０５上にコンタクトのためのスルー
ホールを形成し、ＡＱ電極１０９を形成する。次いで、
Ｎｚ雰囲気、４５０℃で熱処理を行い、窒化シリコン膜
１０６中の活性水素を電荷保持用キャパシタ部１１２を
除いたスイッチング用ＴＦＴ部１１１の多結晶シリコン
膜１０２中に熱拡散させ、選択的に水素化する。最後に
第１図（ｇ）のようにＩＴＯ膜１１０を形成し、ホト・
エツチングにより画素電極形状を形成する。The present invention will be explained in detail below. FIG. 1 shows a cross-sectional structure diagram for each manufacturing process for one pixel of polycrystalline silicon TPT according to the present invention. FIG. 1(e) is a completed diagram, and FIG.
g) The switching TFT section 112 shown in the middle 111 is a charge holding capacitor section. First, as shown in FIG. 1(a), a polycrystalline silicon film 102 is formed on a glass substrate 101 by the CVD method, processed into an island shape by photo-etching, and then gate oxidized as shown in FIG. 1(b). A film 103 and a polycrystalline silicon film 104 which will become a gate electrode are formed by CVD, and a gate oxide film and gate electrode shape are formed by photo-etching. Next, impurities are added by ion implantation, thermal diffusion, etc. to form the doble source/drain regions 105. In this embodiment, the gate oxide film is formed by the CVD method, but the conventional structure shown in FIG. Similarly, the polycrystalline silicon film 102 may be formed by thermal oxidation. Next, as shown in FIG. 1(c), a silicon nitride film 106 containing active hydrogen is formed on the entire surface by plasma CVD. Photo-etched charge holding capacitor section 112
Next, as shown in FIG. 1(d), an ITO film 107 is formed by sputtering, and a lower transparent electrode shape is formed by photo-etching. Next, as shown in FIG. 1(e), CV
A PSG film 108 formed by method D is formed on the entire surface.
Next, as shown in FIG. 1(f), through holes for contact are formed on the source/drain regions 105 by photo-etching, and AQ electrodes 109 are formed. Then,
Heat treatment is performed at 450° C. in a Nz atmosphere to thermally diffuse active hydrogen in the silicon nitride film 106 into the polycrystalline silicon film 102 of the switching TFT section 111 excluding the charge retention capacitor section 112, thereby selectively hydrogenating it. do. Finally, as shown in FIG. 1(g), an ITO film 110 is formed and
A pixel electrode shape is formed by etching.
第１図（ｅ）の工程の熱処理雰囲気をＮｚ雰囲気とする
ことにより、多結晶シリコン膜１０２の水素化とへ〇電
極１０９のシンターを同時に行うことができる。また、
同然処理工程は、第１図（ｃ）の窒化シリコン膜形成後
であれば、いつでもよい。By setting the heat treatment atmosphere in the step of FIG. 1(e) to a Nz atmosphere, hydrogenation of the polycrystalline silicon film 102 and sintering of the 〇 electrode 109 can be performed simultaneously. Also,
The process may be carried out at any time after the silicon nitride film shown in FIG. 1(c) is formed.
以上の様に本発明によれば、保護膜を形成しなくても、
酸化スズ、酸化インジウム、ＩＴＯＩＩ等から成る下部
透明電極を水素プラズマ雰囲気により還元、変質させる
ことなく、スイッチングＴＦＴ部の多結晶シリコン膜を
選択的に水素化できる。As described above, according to the present invention, even without forming a protective film,
The polycrystalline silicon film of the switching TFT section can be selectively hydrogenated without reducing or deteriorating the lower transparent electrode made of tin oxide, indium oxide, ITOII, etc. in a hydrogen plasma atmosphere.
また、上記実施例においては、スイッチングＴＦＴ部の
眉間絶ｌｌ１ｉ膜が窒化シリコン膜１０６とＰＳＧ膜１
０８の積層構造となるため、ゲート電極とソース・ドレ
イン電極のクロス部の耐圧は、窒化シリコン膜１０６が
ない場合に比較して有利となる。Further, in the above embodiment, the interglabellar film 11i of the switching TFT section is the silicon nitride film 106 and the PSG film 1.
08 layered structure, the breakdown voltage at the cross section between the gate electrode and the source/drain electrode is more advantageous than in the case where the silicon nitride film 106 is not provided.
また、上記実施例において、窒化シリコン膜１０６は、
膜中に活性水素を含む絶縁膜であれば何でもよい。Further, in the above embodiment, the silicon nitride film 106 is
Any insulating film containing active hydrogen may be used.
本発明によれば、電荷保持用キャパシタを付加した多結
晶シリコンＴＰＴにおいてもＩＴＯ膜等から成る下部電
極を変質させることなく、多結晶シリコン膜を選択的に
水素化することができる。According to the present invention, it is possible to selectively hydrogenate a polycrystalline silicon film even in a polycrystalline silicon TPT with a charge retention capacitor added thereto, without altering the lower electrode made of an ITO film or the like.
よって、薄膜トランジスタ特性が良好で画質の優れた液
晶表示パネルが得られる。Therefore, a liquid crystal display panel with good thin film transistor characteristics and excellent image quality can be obtained.
第１図は本発明の実施例を示す図、第２図及び第３図は
従来例の多結晶シリコンＴＰＴの等価回路及びその断面
構造図である。
１゛０１・・・ガラス基板、１０２・・・多結晶シリコ
ン膜、１０３・・・ゲート酸化膜、１０４・・・ゲート
電極、１０５・・・ソース・ドレイン領域、１０６・・
・窒化シリコン膜、１０７・・・下部透明電極（ＩＴＯ
膜）、１０８・・・層間絶縁膜、１０９・・・ＡＱ電極
、１１０・・・画素電極（ＩＴＯ膜）、１１１・・・ス
イッチング用ＴＦＴ部、１１２・・・電荷保持用キャパ
シタ部。
第１図
ＩＩＩ １１２FIG. 1 is a diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are an equivalent circuit and a cross-sectional structural diagram of a conventional polycrystalline silicon TPT. 1゛01... Glass substrate, 102... Polycrystalline silicon film, 103... Gate oxide film, 104... Gate electrode, 105... Source/drain region, 106...
・Silicon nitride film, 107...lower transparent electrode (ITO
film), 108... interlayer insulating film, 109... AQ electrode, 110... pixel electrode (ITO film), 111... switching TFT section, 112... charge retention capacitor section. Figure 1 III 112
Claims (1)
ャパシタを有する多結晶シリコン薄膜トランジスタにお
いて、ゲート電極形成後、膜中に活性水素を含む絶縁膜
を形成し、少なくとも電荷保持用キャパシタ部の該絶縁
膜を除去した後、電荷保持用キャパシタ部の下部透明電
極を形成し、次いで熱処理することを特徴とする多結晶
シリコン薄膜トランジスタ。 ２、第１項記載の多結晶シリコン薄膜トランジスタにお
いて、該絶縁膜としてプラズマＣＶＤ法により被着形成
した窒化シリコン膜を用いたことを特徴とする多結晶シ
リコン薄膜トランジスタ。 ３、第１項記載の多結晶シリコン薄膜トランジスタにお
いて、該透明電極として酸化インジウム、酸化スズ、酸
化インジウムスズ等の金属酸化物トランジスタ。 ４、第１項記載の多結晶シリコン薄膜トランジスタにお
いて、該絶縁膜をゲート電極とソース・ドレイン電極の
間の層間絶縁膜に用いたことを特徴とする多結晶シリコ
ン薄膜トランジスタ。[Claims] 1. In a polycrystalline silicon thin film transistor having a charge retention capacitor having a structure in which an insulating film is sandwiched between transparent conductive films, after forming a gate electrode, an insulating film containing active hydrogen is formed in the film, and at least A polycrystalline silicon thin film transistor characterized in that after the insulating film of the charge retention capacitor part is removed, a lower transparent electrode of the charge retention capacitor part is formed and then heat treated. 2. The polycrystalline silicon thin film transistor according to item 1, wherein a silicon nitride film deposited by plasma CVD is used as the insulating film. 3. In the polycrystalline silicon thin film transistor according to item 1, the transparent electrode is a metal oxide transistor such as indium oxide, tin oxide, or indium tin oxide. 4. The polycrystalline silicon thin film transistor according to item 1, wherein the insulating film is used as an interlayer insulating film between the gate electrode and the source/drain electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63229989A JPH0279027A (en) | 1988-09-16 | 1988-09-16 | Polycrystalline silicon thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63229989A JPH0279027A (en) | 1988-09-16 | 1988-09-16 | Polycrystalline silicon thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0279027A true JPH0279027A (en) | 1990-03-19 |
Family
ID=16900858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63229989A Pending JPH0279027A (en) | 1988-09-16 | 1988-09-16 | Polycrystalline silicon thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0279027A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100399179C (en) * | 2004-09-22 | 2008-07-02 | 中华映管股份有限公司 | Pixel structure of liquid crystal panel and manufacturing method and driving method thereof |
| US7855106B2 (en) | 1991-08-26 | 2010-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| CN109155166A (en) * | 2016-05-13 | 2019-01-04 | 株式会社钟化 | Transparent conducting film and its manufacturing method |
| WO2019186924A1 (en) * | 2018-03-29 | 2019-10-03 | シャープ株式会社 | Display device and production method for display device |
-
1988
- 1988-09-16 JP JP63229989A patent/JPH0279027A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7855106B2 (en) | 1991-08-26 | 2010-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| CN100399179C (en) * | 2004-09-22 | 2008-07-02 | 中华映管股份有限公司 | Pixel structure of liquid crystal panel and manufacturing method and driving method thereof |
| CN109155166A (en) * | 2016-05-13 | 2019-01-04 | 株式会社钟化 | Transparent conducting film and its manufacturing method |
| WO2019186924A1 (en) * | 2018-03-29 | 2019-10-03 | シャープ株式会社 | Display device and production method for display device |
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