JPH10133231A - Multilayered wiring structure and its production, thin-film transistor array and its production as well as liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To embody a TFT(thin-film transistor) array with which the shorting defects in the overlapping parts of intersected parts of gate wirings and source and drain wrings may be decreased. SOLUTION: A semiconductor layer 2, a gate insulating layer 3 and a conductive thin film 4 are formed on a translucent glass substrate 1. Gate electrodes 4a, the gate wirings 4c and extraction wirings 14 for anodic oxidation are formed by working the conductivet thin film 4. The gate wirings 4c of the regions overlapping on the source drain electrode wirings 10 by intersection, etc., are anodically oxidized to form anodically oxidized insulating layers 12. After the formation of the source-drain regions 6 of a P type, the conductive thin film 4 is worked to form the gate electrodes 4b and simultaneously the extraction wirings 14 for anodic oxidation are removed. After the formation of the source-drain regions 6 of an N type, a first interlayer insulating layer 7, pixel electrodes 8 and a second interlayer insulating layer 9 are formed and sourcedrain electrode wirings 10 and a protective insulating layer 11 are formed and are opened above the pixel electrodes 8. The shorting defects between the gate wirings 4c and the source drain electrode wirings 10 are decreased by the anodically oxidized insulating layers 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure used for a semiconductor device and the like, a method of manufacturing the same, a thin film transistor array and a method of manufacturing the same, and a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, a liquid crystal display device is mounted on a viewfinder of a home video camera, a notebook computer, and the like. Among these liquid crystal display devices, an active matrix type liquid crystal display device capable of displaying a high quality image is provided. Has received particular attention. In this active matrix type liquid crystal display device, as a switching element of a pixel electrode,
Thin Film Transi
(hereinafter, abbreviated as TFT) is often used.

An example of such a TFT is disclosed in Japanese Patent Application No. Hei.
No. 0680. Hereinafter, the TFT array shown in FIG. 4 will be described as an example. FIG. 4 is a sectional view of a main part of a TFT array used in a conventional liquid crystal display device. First, a semiconductor layer 2 is formed on a translucent glass substrate 1, and a gate insulating layer 3 is formed thereon. Then, a conductive thin film serving as a gate electrode wiring is formed on the gate insulating layer 3a, and the conductive thin film is processed to form a gate electrode 4a and a gate wiring 4c. By introducing impurities into some regions, P
A source / drain region 5 is formed. Further, after processing the conductive thin film to form the gate electrode 4b, impurities are introduced into a part of the semiconductor layer 2 using the gate electrode 4b as a mask to form the N-type source / drain regions 6. After forming a first interlayer insulating layer 7 thereon, a pixel electrode 8 and a second interlayer insulating layer 9 are formed. Next, a contact hole is opened, a source / drain electrode wiring 10 is formed of titanium or the like, a protective insulating layer 11 is formed thereon, and an opening is formed on the pixel electrode 8 to complete a TFT array.

An example in which P-type and N-type TFTs are formed on a TFT array substrate and a pixel TFT and a circuit for driving the pixel TFT are formed is described in the International Display Research Conference, 1994, pp. 414-417 and 418. 421 pages (1994 International)
onal Display Research Con
reference: pages 418 to 421).

[0005]

In a conventional TFT array for a liquid crystal display device, a gate wiring and a source wiring are arranged in a matrix in a matrix so as to drive a pixel TFT in a screen portion. In many cases, a short-circuit failure or the like in an overlapping portion such as a portion occurs. Further, a circuit for driving a pixel TFT may be formed on a TFT array substrate. In this circuit portion, a multi-layer wiring is frequently used and has the same problem. In order to reduce this, it was necessary to form an interlayer insulating film between wirings to be sufficiently thick. However, in this case, there are disadvantages such as an increase in the burden on the post-process such as an increase in the process of forming the contact hole in the interlayer insulating film, an increase in the process time due to an increase in the thickness of the source / drain electrodes, and the like. Therefore, there has been a demand for a method of easily reducing a short circuit in an overlapping portion such as the intersection of the upper and lower wirings. Such a problem is also found in a multilayer wiring structure such as a semiconductor device.

An object of the present invention is to provide a multilayer wiring structure capable of reducing a short-circuit defect at an overlapping portion such as an intersection of a multilayer wiring and a method of manufacturing the same. Also,
It is another object of the present invention to provide a TFT array capable of reducing short-circuit defects at an overlapping portion such as an intersection between a gate wiring and a source / drain wiring, and a method of manufacturing the same.

Another object of the present invention is to provide a liquid crystal display device capable of reducing a short-circuit defect at an overlapping portion such as an intersection between a gate wiring and a source wiring in a TFT array substrate.

[0008]

According to a first aspect of the present invention, there is provided a multilayer wiring structure having a lower wiring and an upper wiring at least partially overlapping on a substrate, wherein at least an upper wiring of the lower wiring is provided. Characterized in that an anodic oxide insulating layer is formed in the overlapping portion of According to this configuration, by forming the anodized insulating layer at least in the overlapping portion of the lower wiring and the upper wiring, the anodized insulating layer has few pinholes, has a high withstand voltage, and has good coverage and good quality. Since the insulating film is used, a short-circuit defect at an overlapping portion such as an intersection between a lower wiring and an upper wiring can be reduced.

According to a second aspect of the present invention, there is provided a multilayer wiring structure.
In the multilayer wiring structure described above, an interlayer insulating layer is formed between the lower wiring having the anodic oxide insulating layer formed thereon and the upper wiring. According to this configuration, since the anodic oxide insulating layer, which is a high-quality insulating film, is formed on the lower wiring, it is possible to overlap the lower wiring and the upper wiring at intersections without increasing the thickness of the interlayer insulating layer. It is possible to reduce short-circuit defects in the part.

According to a third aspect of the present invention, there is provided a multilayer wiring structure.
In the multilayer wiring structure described in Item 2, the lower layer wiring is made of a material containing aluminum, tantalum, or silicon as a main component. As described above, by using a material containing aluminum, tantalum, or silicon as a main component for the lower wiring, anodic oxidation can be easily performed, and a higher quality insulating layer can be formed.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a multilayer wiring structure, wherein a lower wiring and an upper wiring at least partially overlapping on a substrate are formed. A first step of forming a lower layer wiring,
A second step of anodizing at least a portion of the lower wiring overlapping the upper wiring to form an anodic oxide insulating layer; and forming an upper wiring having an overlapping portion with the lower wiring at a portion where the anodic oxide insulating layer is formed. And a third step.

According to this manufacturing method, an anodized insulating layer is formed by anodizing at least a portion of the lower wiring overlapping with the upper wiring, so that the anodized insulating layer has a small number of pinholes and a high withstand voltage. In addition, since the insulating film has good coverage and good quality, a short-circuit defect at an overlapping portion such as an intersection between the lower wiring and the upper wiring can be reduced. According to a fifth aspect of the present invention, there is provided a method of manufacturing a multilayer wiring structure according to the fourth aspect, further comprising the step of forming an interlayer insulating layer after the second step and before the third step. It is characterized by the following.

According to this manufacturing method, since the anodic oxide insulating layer, which is a high quality insulating film, is formed on the lower wiring, the thickness of the interlayer insulating layer formed between the lower wiring and the upper wiring is increased. Even without this, it is possible to reduce short-circuit defects at overlapping portions such as intersections between the lower wiring and the upper wiring. According to a sixth aspect of the present invention, in the method of the fourth or fifth aspect, the lower layer wiring is formed of a material containing aluminum, tantalum or silicon as a main component. I do.

Thus, the lower layer wiring is made of aluminum,
By using a material containing tantalum or silicon as a main component, anodic oxidation can be easily performed, and a higher-quality insulating layer can be formed. 8. The thin film transistor array according to claim 7, wherein the gate wiring and the source / drain wiring of the plurality of thin film transistors overlap at least partially, and the gate wiring is located below the source / drain wiring at the overlapping portion of the gate wiring and the source / drain wiring. The thin film transistor array described above, wherein an anodic oxide insulating layer is formed at least in an overlapping portion of the gate wiring with the source / drain wiring.

According to this structure, since the anodic oxide insulating layer is formed at least in the portion where the gate wiring overlaps with the source / drain wiring, the anodic oxide insulating layer has a small number of pinholes, a high withstand voltage, and a high coating density. Since the insulating film has good properties and a high quality, a short-circuit defect at an overlapping portion such as an intersection between a gate wiring and a source / drain wiring can be reduced.

The thin film transistor array according to claim 8 is the thin film transistor array according to claim 7,
An interlayer insulating layer is formed between the gate wiring on which the anodized insulating layer is formed and the source / drain wiring. According to this configuration, since the anodic oxide insulating layer, which is a high-quality insulating film, is formed on the gate wiring, the intersection of the gate wiring and the source / drain wiring can be formed without increasing the thickness of the interlayer insulating layer. Short-circuit defects at the overlapping portions can be reduced.

According to a ninth aspect of the present invention, in the thin film transistor array of the seventh or eighth aspect, the gate wiring is made of a material containing aluminum or tantalum as a main component. In this manner, by using a material containing aluminum or tantalum as a main component for the gate wiring forming the anodic oxide insulating layer, anodic oxidation can be easily performed, and a higher quality insulating layer can be formed.

According to a tenth aspect of the invention, there is provided a method of manufacturing a thin film transistor array, comprising: a first step of forming a semiconductor layer of a thin film transistor having one conductivity type channel and another conductivity type channel on a substrate having an insulating surface; A second step of forming a gate insulating layer, a third step of forming an anodically oxidizable conductive thin film on the substrate on which the gate insulating layer is formed, and processing a part of the conductive thin film into a predetermined shape. Forming a gate line and a gate electrode of a thin film transistor of one conductivity type channel by anodizing a predetermined region of the gate line to form an anodized insulating layer; Forming an impurity into a semiconductor layer of a thin film transistor of one conductivity type by using a gate electrode of the thin film transistor as a mask to form a source / drain region of one conductivity type; A seventh step of processing the remaining portion of the conductive thin film into a predetermined shape to form a gate electrode of the thin film transistor of the other conductivity type, and a step of forming the other conductive type using the gate electrode of the thin film transistor of the other conductivity type as a mask. An eighth step of introducing impurities into the semiconductor layer of the thin film transistor of the type channel to form source / drain regions of the other conductivity type; Conductive source
A ninth step of forming a source / drain electrode wiring electrically connected to the drain region.

According to this manufacturing method, there is provided a method of manufacturing a thin film transistor array having thin film transistors of one conductivity type channel and another conductivity type channel, wherein an anodized insulating layer is formed at an overlapping portion between a source / drain electrode wiring and a lower gate wiring. Forming the gate wiring and the source
Short-circuit defects at an overlapping portion such as an intersection with the drain electrode wiring can be reduced.

A method of manufacturing a thin film transistor array according to an eleventh aspect is characterized in that, in the method of manufacturing a thin film transistor array according to the tenth aspect, the fifth step is performed after the sixth step. As described above, either of the fifth step of forming the anodic oxide insulating layer on the gate wiring and the sixth step of forming the source / drain region of one conductivity type may be performed first.

According to a twelfth aspect of the present invention, in the method of the tenth or eleventh aspect, an interlayer insulating layer is formed after the eighth step and before the ninth step. It is characterized by having a process. According to this manufacturing method, the interlayer insulating layer is formed between the gate wiring and the source / drain electrode wiring, and the anodic oxide insulating layer, which is a high-quality insulating film, is formed on the gate wiring. Even if the film thickness is not increased, a short-circuit defect at an overlapping portion such as an intersection between a gate wiring and a source / drain electrode wiring can be reduced.

According to a thirteenth aspect of the present invention, in the method of manufacturing a thin film transistor array according to the tenth, eleventh, or twelfth aspect, in the fourth step, the voltage during anodic oxidation is obtained by processing the conductive thin film. It is characterized in that the application wiring is formed simultaneously. As described above, the voltage application wiring at the time of anodic oxidation is formed by the conductive thin film forming the gate wiring and the gate electrode, and is formed simultaneously with the gate wiring and the gate electrode of the thin film transistor of one conductivity type channel. It is not necessary to newly provide a step for forming a voltage application wiring at the time of oxidation.

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a thin film transistor array according to the thirteenth aspect, wherein the conductive thin film is processed in the seventh step to form a wiring for voltage application during anodic oxidation. The removal is performed simultaneously. Thus, by removing the voltage application wiring at the time of anodic oxidation simultaneously with the formation of the gate electrode of the thin film transistor of the other conductivity type channel,
It is not necessary to newly provide a step for removing the voltage application wiring at the time of anodic oxidation.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a thin film transistor array according to the tenth aspect.
4. The method for manufacturing a thin film transistor array according to item 4,
The conductive thin film is formed using a material mainly containing aluminum or tantalum. As described above, by using a material mainly containing aluminum or tantalum for the conductive thin film serving as the gate wiring for forming the anodic oxide insulating layer, anodic oxidation can be easily performed, and a higher quality insulating layer is formed. be able to.

In the liquid crystal display device according to the present invention, a drain electrode of a thin film transistor is connected to each pixel electrode arranged in a matrix, and a gate wiring and a source wiring of the thin film transistor are arranged in a lattice between the pixel electrodes; In an overlapping portion of the gate wiring and the source wiring, a liquid crystal display device in which liquid crystal is sandwiched between a thin film transistor array substrate in which the gate wiring is located below the source wiring and a counter substrate provided with a transparent electrode opposed to the pixel electrode is provided. In addition, an anodic oxide insulating layer is formed at least at a portion where the gate wiring of the thin film transistor array substrate overlaps with the source wiring.

According to this structure, since the anodic oxide insulating layer is formed at least at the portion where the gate wiring of the thin film transistor array substrate overlaps with the source wiring, the anodic oxide insulating layer has a small number of pinholes and a high withstand voltage. In addition, since the insulating film is a high-quality insulating film with good coverage, a short-circuit defect at an overlapping portion such as an intersection between a gate wiring and a source wiring can be reduced.

According to a seventeenth aspect of the present invention, in the liquid crystal display device of the sixteenth aspect, an interlayer insulating layer is formed between the gate wiring and the source wiring of the thin film transistor array substrate on which the anodic oxide insulating layer is formed. I have. According to this configuration, since the anodic oxide insulating layer, which is a high-quality insulating film, is formed on the gate wiring, it is possible to overlap the intersection of the gate wiring and the source wiring without increasing the thickness of the interlayer insulating layer. It is possible to reduce short-circuit defects in the part.

The liquid crystal display device according to claim 18 is the liquid crystal display device according to claim 16 or 17, wherein the gate wiring of the thin film transistor array substrate is made of a material containing aluminum or tantalum as a main component. in this way,
By using a material containing aluminum or tantalum as a main component for a gate wiring for forming an anodic oxide insulating layer, anodic oxidation can be easily performed, and a higher quality insulating layer can be formed.

[0029]

Embodiments of the present invention will be described below. [First Embodiment] FIG. 1 is a process sectional view showing a method for manufacturing a TFT array according to a first embodiment of the present invention.
Here, an example of a manufacturing process of a coplanar TFT array will be described.

First, as a precursor of the semiconductor layer 2, a film thickness of 50 n was formed on a light transmitting glass substrate 1 by a plasma CVD method.
An amorphous silicon film having a thickness of m is formed and processed into an island shape using photolithography and etching. Next, heat treatment is performed at 400 ° C. for 3 hours in a vacuum of, for example, about 1 mTorr to reduce the content of hydrogen atoms in the amorphous silicon. This is to prevent a large amount of hydrogen from being rapidly released from the film and causing ablation at the time of the next laser light irradiation, thereby preventing the surface state of the film from being deteriorated.
Next, for example, a 308 nm wavelength XeCl laser is
Irradiation is performed at an energy density of about 500 mJ / cm ² to crystallize to form polycrystalline silicon as the semiconductor layer 2 (FIG. 1A).

Thereafter, normal pressure CVD is performed as the gate insulating layer 3.
A silicon dioxide film having a thickness of 100 nm is formed by the method.
On the gate insulating layer 3, for example, a 350 nm-thick aluminum film is formed as a conductive thin film 4 that can be anodized by a sputtering method (FIG. 1B). Thereafter, the conductive thin film 4 is formed using photolithography and etching.
Is processed into a shape as shown in FIG. By this processing, a gate electrode 4a, a gate wiring 4c and a lead-out wiring 14 for anodic oxidation of a P-type (one conductivity type) channel TFT are formed. At this time, the N-type (other conductivity type) channel TFT region is covered with the conductive thin film 4.

Thereafter, as shown in FIG. 1D, an anodizing mask 13 having an opening in the region to be anodized is formed using, for example, an insulating photoresist or the like. Then, anodic oxidation is performed on the portion where the mask is opened. For example, the array substrate and the platinum electrode are immersed in a chemical solution prepared by mixing ethylene glycol and nitric acid so that the pH becomes neutral, and a voltage of 140 V is applied to the array substrate using the lead-out wiring 14 for anodic oxidation. Gate wiring 4c is anodized to about 200n
An anodic oxide insulating layer 12 of aluminum oxide is formed. The anodic oxide insulating layer 12 is formed in an overlapping region such as the intersection of the gate wiring 4c and the source / drain electrode wiring 10 (see FIG. 1H).

Then, after removing the anodic oxidation mask 13, as a first doping step, boron and boron are applied to a predetermined semiconductor layer 2 by ion shower doping, for example, using the gate electrode 4 a and the conductive thin film 4 as a mask. By doping with hydrogen, a P-type source / drain region 5 is formed (FIG. 1E). The ion shower doping method referred to here is a method in which ion species including an element to be implanted are accelerated without mass separation, and a source / drain region formed by this method is kept at a low temperature of about 400 ° C. But it is known to be activated.

Next, the conductive thin film 4 is processed into a shape as shown in FIG. 1F by using photolithography and etching. By this processing, N-type channel TFT
At the same time as forming the gate electrode 4b of FIG. Next, using the gate electrode 4b as a mask, the predetermined semiconductor layer 2 is doped with phosphorus and hydrogen by an ion shower doping method to form N-type source / drain regions 6. However, the P-type source / drain region 5 formed in the previous step is prevented from becoming N-type by, for example, making the boron in the first doping step larger than the dose of phosphorus in the second doping step. There is a need.

Then, as the first interlayer insulating layer 7, for example, 300 nm-thick silicon dioxide is formed by the normal pressure CVD method, and then the ITO is formed as the pixel electrode 8 by the sputtering method.
A thin film is deposited to a thickness of 100 nm and processed into a predetermined shape by photolithography and etching. Furthermore, the second
The thickness of the interlayer insulating layer 9 is, for example, 2
A 00 nm silicon dioxide is formed (FIG. 1 (g)).

Thereafter, a contact hole is formed by photolithography and etching, and a titanium film having a thickness of, for example, 700 nm is formed as the source / drain electrode wiring 10 by a sputtering method and processed into a predetermined shape. Next, a 700 nm silicon nitride film is deposited as a protective insulating layer 11 by a plasma CVD method, and an opening is formed in the pixel electrode 8 and a wiring connection portion (not shown) with the outside to complete a TFT array (FIG. 1 (h)). )).

In the above manufacturing method, FIG.
And the step of FIG. 1E may be performed in reverse. That is, the gate electrode 4a and the gate wiring 4c shown in FIG.
After forming the lead-out wiring 14 for anodic oxidation, a P-type source / drain region 5 is formed in a predetermined semiconductor layer 2, and thereafter, a mask 13 for anodic oxidation is formed, and anodic oxidation of the gate wiring 4 c is performed. An anodic oxide insulating layer 12 is formed. Thereafter, the mask 13 for anodic oxidation is removed, and FIG.
The (f) formation of the gate electrode 4b and the removal of the anodizing lead wire 14 may be performed to form the N-type source / drain region 6.

In the above embodiment, the one conductivity type is P
Although the type has been described as being N-type and the other conductivity type has been described as N-type, it is needless to say that one conductivity type may be N-type and the other conductivity type may be P-type. According to the first embodiment, the gate wiring 4
Since the gate wiring 4c is anodically oxidized to form an anodic oxide insulating layer 12 at an overlapping portion such as the intersection of the c and the source / drain electrode wiring 10, the gate wiring 4c and the source / drain electrode wiring 10 It is possible to reduce the occurrence of short-circuit defects between them. In addition, the anodic oxidation insulating layer 12 formed by the anodic oxidation method can provide a high-quality insulating film with few pinholes, high withstand voltage, and good coverage.

In forming the anodic oxide insulating layer 12,
The lead wire 14 for anodic oxidation is connected to the gate electrode wire (4a,
4b, 4c) and the same material as the gate electrode wiring (4b, 4c).
a, 4b, 4c) for forming conductive thin film 4 twice
The formation and removal of the lead-out wiring 14 for anodic oxidation can be performed in accordance with the shape processing described above. There is no significant increase or change.

According to this embodiment, the source / drain regions 5, 6 formed by the ion shower doping method can be activated at a low temperature of about 400 ° C. as described above. Is about 450 ° C. in the process of forming silicon dioxide by normal pressure CVD. As described above, since the substrate temperature can be set to 500 ° C. or lower in all the manufacturing steps, an inexpensive alkali-free glass substrate can be used as the translucent glass substrate 1.

In this embodiment, as a method of forming a precursor (amorphous silicon) of the semiconductor layer 2, the plasma C
Although the VD method is used, any method that can form a predetermined precursor, such as a low pressure CVD method, a sputtering method, a vacuum evaporation method, or a photo CVD method, may be used. In this embodiment, the precursor (amorphous silicon) of the semiconductor layer 2 is irradiated with XeCl laser light in order to crystallize the precursor. However, any method can be used as long as the precursor can be crystallized. Irradiation with laser light, irradiation with lamp light, or thermal annealing with a furnace may be used.

In this embodiment, the semiconductor layer 2
In this example, polycrystalline silicon formed by irradiating amorphous silicon with XeCl laser light was used. However, any material that functions as a semiconductor may be used, such as directly deposited polycrystalline silicon or solid-grown polycrystalline silicon formed by heat. Any method can be used. In addition to polycrystalline silicon, amorphous silicon,
Microcrystalline silicon, single crystal silicon, polycrystalline silicon germanium, germanium, gallium arsenide, or the like may be used.

In this embodiment, silicon dioxide formed by the normal pressure CVD method is used as the gate insulating layer 3. However, any material can be used as long as it functions as the gate insulating layer 3, such as a low pressure CVD method or a plasma CVD method. It may be silicon dioxide, silicon nitride, tantalum oxide, or the like formed by a film forming method such as a sputtering method, a sputtering method, or an ECR-CVD method.

In this embodiment, the conductive thin film 4 for forming the gate electrode wirings (4a, 4b, 4c) is used.
Although aluminum is used as the material, any material that can be anodized and functions as an electrode wiring may be used. For example, a material containing aluminum or tantalum as a main component or polycrystalline silicon doped with a large amount of impurities may be used. In addition,
By using a material containing aluminum or tantalum as a main component, anodic oxidation can be easily performed, and a higher-quality insulating layer can be formed.

In this embodiment, the ion shower doping method is used as a method for introducing a predetermined element. However, any method capable of introducing a predetermined element may be used, such as an ion implantation method or a plasma doping method. It may be a law. In this embodiment, phosphorus is used as a donor for forming the source / drain regions 5 and 6, and boron is used as an acceptor. However, in the case of manufacturing an N-channel TFT, if an arsenic such as arsenic works as a donor. Any material may be used, and when manufacturing a P-channel TFT, any material that works as an acceptor, such as aluminum, may be used.

In this embodiment, titanium is used as the source / drain electrode wiring 10. However, any material can be used as long as it functions as an electrode. For example, chromium, tantalum, molybdenum, aluminum, etc. Or a transparent conductive layer such as ITO (indium tin oxide). In addition,
In this embodiment, as the interlayer insulating layers 7 and 9, a normal pressure CV
Although silicon dioxide formed by the method D was used, any material can be used as long as it functions as an insulating layer.
D method, plasma CVD method, sputtering method, or ECR-
Silicon nitride, tantalum oxide, or the like formed using a film formation technique such as a CVD method may be used.

If the anodized insulating layer 12 formed on the gate wiring 4c has a sufficient withstand voltage, no interlayer insulating layer is required on the anodized insulating layer 12. In the first embodiment, the translucent glass substrate 1 is used because it is a TFT array for a transmissive liquid crystal display device. However, any transparent substrate having an insulating surface may be used. A substrate may be used. In the case of a TFT array for a light reflection type liquid crystal display device or a TFT array not limited to a liquid crystal display device, a crystalline silicon substrate or a metal plate having silicon dioxide formed on the surface may be used.

In the first embodiment, the TFT array has been described. However, the upper wiring is arranged on the substrate so as to cross the lower wiring or to be arranged along the lower wiring.
In a multilayer wiring structure having an overlapping portion where the upper wiring and the lower wiring overlap at least partially, by forming an anodic oxide insulating layer at least in the overlapping portion of the lower wiring with the upper wiring, the intersection between the lower wiring and the upper wiring is formed. Short-circuit defects at overlapping portions such as portions can be reduced. The manufacturing method in this case is such that after forming a lower layer wiring made of an anodizable material on a substrate, the lower layer wiring is anodized in the same manner as the gate wiring 4c in the first embodiment, and the lower wiring is formed. An anodic oxide insulating layer is formed at least in an overlapping portion such as an intersection with the upper wiring. Then, after forming an interlayer insulating layer, an upper layer wiring is formed. Note that the interlayer insulating layer is not necessary when only the anodized insulating layer has a sufficient withstand voltage.

In this case, by using a material containing aluminum, tantalum, or silicon as a main component for the lower wiring, anodic oxidation can be easily performed, and a high-quality insulating layer can be formed. Note that a material containing silicon as a main component (for example, polycrystalline silicon doped with a large amount of silicon) has a high resistance as a gate wiring of a liquid crystal display device, and therefore cannot be used for a gate wiring of a liquid crystal display device. Further, as the substrate, any surface may be used as long as it has insulating properties.
A glass substrate, a plastic substrate, a crystalline silicon substrate having a surface on which an insulating film such as silicon dioxide is formed, a metal plate, or the like may be used.

[Second Embodiment] In the second embodiment, a TF manufactured by the same process as that of the first embodiment is used.
A liquid crystal display device manufactured using a T array substrate will be described. FIG. 2 is a conceptual diagram showing a planar arrangement of a TFT array substrate manufactured in the same manner as in the first embodiment.
FIG. 3 is a conceptual diagram showing a cross-sectional configuration of a liquid crystal display device manufactured using this TFT array substrate. 2, reference numeral 21 denotes a TFT, 22 denotes a gate wiring, 23 denotes a source wiring, 24 denotes a pixel electrode, 25 denotes a driving circuit constituted by a TFT for applying a scanning signal to the gate wiring 22, and 26 denotes an image on the source wiring 23. A driving circuit 30 composed of TFTs for giving the signal V _S , and 30 is a TFT array substrate. FIG.
In the figure, 31 is a counter substrate having a transparent counter electrode 33 formed on a translucent glass substrate 32, 34 is an alignment layer, 35 is a liquid crystal, 36 is a peripheral sealing agent, 37 is a polarizing plate, and 38 is a pad.

As shown in FIGS. 2A and 2B, the T and T used in the second embodiment and manufactured in the same process as in the first embodiment.
The FT array substrate 30 includes gate wirings 2 arranged in a grid.
2 and a screen region in which the TFTs 21 and pixel electrodes 24 connected to the source lines 23 are arranged in a matrix, and a CMOS-T for driving the TFTs 21 in this screen region.
A peripheral circuit (drive circuits 25, 26, etc.) using FT is provided. In an overlapping portion such as an intersection of the gate wiring 22 and the source wiring 23, an anodic oxide insulating layer ( (Not shown).

As shown in FIG. 3, in the liquid crystal display device of this embodiment, the surfaces of the TFT array substrate 30 and the opposing substrate 31 are subjected to an alignment treatment, and the alignment layer 34 is formed between the substrates 30 and 31. The liquid crystal 35 is sealed, and both substrates 30, 3
A pair of polarizing plates 37 are attached to both outer sides of the device 1. The liquid crystal display device manufactured according to the second embodiment has a TF
In the T-array substrate 30, the anodic oxide insulating layer (not shown) is formed on the surface of the gate wiring 22 corresponding to an overlapping portion such as the intersection with the source wiring 23, so that the gate wiring 2
2 and the source wiring 23 can be reduced in occurrence of short-circuit defects.

[0053]

As described above, according to the present invention, in a multilayer wiring structure having a lower wiring and an upper wiring at least partially overlapping on a substrate, anodization is performed on at least an overlapping portion of the lower wiring with the upper wiring. By forming the insulating layer, the anodized insulating layer is a high-quality insulating film having few pinholes, high withstand voltage, and good coverage, and therefore, an overlapping portion such as an intersection between a lower wiring and an upper wiring. Short-circuit defects can be reduced.

In a thin film transistor array in which the gate wiring and the source / drain wiring of the plurality of thin film transistors overlap at least partially, and where the gate wiring and the source / drain wiring overlap each other, the gate wiring is located below the source / drain wiring. By forming the anodic oxide insulating layer at least at the overlapping portion of the gate wiring with the source / drain wiring, short-circuit defects at the overlapping portion such as the intersection of the gate wiring and the source / drain wiring can be reduced.

A drain electrode of the thin film transistor is connected to each pixel electrode arranged in a matrix, a gate wiring and a source wiring of the thin film transistor are arranged in a lattice between the pixel electrodes, and an overlapping portion of the gate wiring and the source wiring is formed. In a liquid crystal display device in which liquid crystal is sandwiched between a thin film transistor array substrate in which a gate wiring is positioned below a source wiring and a counter substrate provided with a transparent electrode opposed to a pixel electrode, a gate wiring of the thin film transistor array substrate is formed. By forming the anodic oxide insulating layer at least at the overlapping portion with the source wiring, short-circuit defects at the overlapping portion such as the intersection between the gate wiring and the source wiring of the thin film transistor array substrate can be reduced.

As described above, by forming the anodic oxide insulating layer on the lower wiring corresponding to the overlapping portion where the upper wiring crosses the lower wiring or is arranged along the lower wiring and overlaps with the lower wiring, the upper and lower wirings are formed. The insulation performance between wirings can be improved, and short circuit failure can be reduced.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a TFT array according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a planar arrangement configuration of a TFT array substrate according to a second embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a sectional configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a main part of a TFT array used in a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Translucent glass substrate 2 Semiconductor layer 3 Gate insulating layer 4 Conductive thin film 4a, 4b Gate electrode 4c Gate wiring 5 P-type source / drain region 6 N-type source / drain region 7 First interlayer insulating layer 8 Pixel Electrode 9 Second interlayer insulating layer 10 Source / drain electrode wiring 11 Protective insulating layer 12 Anodized insulating layer 13 Anodized mask 14 Anodized lead-out wiring 21 TFT 22 Gate wiring 23 Source wiring 24 Pixel electrode 25, 26 Drive circuit Reference Signs List 30 TFT array substrate 31 opposing substrate 32 translucent glass substrate 33 opposing electrode 34 alignment layer 35 liquid crystal 36 peripheral sealing agent 37 polarizing plate 38 pad

Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/336 H01L 29/78 617W (72) Inventor Tetsuya Kawamura 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yutaka Miyata 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (18)

[Claims] 1. A multilayer wiring structure having a lower wiring and an upper wiring at least partially overlapping a substrate, wherein an anodic oxide insulating layer is formed at least in an overlapping portion of the lower wiring with the upper wiring. The multilayer wiring structure characterized by the above. 2. The multilayer wiring structure according to claim 1, wherein an interlayer insulating layer is formed between the lower wiring having the anodic oxide insulating layer and the upper wiring. 3. The multilayer wiring structure according to claim 1, wherein the lower wiring is made of a material containing aluminum, tantalum or silicon as a main component. 4. A method of manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring at least partially overlapping on a substrate are formed, wherein a first step of forming the anodically oxidizable lower wiring on the substrate is performed. A second step of anodizing at least a portion of the lower wiring that overlaps with the upper wiring to form an anodized insulating layer; and having an overlapping portion with the lower wiring at a portion where the anodized insulating layer is formed. And a third step of forming the upper layer wiring. 5. The method according to claim 4, further comprising a step of forming an interlayer insulating layer after the second step and before the third step. 6. The method according to claim 4, wherein the lower wiring is formed of a material containing aluminum, tantalum or silicon as a main component. 7. A gate wiring and source / drain wiring of a plurality of thin film transistors overlap at least partially,
A thin film transistor array in which the gate wiring is located below the source / drain wiring in an overlapping portion of the gate wiring and the source / drain wiring, wherein at least an overlapping portion of the gate wiring with the source / drain wiring is anodized; A thin film transistor array having an insulating layer formed thereon. 8. The thin film transistor array according to claim 7, wherein an interlayer insulating layer is formed between the gate wiring on which the anodic oxide insulating layer is formed and the source / drain wiring. 9. The thin film transistor array according to claim 7, wherein the gate wiring is made of a material containing aluminum or tantalum as a main component. 10. A first step of forming a semiconductor layer of a thin film transistor having one conductivity type channel and another conductivity type channel on an insulating substrate, and a second step of forming a gate insulating layer on the semiconductor layer. A third step of forming an anodically oxidizable conductive thin film on the substrate on which the gate insulating layer is formed, and processing a part of the conductive thin film into a predetermined shape to form a gate wiring and one conductivity type. A fourth step of forming a gate electrode of the channel thin film transistor, a fifth step of anodizing a predetermined region of the gate wiring to form an anodic oxide insulating layer, and a gate electrode of the one conductivity type channel thin film transistor A sixth step of introducing impurities into the semiconductor layer of the one-conductivity-type channel thin film transistor by using as a mask to form one-conductivity-type source / drain regions; A seventh step of processing the remaining portion into a predetermined shape to form a gate electrode of the thin film transistor of the other conductivity type channel, and using the gate electrode of the thin film transistor of the other conductivity type channel as a mask. An eighth step of introducing a dopant into the semiconductor layer to form a source / drain region of another conductivity type, and an overlapping portion with the gate wiring on the anodic oxide insulating layer, wherein the one conductivity type and the other conductivity type are provided. Forming a source / drain electrode wiring electrically connected to the source / drain region of the ninth step. 11. The method according to claim 10, wherein the fifth step is performed after the sixth step. 12. After the eighth step and before the ninth step,
12. The method according to claim 10, further comprising a step of forming an interlayer insulating layer. 13. The method of manufacturing a thin film transistor array according to claim 10, wherein in the fourth step, a conductive thin film is processed to form a voltage application wiring at the time of anodic oxidation at the same time. Method. 14. The method of manufacturing a thin film transistor array according to claim 13, wherein in the seventh step, the wiring for voltage application at the time of anodic oxidation is simultaneously removed by processing the conductive thin film. 15. The method according to claim 10, wherein the conductive thin film is formed of a material containing aluminum or tantalum as a main component. 16. A drain electrode of a thin film transistor is connected to each pixel electrode arranged in a matrix, a gate wiring and a source wiring of the thin film transistor are arranged in a lattice between the pixel electrodes, and the gate wiring and a source wiring are provided. A liquid crystal display device in which a liquid crystal is sandwiched between a thin film transistor array substrate in which the gate wiring is located below the source wiring and an opposing substrate provided with a transparent electrode arranged to oppose the pixel electrode in an overlapping portion of A liquid crystal display device, wherein an anodized insulating layer is formed at least in an overlapping portion of the gate wiring of the thin film transistor array substrate with the source wiring. 17. The liquid crystal display device according to claim 16, wherein an interlayer insulating layer is formed between the gate wiring and the source wiring of the thin film transistor array substrate on which the anodic oxide insulating layer is formed. 18. The liquid crystal display device according to claim 16, wherein the gate wiring of the thin film transistor array substrate is made of a material containing aluminum or tantalum as a main component.