JPH0258228A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0258228A JPH0258228A JP20991088A JP20991088A JPH0258228A JP H0258228 A JPH0258228 A JP H0258228A JP 20991088 A JP20991088 A JP 20991088A JP 20991088 A JP20991088 A JP 20991088A JP H0258228 A JPH0258228 A JP H0258228A
- Authority
- JP
- Japan
- Prior art keywords
- alloy layer
- layer
- high melting
- wiring
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000002844 melting Methods 0.000 claims description 10
- 230000008018 melting Effects 0.000 claims description 10
- 150000002736 metal compounds Chemical class 0.000 claims description 5
- 229910001080 W alloy Inorganic materials 0.000 abstract description 8
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 238000002161 passivation Methods 0.000 abstract description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 abstract 4
- 229910000765 intermetallic Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 29
- 229910045601 alloy Inorganic materials 0.000 description 12
- 239000000956 alloy Substances 0.000 description 12
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 229910000676 Si alloy Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特にアルミニラ１１電
横配線を採用した半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit employing aluminum 11-electrode horizontal wiring.
（従来の技術〕
従来の半導体集積回路における電極配線にはＡｆ−３ｉ
合金の単層あるいは、ＡＪ？−３ｔ合金とシリサイドの
積層構造等が採用されていた。(Prior art) Af-3i is used for electrode wiring in conventional semiconductor integrated circuits.
Single layer of alloy or AJ? A laminated structure of -3t alloy and silicide was adopted.
上述した従来の半導体集積回路では、電極配線形成後に
被着されるパッシベーション膜の応力により電極配線の
アルミニウムの一部が移動し、電極配線が断線してしま
うという欠点を有する。The above-described conventional semiconductor integrated circuit has a drawback that a portion of the aluminum of the electrode wiring moves due to the stress of the passivation film deposited after the electrode wiring is formed, resulting in the electrode wiring being disconnected.
さらに、電極配線に電流を流し続けると、電子の流れに
押されアルミニウムが移動する、いわゆるエレクトロマ
イグレーションにより断線したり、あるいは電極配線の
側面ではパッシベーション膜が弱く、パッシベーション
膜を破壊し、アルミニウムの突起が発生し、隣接する配
線と短絡してしまうという欠点を有する。Furthermore, if current continues to flow through the electrode wiring, the aluminum may move due to the flow of electrons, which is called electromigration, which may cause the wire to break, or the passivation film may be weak on the sides of the electrode wiring, destroying the passivation film and causing aluminum to protrude. This has the disadvantage of causing a short circuit with adjacent wiring.
本発明の半導体集積回路は、アルミニウムを主成分とす
る配線の側面に高融点金属あるいは高融点金属化合物の
層を設けたものである。The semiconductor integrated circuit of the present invention is one in which a layer of a high melting point metal or a high melting point metal compound is provided on the side surface of a wiring whose main component is aluminum.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
シリコン酸化膜２で覆われ、所定の位置に開口部が設け
られたシリコン基板１上にスパッタリング法によりＴｉ
−Ｗ合金層３を５０〜２００ｎｍの厚さに、続いてＡｊ
’−３ｉ合金層４を０．５〜２μｍの厚さに連続して形
成する０次に、通常のりソグラフィ技術及びエツチング
技術を用いＴ ｉ −Ｗ合金層３とＡｆｆ−３ｉ合金層
４を所望の電極配線にパターニングする。次にＷＦ６と
Ｈ２ガスを用い、ＣＶＤ法によりＴ ｉ−Ｗ合金層３と
Ａｅ−８ｉ合金層４の表面に泗択的にタングステン層５
を５０〜２００ｎｍの膜厚に形成した後、ＣＦ４ガスを
用いた反応性イオンエッチによりＡｅ−Ｓｉ合金層４上
のタングステン層５をエツチング除去する。この際、エ
ツチングが異方性エツチングのため、Ｔｉ−Ｗ合金層３
とＡｅ−３ｉき金層４の側面にはタングステン層５が残
される。次にパッシベーション膜として、プラズマ窒化
膜６を形成し、電極配線を完成する。Ti is deposited by sputtering on a silicon substrate 1 covered with a silicon oxide film 2 and provided with openings at predetermined positions.
-W alloy layer 3 to a thickness of 50 to 200 nm, followed by Aj
The '-3i alloy layer 4 is continuously formed to a thickness of 0.5 to 2 μm. Next, the Ti-W alloy layer 3 and the Aff-3i alloy layer 4 are formed as desired using normal lamination lithography and etching techniques. Pattern the electrode wiring. Next, using WF6 and H2 gas, a tungsten layer 5 is selectively formed on the surfaces of the Ti-W alloy layer 3 and the Ae-8i alloy layer 4 by the CVD method.
After forming a film with a thickness of 50 to 200 nm, the tungsten layer 5 on the Ae-Si alloy layer 4 is etched away by reactive ion etching using CF4 gas. At this time, since the etching is anisotropic, the Ti-W alloy layer 3
A tungsten layer 5 is left on the side surface of the Ae-3i gold layer 4. Next, a plasma nitride film 6 is formed as a passivation film to complete the electrode wiring.
第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
第１の実施例と同様に、シリコン酸化膜１２で覆われた
シリコン基板１１上にＡｔ７−Ｓｉ合金層１３で第１の
配線を形成する。次に、スパッタリング法によりタング
ステンシリサイド層１４を５０〜２００ｎｍの厚さに被
着した後、反応性イオンエッチ法によりＡ！！−Ｓｉ合
金層１３上のタングステンシリサイド層１４をエツチン
グし、Ａｔ？−３ｉ合金層１３の側面１２のみタングス
テンシリサイド層１４ｆ：残す。次に、眉間絶縁膜とし
て、プラズマ窒化膜１５を形成し、このプラズマ窒化膜
１５を形成し、このプラズマ窒化膜１５の所望の位置に
Ａｅ−３ｉ合金層１３に達する開口部を形成後、再度Ａ
Ｊ７−３ｉ合金層】６で第２の配線を形成する。さらに
、第１の配線と同様に、Ａｆ−３ｉ合金層１６の側面に
のみタングステンシリサイド）Ｖｊ １７を形成し、２
Ｒ配線構造を形成する。As in the first embodiment, a first wiring is formed using an At7-Si alloy layer 13 on a silicon substrate 11 covered with a silicon oxide film 12. Next, after depositing a tungsten silicide layer 14 to a thickness of 50 to 200 nm by sputtering, A! ! - Etching the tungsten silicide layer 14 on the Si alloy layer 13 and etching the At? - Only the side surface 12 of the -3i alloy layer 13 is left with the tungsten silicide layer 14f. Next, a plasma nitride film 15 is formed as an insulating film between the eyebrows, and after forming this plasma nitride film 15 and forming an opening reaching the Ae-3i alloy layer 13 at a desired position of this plasma nitride film 15, A
J7-3i alloy layer] 6 forms the second wiring. Furthermore, similar to the first wiring, tungsten silicide (Vj) 17 is formed only on the side surface of the Af-3i alloy layer 16, and
Form an R wiring structure.
この実施例では、第１の配線と第２の配線の間にアルミ
ニウム以外の金属がないため、接続抵抗は従来のアルミ
ニウム多層配線と同等の値のまま、信頼性が向上できる
という利点がある。In this embodiment, since there is no metal other than aluminum between the first wiring and the second wiring, there is an advantage that reliability can be improved while the connection resistance remains at the same value as the conventional aluminum multilayer wiring.
１ｉ発明の効果〕
以上説明したように、本発明は、アルミニウム合金配線
あるいはアルミニウム合金とシリサイドの積層構造によ
る配線等、アルミニウムを主成分とする配線の側面に、
高融点金属または高融点金属化合物を設けることにより
、応力の大きなパッシベーション膜を形成しても高融点
金属または高融点金属化合物により応力が緩和されアル
ミニウムが断線することは無い。さらにエレクトロマイ
グレーションによりアルミニウムが移動しても、側面に
ある高融点金属あるいは高融点金属化合物のため、アル
ミニウムの突起が発生することはなく、隣接する配線と
短絡する恐れは無いという効果を有する。1i Effects of the Invention] As explained above, the present invention provides the following advantages:
By providing a high melting point metal or a high melting point metal compound, even if a passivation film with large stress is formed, the stress is relaxed by the high melting point metal or high melting point metal compound, and the aluminum will not be disconnected. Furthermore, even if aluminum moves due to electromigration, no protrusions of the aluminum will occur because of the high melting point metal or high melting point metal compound on the side surfaces, and there is no risk of short circuiting with adjacent wiring.
Ｔ ｉ −Ｗ合金層、４・・・ＡＩ！−３ｉ合金層、５
・・・タングステン層、６・・・プラズマ窒化膜、１１
・・・シリコン基板、１２・・・シリコン酸化膜、１３
・・・Ａｆｆ−５ｉ合金層、１４・・・タングステンシ
リサイド層、１５・・・プラズマ窒化膜、１６・・・Ａ
ｌ−９ｉ合金層、１７・・・タングステンシリサイド層
。T i -W alloy layer, 4...AI! -3i alloy layer, 5
... Tungsten layer, 6... Plasma nitride film, 11
...Silicon substrate, 12...Silicon oxide film, 13
...Aff-5i alloy layer, 14...Tungsten silicide layer, 15...Plasma nitride film, 16...A
l-9i alloy layer, 17... tungsten silicide layer.
Claims (1)
たは高融点金属化合物の層が設けられていることを特徴
とする半導体集積回路。A semiconductor integrated circuit characterized in that a layer of a high melting point metal or a high melting point metal compound is provided on the side surface of wiring whose main component is aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20991088A JPH0258228A (en) | 1988-08-23 | 1988-08-23 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20991088A JPH0258228A (en) | 1988-08-23 | 1988-08-23 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0258228A true JPH0258228A (en) | 1990-02-27 |
Family
ID=16580678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20991088A Pending JPH0258228A (en) | 1988-08-23 | 1988-08-23 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0258228A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313536B1 (en) | 1997-04-08 | 2001-11-06 | Nec Corporation | Semicoductor device having a multilayered interconnection structure |
-
1988
- 1988-08-23 JP JP20991088A patent/JPH0258228A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6313536B1 (en) | 1997-04-08 | 2001-11-06 | Nec Corporation | Semicoductor device having a multilayered interconnection structure |
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