JP2720863B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a wiring structure capable of withstanding thermal stress during resin sealing and improving the adhesion between a surface protective film and a sealing resin. The present invention relates to an improved semiconductor integrated circuit device.

[0002]

2. Description of the Related Art When a semiconductor chip is sealed with a resin, a metal wiring layer does not have high adhesion to an interlayer insulating film or a surface protection film (passivation film), and a metal wiring layer is formed only on a base wiring through a through hole. Since the wiring layer is merely fixed, the wiring layer moves due to the thermal shock, causing disconnection or peeling from the insulating film.

Further, in the conventional resin-encapsulated semiconductor integrated circuit device, the adhesion between the surface protective film and the encapsulating resin is not good, and the two have different coefficients of thermal expansion. Thus, a problem has occurred that a gap is formed between the sealing resin and the surface protective film. If a gap is formed below the sealing resin film, moisture accumulates in the gap, causing corrosion of wiring and the like, which significantly reduces the reliability of the semiconductor device.

Several techniques have been proposed to address these problems. The one shown in FIG. 6 is the one proposed by Japanese Patent Application Laid-Open No.
A conductive film 13 is formed on a semiconductor substrate 11 or an insulating film 12 for element isolation, and an interlayer insulating film 1 having a concave portion formed on the surface thereof.
4 are formed. A metal wiring film 15 is formed on interlayer insulating film 14 so as to fill the recess, and a wiring protection film 16 is formed thereon. According to this configuration, since the metal wiring film 15 is mechanically and strongly coupled to the interlayer insulating film 14, the movement is suppressed and an accident such as disconnection is avoided.

FIG. 7 is a cross-sectional view of a semiconductor integrated circuit device (hereinafter referred to as a second conventional example) proposed in Japanese Patent Application Laid-Open No. Sho 62-150859, in which an inorganic passivation film is formed on a semiconductor substrate 21. A buffer coating film 24 made of polyimide or the like and having a concave portion 25 on the surface is formed thereon. In addition, the passivation film 23 and the buffer coating film 24 include
An opening for exposing the surface of the bonding pad 22 is provided. According to this configuration, the coating film 2
4 and the sealing resin (not shown) have high mechanical adhesion, so that a gap is not generated between them due to thermal shock.

[0006]

In the structure of the first conventional example described above, there is no improvement in the adhesion between the sealing resin and the wiring protective film, and the sealing resin is not affected when a thermal shock is applied. There is a problem that a gap is likely to be formed between the semiconductor device and the wiring protection film, thereby impairing the moisture resistance of the semiconductor device.
Further, in this conventional example, since the interlayer insulating film is partially thinned, there is a drawback that an electrical withstand voltage failure between wiring layers is likely to occur due to manufacturing variations in the formation process. There is also a drawback that electromigration is likely to occur because the thickness of the metal wiring film is insufficient on the film protrusion.

In the structure of the second conventional example described above, although the adhesion between the sealing resin and the surface protective film is maintained, no measure is taken against the displacement of the wiring layer, and the resin sealing is not performed. The wiring layer may be displaced by stress due to a thermal shock or the like applied at the time of stoppage, which may cause disconnection or a short circuit accident.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a wiring which occurs due to a thermal shock applied during resin sealing and an internal stress due to a subsequent temperature cycle. To prevent the occurrence of disconnection and short-circuit by preventing the displacement, and to enhance the adhesion between the sealing resin and the surface protective film to prevent the occurrence of the gap therebetween. is there.

[0009]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention has a wiring layer formed on a semiconductor substrate via an insulating film, and a surface protective film covers the wiring. And a sealing resin film for sealing the semiconductor chip, wherein a discontinuous trapezoidal conductor is formed on the wiring layer, and a surface of the surface protection film is formed on the surface of the surface protection film. Is characterized in that the pattern of the trapezoidal conductor is substantially reproduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a semiconductor integrated circuit device for explaining an embodiment of the present invention. As shown in FIG. 1, the semiconductor chip to be sealed with a resin has an Al wiring layer 3 formed on a semiconductor substrate 1 via an insulating film 2, a trapezoidal conductor 4 formed thereon, and a surface. The surface is covered with the protective film 5. The trapezoidal conductor 4 is formed so as to straddle the Al wiring layer 3, and its end portion extends over the insulating film 2. The trapezoidal conductor 4 can also be formed by a base conductor layer and a columnar conductive layer. Al
The surface protective film 5 formed on the wiring layer 3 and the trapezoidal conductor 4 is formed with a film thickness and under conditions that reproduce the pattern formed by the trapezoidal conductor 4.

The semiconductor chip thus formed is mounted on the island of the lead frame 6, and after the connection by the bonding wire 7 is completed, the semiconductor chip is sealed with the sealing resin 8 by using a transfer molding method. In the semiconductor integrated circuit device thus configured, the surface protection film 5
And the sealing resin 8 are in mesh with each other to enhance the mechanical coupling, so that a gap is formed between the two even after a thermal cycle or the like or even when there is a difference in the coefficient of thermal expansion between the two. Is suppressed. Further, since the Al wiring layer 3 is fixed to the insulating film 2 by the trapezoidal conductor 4, and the trapezoidal conductor 4 is mechanically and strongly bonded to the surface protective film 5, the Al wiring layer 3 can be used during resin sealing or thermal cycling. In such a case, it is possible to suppress the occurrence of displacement of the wiring layer due to a thermal shock, and it is possible to drastically reduce accidents such as disconnection and short circuit.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 2A is a plan view for explaining a first embodiment of the present invention, and FIG. 2B and FIG.
Is a cross-sectional view taken along line AA and line BB. The semiconductor chip used in the semiconductor integrated circuit device of the present invention is:
A wiring layer made of a semiconductor substrate (silicon substrate) 1 and an Al film formed on an insulating film 2 of the semiconductor substrate 1 or an alloy film containing Al as a main component, for example, Si, Cu, etc. An aluminum wiring layer 3), a trapezoidal conductor 4 formed by covering the side surface of the aluminum wiring layer 3 and surface-adhering on the insulating film 2, and discontinuous on the aluminum wiring layer 3. Wiring layer 3 including this trapezoidal conductor 4
And a surface protective film 5 covering the whole.

In forming the trapezoidal conductor 4, for example, Cu may be deposited by an electron beam evaporation method, and the patterning can be performed by an evaporation method using a mask or a photolithography technique. .
Alternatively, patterning may be performed using a so-called lift-off method. In this case, it is desirable that the photoresist film for patterning is thickly applied using a photoresist having high viscosity.

The trapezoidal conductor may include a high melting point metal compound, such as Mo, N
The same effect can be obtained by using a single layer of i, Cr, Ti, Pt, Au, W, TiN, TiW, or the like, or a laminate including Cu and a combination thereof. Where Mo, N
Each metal film of i, Cr, Ti, and Au is formed by an electron beam evaporation method, each metal film of Ti, Pt, and TiW is formed by a normal sputtering method using each metal as a target.
It can be formed by a sputtering method using an i-plate as a target and introducing N ₂ gas. The Au layer may be plated,
The W layer can be deposited by a CVD method using a mixed gas of WF ₆ and H ₂ as a reaction gas.

When a trapezoidal conductor having a laminated structure is formed on an Al wiring layer, a metal Al deposited on an upper layer is formed.
Ti, Mo, Cr, TiN, or the like can be used as the barrier metal in consideration of improvement in adhesion to a metal or an insulating film, prevention of thermal diffusion, and the like. In this case, the reliability of the wiring structure of the semiconductor device can be further improved as compared with the case where only a single metal layer is attached.

[Second Embodiment] FIG. 3A is a plan view for explaining a second embodiment of the present invention.
(B) is a cross-sectional view taken along line CC. As shown in FIG. 3, in the semiconductor chip used in the semiconductor integrated circuit device of this embodiment, the trapezoidal conductor 4 is composed of a Ti film 4a and a TiN film that continuously cover the Al wiring layer 3 including the side surfaces. 4
b, and a Cu layer 4c discontinuously formed in a prismatic shape on the underlying conductive layer.

Next, the manufacturing method of this embodiment will be described with reference to FIGS. 4A to 4C which are sectional views showing the manufacturing steps of the semiconductor chip shown in FIG. The insulating film 2 and the Al wiring layer 3 are formed on the semiconductor substrate
Are sequentially formed, a photoresist film 9 is formed by photolithography in a pattern opposite to the underlying conductive layer to be formed on the insulating film 2. Subsequently, a Ti film 4a as a barrier metal and a TiN film 4b are deposited by sputtering (FIG. 4A). Here, a Ti film thickness of 〜１０10
The thickness of TiN is set to about 0.2 to 3 μm. The photoresist film is formed to have a thickness of 2 to 3 μm by adjusting its viscosity so that the side wall of the photoresist film is not completely covered with the metal film. The TiN film can be formed using Ti as a sputtering target and a mixed gas of argon and nitrogen as a discharge gas. The film can be formed efficiently.

Next, as shown in FIG. 4B, when the photoresist film 9 is removed by ashing or a photoresist stripper, the Ti films 4a, T on the photoresist film are simultaneously removed.
It is possible to lift off the laminated film of the iN film 4b,
The laminated film of the Ti film 4a and the TiN film 4b can be left only on the surface and side surfaces of the wiring layer 3 and on the insulating film near both side edges. According to this embodiment, the entire Al wiring layer 3 is T
Since the i film and the TiN cover, the electromigration resistance can be improved.

Next, as shown in FIG. 4C, a prismatic Cu layer 4c is formed on the underlying laminated films (4a and 4b) located above the Al wiring layer 3. Thus, the trapezoidal conductor 4 is composed of the laminated base layers (4a and 4b) and the upper metal layer (4
c) is formed as having a divided structure. The Cu layer 4c may be formed by electron beam evaporation of Cu and photolithography, or may be formed by an evaporation method using a mask or a lift-off method. After the trapezoidal conductor 4 is formed, if the entire Al wiring layer 3 including the trapezoidal conductor 4 is covered with the surface protection film 5, the structure becomes the same as that of the first embodiment.

In the above embodiment, a laminated film of a Ti film and a TiN film was described as a lower film of the trapezoidal conductor. However, for example, a single layer of a TiN film or a laminated film of a Ti film and a Pt film may be used. Similar effects can be obtained. Further, although the metal as the upper layer film has been described as Cu, Au or W may be used. The combination of these metals and the selection of the forming method are the same as those in the first embodiment.

[Third Embodiment] FIG. 5A is a plan view of a semiconductor chip used in a third embodiment of the present invention, and FIG. 5B is a cross section taken along the line DD. FIG. The present embodiment is different from the second embodiment shown in FIG.
The point is that the laminated underlayer composed of the film 4a and the TiN film 4b is not formed continuously, and that the trapezoidal conductor 4 is formed in a zigzag manner in the vertical direction of FIG. By forming the trapezoidal conductor in a zigzag pattern, the adhesion between the surface protective film and the sealing resin can be further improved. In addition,
The manufacturing method of this embodiment is the same as that of the second embodiment.

[0022]

Since the semiconductor integrated circuit device according to the present invention is configured as described above, the following effects can be obtained. Since a large number of trapezoidal conductors composed of metal layers are discontinuously formed on the wiring layer and formed,
The surface protective film covering the entire wiring layer including the trapezoidal conductor has an uneven surface on its surface while keeping its thickness uniform. Thereby, the adhesiveness between the sealing resin layer and the surface protective film can be improved, and the adhesive strength can be increased.
Therefore, even if a heat shock or a heat cycle is applied, the sealing resin layer does not peel off, and the long-term reliability of the semiconductor integrated circuit device can be improved by preventing a decrease in moisture resistance due to formation of a gap. it can.

Also, by forming the trapezoidal conductor,
The adhesion between the underlying insulating film of the wiring layer including the trapezoidal conductor and the upper surface protective film can be improved. For this reason, it is possible to prevent the wiring layer from being displaced due to a thermal shock or the like received at the time of resin sealing, and it is possible to avoid occurrence of a disconnection or a short circuit accident of the wiring layer. Further, since the trapezoidal conductor is present on the wiring layer so as to cover the wiring layer, the thickness of the wiring layer is not reduced, and the wiring layer is not provided with a current density required for circuit design. Can be prevented from being degraded.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 2 is a plan view and a cross-sectional view for explaining a first embodiment of the present invention.

FIG. 3 is a plan view and a sectional view for explaining a second embodiment of the present invention.

FIG. 4 is a process order sectional view for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 5 is a plan view and a sectional view for explaining a third embodiment of the present invention.

FIG. 6 is a sectional view of a first conventional example.

FIG. 7 is a sectional view of a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11, 21 Semiconductor substrate 2 Insulating film 3 Al wiring layer 4 Trapezoidal conductor 4a Ti film 4b TiN film 4c Cu layer 5 Surface protection film 6 Lead frame 7 Bonding wire 8 Sealing resin 9 Photoresist film 12 Element separation Insulating film 13 Conductive film 14 Interlayer insulating film 15 Metal wiring film 16 Wiring protective film 22 Bonding pad 23 Passivation film 24 Buffer coating film 25 Depression

Claims (6)

(57) [Claims] 1. A semiconductor chip having a wiring layer formed on a semiconductor substrate with an insulating film interposed therebetween and a surface protective film covering the wiring, and a sealing resin film for sealing the semiconductor chip. A semiconductor integrated circuit device, wherein a discontinuous trapezoidal conductor is formed on the wiring layer, and a pattern of the trapezoidal conductor is substantially reproduced on a surface of the surface protection film. Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said trapezoidal conductor comprises a base conductor layer and a columnar conductive layer formed thereon. 3. The semiconductor integrated circuit device according to claim 1, wherein the trapezoidal conductor covers a side surface of the wiring layer and partially covers a surface of the insulating film. 4. The method according to claim 1, wherein the trapezoidal conductor or the columnar conductive layer is made of Cu, W, Mo, Ni, Cr, Ti, Pt, Au,
3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed of a plurality of conductive films formed of a single layer of TiN or TiW or a combination thereof. 5. The method according to claim 1, wherein the underlying conductor layer is made of W, Mo, Ni,
3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is formed of a single layer made of Cr, Ti, TiN, and TiW or a plurality of conductive films made of a combination thereof. 6. The semiconductor integrated circuit device according to claim 2, wherein said base conductor layer continuously covers a surface and a side surface of said wiring layer.