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JPH0233929A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0233929A
JPH0233929A JP63184103A JP18410388A JPH0233929A JP H0233929 A JPH0233929 A JP H0233929A JP 63184103 A JP63184103 A JP 63184103A JP 18410388 A JP18410388 A JP 18410388A JP H0233929 A JPH0233929 A JP H0233929A
Authority
JP
Japan
Prior art keywords
metal bump
metal
bump layer
layer
soft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63184103A
Other languages
Japanese (ja)
Inventor
Yasuhiko Iwamoto
岩本 泰彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63184103A priority Critical patent/JPH0233929A/en
Publication of JPH0233929A publication Critical patent/JPH0233929A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To alleviate load at the time of connecting an outer lead and ease the influence on a substrate by surrounding a second metal bump layer composed of hard metallic material by the use of a first and a third bump layers composed of a soft metallic material whose surface is difficultly oxidized. CONSTITUTION:An insulating film 12 on a semiconductor substrate 11 is opened on an Al electrode 13 to constitute a pad electrode and a first and a second metal films 14, 15 such as Ti/Cu or Ti/Pt are formed so as to cover the opening. Further a first comparatively soft metal bump layer 16 such as gold is formed on these metal films 14, 15 and a second comparatively hard metal bump layer 17 such as copper in the narrow range thereon. Further a third soft metal bump layer 18 such as gold is formed so as to cover the second metal bump layer 17 thereon and the device is constituted so that the second metal bump layer 17 can be surrounded by the first and the third metal bump layers 16, 18.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に金属バンプを有する半
導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having metal bumps.

〔従来の技術〕[Conventional technology]

従来、外部接続用電極として半導体装置に形成される金
属バンプは、第3図に示すように、銅等の金属バンプ3
6の表面に外部リード線との密着性を良くするための金
等の金属層37を形成した構造となっている。即ち、第
3図の構造の金属バンプは、半導体基板31上に形成し
た絶縁膜32をアルミニウム電極33上で開口してパッ
ド電極を構成し、この上に第1.第2の各金属膜34゜
35を形成する。そして、この上にフォトレジスト等を
付着した上で、アルミニウム電極33よりも大きな開口
を開設し、ここにメツキ法により銅等の金属を選択的に
形成して金属バンプ36を形成する。また、この金属バ
ンプ36上に金等の金属層37を形成する。しかる上で
、フォトレジストを除去し、かつ金属バンプ36をマス
クにして第1.第2の金属膜34.35をエツチングす
ることにより完成される。
Conventionally, metal bumps formed on semiconductor devices as external connection electrodes are metal bumps 3 made of copper or the like, as shown in FIG.
It has a structure in which a metal layer 37 such as gold is formed on the surface of the wire 6 to improve adhesion with external lead wires. That is, in the metal bump having the structure shown in FIG. 3, an insulating film 32 formed on a semiconductor substrate 31 is opened on an aluminum electrode 33 to form a pad electrode, and a first pad electrode is formed on the aluminum electrode 33. Second metal films 34 and 35 are formed. Then, a photoresist or the like is adhered thereon, and an opening larger than the aluminum electrode 33 is opened, and a metal such as copper is selectively formed therein by a plating method to form a metal bump 36. Further, a metal layer 37 of gold or the like is formed on the metal bump 36. Then, the photoresist is removed, and the first. This is completed by etching the second metal films 34 and 35.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の金属バンプは、殆どが銅等のように比較
的硬い金属材料で構成されるため、外部リードの接続に
伴う圧力荷重がそのまま半導体基板31に伝達される。
Since most of the conventional metal bumps described above are made of a relatively hard metal material such as copper, the pressure load associated with the connection of the external leads is directly transmitted to the semiconductor substrate 31.

このため、半導体基板31にクラックが発生し、或いは
下層に形成した素子の特性劣化を生じる原因となってい
る。この場合、金属バンプを単に軟らかい金属で形成す
ると、外部リードの接続時に金属バンプが潰れて横に広
がり、隣接するリード等と短絡するおそれがあり、電極
の高密度化の障害となる。
This causes cracks to occur in the semiconductor substrate 31 or deterioration of characteristics of elements formed in the underlying layer. In this case, if the metal bumps are simply made of a soft metal, there is a risk that the metal bumps will collapse and spread laterally when external leads are connected, resulting in a short circuit with adjacent leads, etc., which will impede high density electrodes.

また、従来の金属バンプ36は、上面は金等の金属層3
7で被覆されているが、側面において素材が露呈されて
おり、この側面が酸化されて表面の変質が生じ易い。こ
のため、外部リードとの接続抵抗が増大し、或いは接続
不良が生じて半導体装置の信頼性が低下されるという問
題がある。
Further, the conventional metal bump 36 has a metal layer 3 such as gold on the top surface.
7, but the material is exposed on the side surfaces, and this side surface is easily oxidized and surface deterioration occurs. For this reason, there is a problem that the connection resistance with the external lead increases or a connection failure occurs, resulting in a decrease in the reliability of the semiconductor device.

本発明は酸化等による表面の変質を防止し、かつ外部リ
ードとの接続時の圧力荷重を低減して半導体装置へのダ
メージを防止して、信頼性の向上を図った半導体装置を
提供することを目的としている。
An object of the present invention is to provide a semiconductor device which is improved in reliability by preventing surface deterioration due to oxidation, etc., and reducing pressure load during connection with external leads to prevent damage to the semiconductor device. It is an object.

〔課題を解決するための手段〕 本発明の半導体装置は、半導体基板上に設けたパッド電
極上に軟質で表面酸化され難い金属材料で形成した第1
金属バンプ層と、この第1金属バンプ層上に硬質の金属
材料で形成した第2金属バンプ層と、この第2金属バン
プ層を覆うように軟質で表面酸化され難い金属材料で形
成した第3金属バンプ層とで構成した金属バンプを有し
ている。
[Means for Solving the Problems] The semiconductor device of the present invention provides a first pad electrode formed on a pad electrode provided on a semiconductor substrate using a metal material that is soft and whose surface is not easily oxidized.
a second metal bump layer made of a hard metal material on the first metal bump layer; and a third metal bump layer made of a soft metal material whose surface is not easily oxidized so as to cover the second metal bump layer. It has a metal bump composed of a metal bump layer.

〔作用〕[Effect]

」二連した構成では、第1及び第3金属バンプ層が軟質
かつ表面酸化され難いために、外部リードの接続時にお
ける荷重をこれら金属バンプ層で緩和して半導体基板へ
の影響を緩和し、かつ一方では表面酸化による接続不良
を防止する。また、硬質の第2金属バンプ層により、金
属バンプの潰れを最小限に抑え、電極の高密度化を実現
する。
In the double-connected configuration, the first and third metal bump layers are soft and difficult to oxidize, so the load when connecting external leads is alleviated by these metal bump layers to reduce the impact on the semiconductor substrate. On the other hand, it also prevents connection failures due to surface oxidation. In addition, the hard second metal bump layer minimizes crushing of the metal bumps and achieves high density electrodes.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の半導体装置に適用される金属バンプの
一実施例の断面図である。図示のように、半導体基板1
1上の絶縁膜12をアルミニウム電極13上で開口して
パッド電極を構成し、この開口を覆うようにT i /
 Cu又はT i / P tのような第1.第2の金
属膜14.15を形成している。
FIG. 1 is a sectional view of one embodiment of a metal bump applied to a semiconductor device of the present invention. As shown, a semiconductor substrate 1
A pad electrode is formed by opening the insulating film 12 on the aluminum electrode 13, and T i /
1. such as Cu or Ti/Pt. A second metal film 14.15 is formed.

更に、これら金属膜14.15の上に金等のような比較
的軟らかい第1金属バンプ層16を形成し、この上の狭
い領域に銅等のような比較的硬い第2金属バンプ117
を形成する。更に、この上に第2金属バンプ層17を覆
うように、再度金等のような軟らかい第3金属バンプ層
18を形成し、この第1.第3の金属バンプ層16.1
8で第2金属バンプ層17を包囲するように構成してい
る。
Furthermore, a relatively soft first metal bump layer 16 made of gold or the like is formed on these metal films 14.15, and a relatively hard second metal bump layer 117 made of copper or the like is formed in a narrow area on top of this layer 16.
form. Further, a soft third metal bump layer 18 made of gold or the like is again formed thereon so as to cover the second metal bump layer 17, and then the first metal bump layer 18 is formed again. Third metal bump layer 16.1
8 surrounds the second metal bump layer 17.

第2図(a)乃至第2図(g)は、第1・図の構造の製
造方法を工程順に示す断面図である。
FIGS. 2(a) to 2(g) are cross-sectional views showing the method for manufacturing the structure shown in FIG. 1 in order of steps.

先ず、第2図(a)のように、図外の半導体素子を形成
した半導体基板11上の全面にアルミニウム層を薫着法
又はスパッタ法により1μm程度形成し、フォトレジス
トを利用したフォトリソグラフィ技術により選択エツチ
ングしてアルミニウム電極13を形成する。この上にC
VD酸化膜やCVD窒化膜等の絶縁膜12を形成し、か
つフォトリソグラフィ技術を用いてこの絶縁膜12を選
択エツチングすることにより、前記アルミニウム電極1
3上の電極を構成する領域を開口し、パッド電極を構成
する。
First, as shown in FIG. 2(a), an aluminum layer of about 1 μm is formed on the entire surface of the semiconductor substrate 11 on which semiconductor elements (not shown) are formed by a smoke deposition method or a sputtering method, and then a photolithography technique using a photoresist is applied. The aluminum electrode 13 is formed by selective etching. C on top of this
The aluminum electrode 1 is formed by forming an insulating film 12 such as a VD oxide film or a CVD nitride film, and selectively etching this insulating film 12 using photolithography technology.
A region constituting an electrode on 3 is opened to constitute a pad electrode.

次いで、第2図(b)のように、スパッタ法により全面
にT i / Cu又はT i / P を等の第1゜
第2の金属!14.15を夫々10008程度の厚さに
形成する。この上に、ネガ型の第1のフォトレジスト2
0を付着形成し、前記絶縁膜12の開口よりも多少大き
い開口窓を開設する。
Next, as shown in FIG. 2(b), the first and second metals, such as Ti/Cu or Ti/P, are deposited on the entire surface by sputtering. 14 and 15 are each formed to a thickness of about 10008. On top of this, a negative type first photoresist 2 is applied.
0 is deposited and an aperture window somewhat larger than the aperture of the insulating film 12 is formed.

次に、第2図(c)のように、前記第1のフォトレジス
ト20をマスクにしたメツキ法により、このフォトレジ
スト20に等しいか或いは若干薄い厚さ、例えば4〜5
μmの厚さに金等のように比較的軟らかい金属材料から
なる第1金属バンプ層16を形成する。
Next, as shown in FIG. 2(c), by a plating method using the first photoresist 20 as a mask, the thickness of the photoresist 20 is equal to or slightly thinner, for example, 4 to 5.
A first metal bump layer 16 made of a relatively soft metal material such as gold is formed to a thickness of μm.

次いで、第2図(d)のように、前記第1のフォトレジ
スト20をそのまま残し、この上にポジ型の第2のフォ
トレジスト21を形成し、ここに第1金属バンプ層16
よりも小さい開口窓を開設する。
Next, as shown in FIG. 2(d), the first photoresist 20 is left as it is, a positive type second photoresist 21 is formed thereon, and the first metal bump layer 16 is formed thereon.
Open a window with a smaller opening.

続いて、第2図(e)のように、前記第2のフオドレジ
スト21をマスクにしたメツキ法により・第1金属バン
プ層16上に銅等のように比較的硬い金属材料からなる
第2金属バンプN17を形成する。その後、第2図(f
)のように、第2のフォトレジスト21を感光させ、現
像除去させる。
Subsequently, as shown in FIG. 2(e), a second metal made of a relatively hard metal material such as copper is deposited on the first metal bump layer 16 by a plating method using the second photoresist 21 as a mask. A bump N17 is formed. After that, Fig. 2 (f
), the second photoresist 21 is exposed, developed and removed.

しかる後、前記第1のフォトレジスト20を再度マスク
に用いたメツキ法により、前記第1金属バンプ層16及
び第2金属バンプ層17上に金等の比較的軟らかい金属
材料を厚さ4〜5μm形成し、第3金属バンプ層18を
形成する。この後、第1のフォトレジスト20を除去し
、かつ第3金属バンプJilBをマスクにして、第1及
び第2金属膜14.15をエツチング除去することによ
り、第1図の構造が完成される。なお、これら金属膜1
4.15のエツチングでは、T i / Cuの場合に
は専用のエツチング液で容易にエツチングを行うことが
でき、T i / P tの場合にはイオンミリング法
等の強い方向性を有するエツチング法を利用する。
Thereafter, a relatively soft metal material such as gold is deposited on the first metal bump layer 16 and the second metal bump layer 17 to a thickness of 4 to 5 μm using the first photoresist 20 as a mask again. A third metal bump layer 18 is formed. Thereafter, the first photoresist 20 is removed, and the first and second metal films 14 and 15 are etched away using the third metal bump JilB as a mask, thereby completing the structure shown in FIG. . Note that these metal films 1
For etching in 4.15, Ti/Cu can be easily etched with a special etching solution, while Ti/Pt can be etched using a highly directional etching method such as ion milling. Use.

したがって、この構成の金属バンプでは、比較的硬質の
第2金属バンプ層17を、比較的軟質の第1及び第3の
金属バンプ層16.18で包み込んでいるので、外部リ
ードとの接続時における圧力荷重によって第1及び第3
の金属バンプ層16゜18が潰れてこの圧力荷重を吸収
するので、半導体基板11への荷重の印加を緩和し、ク
ラックや素子欠陥の発生を防止する。一方、中心部に存
在する硬質の第2金属バンプ層17により、金属バンプ
の潰れを最小限に抑えることができ、電極の高密度化を
維持させる。
Therefore, in the metal bump having this configuration, since the relatively hard second metal bump layer 17 is surrounded by the relatively soft first and third metal bump layers 16 and 18, when connecting to the external lead, 1st and 3rd by pressure load
The metal bump layers 16 and 18 are crushed and absorb this pressure load, thereby alleviating the load applied to the semiconductor substrate 11 and preventing the occurrence of cracks and device defects. On the other hand, the hard second metal bump layer 17 present in the center can minimize crushing of the metal bumps and maintain high density of the electrodes.

また、この構成の金属バンプは、酸化され難い金からな
る第1及び第3金属バンプ層16.18で、表面酸化さ
れ易い銅からなる第2金属バンプ層17を包囲している
ので、金属バンプの表面変質を防止でき、外部リードと
の接触不良を防止でき、接続の信頼性を向上する。
Furthermore, in the metal bump having this configuration, the first and third metal bump layers 16 and 18 made of gold, which is difficult to oxidize, surround the second metal bump layer 17 made of copper, which is easily oxidized on the surface. This prevents surface deterioration, prevents poor contact with external leads, and improves connection reliability.

なお、前記実施例では第1金属バンプ層16と第3金属
バンプ層18を夫々金で構成しているが、異なる材料で
あってもよい。ただし、これらの金属材料はいずれも軟
質で表面酸化され難い金属で構成することが肝要である
Note that in the embodiment described above, the first metal bump layer 16 and the third metal bump layer 18 are each made of gold, but they may be made of different materials. However, it is important that these metal materials are soft and resistant to surface oxidation.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、軟質で表面酸化され難い
金属材料からなる第1及び第3金属バンプ層で、硬質の
金属材料からなる第2金属バンプ層を包囲した構成とし
ているので、第1及び第3金属バンプ層により外部リー
ドの接続時における荷重を緩和して半導体基板への影響
を緩和し、かつ一方では表面酸化による接続不良を防止
することができる。また、硬質の第2金属バンプ層によ
り、金属バンプの潰れを最小限に抑え、電極の高密度化
を実現することができる。
As explained above, the present invention has a structure in which the second metal bump layer made of a hard metal material is surrounded by the first and third metal bump layers made of a metal material that is soft and whose surface is not easily oxidized. The third metal bump layer can reduce the load when connecting the external leads and reduce the influence on the semiconductor substrate, while also preventing connection failures due to surface oxidation. Moreover, the hard second metal bump layer can minimize crushing of the metal bumps and achieve high density electrodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体装置の金属バンプの断面図、第
2図(a)乃至第2図(g)は第1図の構造を製造する
方法を工程順に示す断面図、第3図は従来の半導体装置
の金属バンプの断面図である。 11・・・半導体基板、12・・・絶縁膜、13・・・
アルミニウム電極、14・・・第1金属膜、15・・・
第2金属膜、16・・・第1金属バンプ層、17・・・
第2金属バンプ層、18・・・第3金属バンプ層、20
・・・第1フオトレジスト、21・・・第2フオトレジ
スト、31・・・半導体基板、32・・・絶縁膜、33
・・・アルミニウム電極、34・・・第1金属膜、35
・・・第2金属膜、36・・・金属バンプ、37・・・
金属層。 第 図 第3 図 第 図 第2 図
FIG. 1 is a cross-sectional view of a metal bump of a semiconductor device of the present invention, FIGS. 2(a) to 2(g) are cross-sectional views showing the method of manufacturing the structure of FIG. 1 in order of steps, and FIG. FIG. 2 is a cross-sectional view of a metal bump of a conventional semiconductor device. 11... Semiconductor substrate, 12... Insulating film, 13...
Aluminum electrode, 14... first metal film, 15...
Second metal film, 16... First metal bump layer, 17...
Second metal bump layer, 18...Third metal bump layer, 20
... first photoresist, 21 ... second photoresist, 31 ... semiconductor substrate, 32 ... insulating film, 33
... Aluminum electrode, 34 ... First metal film, 35
...Second metal film, 36...Metal bump, 37...
metal layer. Figure 3 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板上に設けたパッド電極上に形成した軟質
でかつ表面酸化され難い金属材料からなる第1金属バン
プ層と、この第1金属バンプ層上に形成した硬質の金属
材料からなる第2金属バンプ層と、この第2金属バンプ
層を覆うように前記第1金属バンプ層上に形成した軟質
でかつ表面酸化され難い金属材料からなる第3金属バン
プ層とで構成した金属バンプを有することを特徴とする
半導体装置。
1. A first metal bump layer made of a soft metal material whose surface is not easily oxidized and formed on a pad electrode provided on a semiconductor substrate, and a second metal bump layer made of a hard metal material formed on this first metal bump layer. It has a metal bump composed of a metal bump layer and a third metal bump layer formed on the first metal bump layer so as to cover the second metal bump layer and made of a metal material that is soft and whose surface is not easily oxidized. A semiconductor device characterized by:
JP63184103A 1988-07-23 1988-07-23 Semiconductor device Pending JPH0233929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63184103A JPH0233929A (en) 1988-07-23 1988-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63184103A JPH0233929A (en) 1988-07-23 1988-07-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0233929A true JPH0233929A (en) 1990-02-05

Family

ID=16147446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63184103A Pending JPH0233929A (en) 1988-07-23 1988-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0233929A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459493A3 (en) * 1990-06-01 1994-02-23 Toshiba Kk
US5293071A (en) * 1992-01-27 1994-03-08 Gennum Corporation Bump structure for bonding to a semi-conductor device
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
US6483190B1 (en) 1999-10-20 2002-11-19 Fujitsu Limited Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459493A3 (en) * 1990-06-01 1994-02-23 Toshiba Kk
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
US5654584A (en) * 1990-06-01 1997-08-05 Kabushiki Kaisha Toshiba Semiconductor device having tape automated bonding leads
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