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JPH0257628U - - Google Patents

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Publication number
JPH0257628U
JPH0257628U JP13622288U JP13622288U JPH0257628U JP H0257628 U JPH0257628 U JP H0257628U JP 13622288 U JP13622288 U JP 13622288U JP 13622288 U JP13622288 U JP 13622288U JP H0257628 U JPH0257628 U JP H0257628U
Authority
JP
Japan
Prior art keywords
output terminal
signal
switching
count buffer
buffer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13622288U
Other languages
Japanese (ja)
Other versions
JPH0537548Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13622288U priority Critical patent/JPH0537548Y2/ja
Publication of JPH0257628U publication Critical patent/JPH0257628U/ja
Application granted granted Critical
Publication of JPH0537548Y2 publication Critical patent/JPH0537548Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の一実施例を示す回路図、第
2図は従来のカウントバツフア回路を示す回路図
、及び第3図は本考案の具体回路例を示す回路図
である。 11……切換回路、12……コンデンサ、13
……出力ピン、16……停止回路、17……マイ
クロコンピユータ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional count buffer circuit, and FIG. 3 is a circuit diagram showing a specific example of the circuit of the present invention. 11...Switching circuit, 12...Capacitor, 13
...Output pin, 16...Stop circuit, 17...Microcomputer.

Claims (1)

【実用新案登録請求の範囲】 (1) 異なるバンドのIF信号が切換出力される
出力端子を有し、前記出力端子に得られるIF信
号をマイクロコンピユータにカウント用の信号と
して印加するとともに、前記マイクロコンピユー
タから発生する制御信号が前記出力端子に印加さ
れるカウントバツフア回路であつて、 前記異なるバンドのIF信号を切換出力する切
換回路と、 該切換回路の出力端と前記出力端子との間に接
続されるコンデンサと、 前記出力端子に印加される制御信号に応じて前
記切換回路の動作を停止させる停止回路と を備えることを特徴とするカウントバツフア回
路。 (2) 前記切換回路は、エミツタが共通に定電流
源に接続された第1及び第2トランジスタから成
る第1差動増幅部と、エミツタが共通に前記定電
流源に接続された第3及び第4トランジスタから
成る第2差動増幅部とを備え、前記第1及び第2
差動増幅部を切換制御することにより、前記第1
及び第2差動増幅部の共通出力端子に第1又は第
2バンドのIF信号を発生することを特徴とする
請求項第1項記載のカウントバツフア回路。 (3) 前記停止回路は、前記制御信号に応じてオ
フする制御トランジスタを備え、前記制御トラン
ジスタがオフになるとき、前記定電流源を動作さ
せ、前記出力端子にIF信号を発生することを特
徴とする請求項第2項記載のカウントバツフア回
路。
[Claims for Utility Model Registration] (1) It has an output terminal to which IF signals of different bands are switched and output, and the IF signal obtained at the output terminal is applied to the microcomputer as a counting signal, and the microcomputer A count buffer circuit to which a control signal generated from a computer is applied to the output terminal, a switching circuit for switching and outputting IF signals of different bands, and between the output terminal of the switching circuit and the output terminal. A count buffer circuit comprising: a capacitor connected to the output terminal; and a stop circuit configured to stop the operation of the switching circuit according to a control signal applied to the output terminal. (2) The switching circuit includes a first differential amplifier section including first and second transistors whose emitters are commonly connected to the constant current source, and third and second transistors whose emitters are commonly connected to the constant current source. a second differential amplification section consisting of a fourth transistor;
By controlling the switching of the differential amplification section, the first
2. The count buffer circuit according to claim 1, wherein the IF signal of the first or second band is generated at the common output terminal of the differential amplifier and the second differential amplifier. (3) The stop circuit includes a control transistor that turns off in response to the control signal, and when the control transistor turns off, operates the constant current source and generates an IF signal at the output terminal. 3. The count buffer circuit according to claim 2.
JP13622288U 1988-10-19 1988-10-19 Expired - Lifetime JPH0537548Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13622288U JPH0537548Y2 (en) 1988-10-19 1988-10-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13622288U JPH0537548Y2 (en) 1988-10-19 1988-10-19

Publications (2)

Publication Number Publication Date
JPH0257628U true JPH0257628U (en) 1990-04-25
JPH0537548Y2 JPH0537548Y2 (en) 1993-09-22

Family

ID=31396528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13622288U Expired - Lifetime JPH0537548Y2 (en) 1988-10-19 1988-10-19

Country Status (1)

Country Link
JP (1) JPH0537548Y2 (en)

Also Published As

Publication number Publication date
JPH0537548Y2 (en) 1993-09-22

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