JPS63171021U - - Google Patents
Info
- Publication number
- JPS63171021U JPS63171021U JP6487387U JP6487387U JPS63171021U JP S63171021 U JPS63171021 U JP S63171021U JP 6487387 U JP6487387 U JP 6487387U JP 6487387 U JP6487387 U JP 6487387U JP S63171021 U JPS63171021 U JP S63171021U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- general
- operational amplifier
- inverting input
- terminal connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案の一実施例による自動オフセツ
ト調整付バツフア回路を示す図、第２図はその第
２実施例による同様なバツフア回路を示す図であ
る。第３図は本考案の第３実施例による自動オフ
セツト調整付非反転増幅回路を示す図、第４図は
その第４実施例による同様な反転増幅回路を示す
図である。第５図及び第６図は従来のオフセツト
調整付増幅回路を示す図である。
１０，２８，３４，４６……汎用オペアンプ、
１２，２２，３６，５０……低ドリフトオペアン
プ、１４，２４，４８……外部入力端子、３６…
…外部出力端子、１８，２０，４０，４２……汎
用オペアンプの反転入力端子で分割する抵抗。
FIG. 1 shows a buffer circuit with automatic offset adjustment according to one embodiment of the present invention, and FIG. 2 shows a similar buffer circuit according to a second embodiment of the invention. FIG. 3 is a diagram showing a non-inverting amplifier circuit with automatic offset adjustment according to a third embodiment of the present invention, and FIG. 4 is a diagram showing a similar inverting amplifier circuit according to a fourth embodiment thereof. FIGS. 5 and 6 are diagrams showing conventional amplifier circuits with offset adjustment. 10, 28, 34, 46...General-purpose operational amplifier,
12, 22, 36, 50...Low drift operational amplifier, 14, 24, 48...External input terminal, 36...
...External output terminal, 18, 20, 40, 42... Resistor divided by the inverting input terminal of the general-purpose operational amplifier.
Claims (1)
出力端子に出力端子を接続した汎用オペアンプと
、その外部入力端子に反転入力端子を接続し、そ
の汎用オペアンプの出力端子に非反転入力端子を
接続した低ドリフトオペアンプとを備え、それら
両オペアンプの出力端子間に、汎用オペアンプの
反転入力端子で分割された抵抗を接続することを
特徴とする自動オフセツト調整付増幅回路。 A general-purpose operational amplifier with one input terminal connected to the external input terminal and an output terminal connected to the external output terminal, an inverting input terminal connected to the external input terminal, and a non-inverting input terminal connected to the output terminal of the general-purpose operational amplifier. 1. An amplifier circuit with automatic offset adjustment, characterized in that a resistor divided by the inverting input terminal of a general-purpose operational amplifier is connected between the output terminals of both operational amplifiers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6487387U JPS63171021U (en) | 1987-04-27 | 1987-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6487387U JPS63171021U (en) | 1987-04-27 | 1987-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63171021U true JPS63171021U (en) | 1988-11-08 |
Family
ID=30901427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6487387U Pending JPS63171021U (en) | 1987-04-27 | 1987-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63171021U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022071000A1 (en) * | 2020-10-02 | 2022-04-07 | 日置電機株式会社 | Differential amplifier circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035293U (en) * | 1983-08-18 | 1985-03-11 | セイコーインスツルメンツ株式会社 | External drive XY sample stage device |
-
1987
- 1987-04-27 JP JP6487387U patent/JPS63171021U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035293U (en) * | 1983-08-18 | 1985-03-11 | セイコーインスツルメンツ株式会社 | External drive XY sample stage device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022071000A1 (en) * | 2020-10-02 | 2022-04-07 | 日置電機株式会社 | Differential amplifier circuit |
| EP4224710A4 (en) * | 2020-10-02 | 2024-11-13 | Hioki E.E. Corporation | Differential amplifier circuit |
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