JPH01172725U - - Google Patents
Info
- Publication number
- JPH01172725U JPH01172725U JP7001088U JP7001088U JPH01172725U JP H01172725 U JPH01172725 U JP H01172725U JP 7001088 U JP7001088 U JP 7001088U JP 7001088 U JP7001088 U JP 7001088U JP H01172725 U JPH01172725 U JP H01172725U
- Authority
- JP
- Japan
- Prior art keywords
- noise
- signal output
- control signal
- controlling
- output control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012935 Averaging Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は雑音の平均化の様子を示す図、第３図は出力
制御信号制限回路３の入出力電圧特性図、第４図
は第二の実施例の出力制御信号制限回路３の入出
力電圧特性図である。
１……信入力端子、２……雑音平均化回路、３
……出力制御信号制限回路、４……出力制御信号
、５……信号増幅器、６……信号出力端子、７…
…マイクロフオン、８……増幅制御信号入力端子
、９……雑音増幅器、１０……制限電圧、１１…
…しや断電圧。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure shows how noise is averaged, Figure 3 shows the input/output voltage characteristics of the output control signal limiting circuit 3, and Figure 4 shows the input/output voltage characteristics of the output control signal limiting circuit 3 of the second embodiment. It is a diagram. 1...Signal input terminal, 2...Noise averaging circuit, 3
...Output control signal limiting circuit, 4...Output control signal, 5...Signal amplifier, 6...Signal output terminal, 7...
... Microphone, 8 ... Amplification control signal input terminal, 9 ... Noise amplifier, 10 ... Limiting voltage, 11 ...
...Shipping voltage.
Claims (1)
音のレベルに対応して信号出力を制御するための
雑音平均化回路と、出力制御信号制限回路を有す
る信号出力装置。 A signal output device for controlling electrical signals, which includes a noise averaging circuit for controlling signal output in response to the level of surrounding noise, and an output control signal limiting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7001088U JPH01172725U (en) | 1988-05-26 | 1988-05-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7001088U JPH01172725U (en) | 1988-05-26 | 1988-05-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01172725U true JPH01172725U (en) | 1989-12-07 |
Family
ID=31295267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7001088U Pending JPH01172725U (en) | 1988-05-26 | 1988-05-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01172725U (en) |
-
1988
- 1988-05-26 JP JP7001088U patent/JPH01172725U/ja active Pending
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