JPH02304938A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPH02304938A JPH02304938A JP12569289A JP12569289A JPH02304938A JP H02304938 A JPH02304938 A JP H02304938A JP 12569289 A JP12569289 A JP 12569289A JP 12569289 A JP12569289 A JP 12569289A JP H02304938 A JPH02304938 A JP H02304938A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate metal
- mask
- semiconductor
- ohmic contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 48
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000010030 laminating Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 5
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
液晶表示素子は低消費電力のフラットパネルディスプレ
イとして広く応用されている。中でも、スイッチング素
子を各画素に作り込んで駆動するアクティブマトリクス
方式は大容量高品質の表示素子としてテレビ、情゛報端
末等に用いられつつある。スイッチング素子としては薄
膜トランジスタ(以下TPTと記す)が使われる。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] Liquid crystal display elements are widely applied as low power consumption flat panel displays. Among these, the active matrix method, in which a switching element is built into each pixel and driven, is being used as a large-capacity, high-quality display element in televisions, information terminals, and the like. A thin film transistor (hereinafter referred to as TPT) is used as the switching element.
本発明はTPTの製造方法に関する。The present invention relates to a method for manufacturing TPT.
第2図、第3図に従来の最も簡単な構造のTPTを示す
。FIGS. 2 and 3 show a conventional TPT with the simplest structure.
第2図はフランスのCNETグループが提案した2枚マ
スク法によるTPTである。まず、ガラス等の基板1上
に透明型ffl I T O’ (酸化インジウム)等
によるソース・ドレイン層8、半導体膜のオーミックコ
ンタクト層7が成膜され、第1のマスクでパタン化され
る。続いて、半導体膜のチャネル層4、ゲート絶縁膜6
、ゲート金属2が連続的に成膜され、第2のマスクでパ
タン化される。Figure 2 shows TPT using the two-mask method proposed by the French CNET group. First, a source/drain layer 8 made of transparent type fflITO' (indium oxide) or the like and an ohmic contact layer 7 made of a semiconductor film are formed on a substrate 1 made of glass or the like, and patterned using a first mask. Next, the channel layer 4 of the semiconductor film and the gate insulating film 6 are formed.
, gate metal 2 is successively deposited and patterned with a second mask.
オーミックコンタクト層7は同一の第2のマスクでパタ
ン化されれば良い。The ohmic contact layer 7 may be patterned using the same second mask.
第3図は松下電器グループが提案した2枚マスク法によ
るTPTである。まず、ガラス等の基板1上にゲート金
属2が成膜され、第1のマスクでパタン化される。続い
て、ゲート絶縁膜6、半導体膜のチャネル層4、オーミ
ックコンタクト層7が連続的に成膜され、ゲート金属2
をマスクとした裏面露光法によってチャネル層4とオー
ミックコンタクト層7とがパタン化される。最後にソー
ス・ドレイン層8が成膜され第2のマスクでパタン化さ
れる。オーミックコンタクト層7は同一の第2のマスク
でパタン化可能である。Figure 3 shows TPT using the two-mask method proposed by the Matsushita Electric Group. First, a gate metal 2 is formed on a substrate 1 such as glass and patterned using a first mask. Subsequently, a gate insulating film 6, a semiconductor channel layer 4, and an ohmic contact layer 7 are successively formed, and a gate metal 2 is formed.
The channel layer 4 and the ohmic contact layer 7 are patterned by a back exposure method using as a mask. Finally, a source/drain layer 8 is formed and patterned using a second mask. The ohmic contact layer 7 can be patterned with the same second mask.
第2図、第3図の従来例は何れも2枚のマスクで製造可
能な優れた方法である。しかし、幾つかの゛欠点が存在
する。The conventional examples shown in FIGS. 2 and 3 are both excellent methods that can be manufactured using two masks. However, there are some drawbacks.
第2図の従来例の欠点は光に対して弱い事である。第2
図からも明らかな如く、ガラスからなる基板1側からの
光照射に対し半導体膜のチャネル層4が全(無防備であ
り光電流によりTPTのスイッチング能力、特にOFF
特性が損なわれる。The disadvantage of the conventional example shown in FIG. 2 is that it is weak against light. Second
As is clear from the figure, the channel layer 4 of the semiconductor film is completely defenseless against light irradiation from the side of the substrate 1 made of glass, and the photocurrent reduces the switching ability of the TPT, especially the OFF state.
properties are impaired.
10万ルクスに及ぶ太陽光下の屋外での使用に耐えるた
めにはガラス基板側に光シールド用の膜(パタン)が必
要となる。以上のように第2図の従来例では実質上は2
枚マスクでは無理であり最低3枚のマスクが必要である
。In order to withstand outdoor use under sunlight of up to 100,000 lux, a light shielding film (pattern) is required on the glass substrate side. As mentioned above, in the conventional example shown in FIG.
It is impossible to do this with just one mask, and at least three masks are required.
第3図の従来例ではガラスからなる基板1側からの光に
対してはゲート金属2がシールドの役割を果たすため問
題は少ない。しかし裏面露光法を用いているため、マス
ク数は2枚であってもフォトリソ工程は3回であり工程
はそれ程簡単ではない。In the conventional example shown in FIG. 3, there are few problems because the gate metal 2 serves as a shield against light from the glass substrate 1 side. However, since the back exposure method is used, the photolithography process is performed three times even though the number of masks is two, and the process is not that simple.
本発明は2枚マスクとい5簡単な製造法で、光にも強い
TPTの製造方法を提供する。The present invention provides a method for manufacturing TPT that is resistant to light, using a simple manufacturing method using two masks.
上記目的を達成するため本発明におけるTPTは下記記
載の工程により製造する。ゲート金属、ゲート絶縁膜、
半導体膜を積層して成膜し第1のマスクでパタン化する
工程と、このゲート金属を実体酸化し酸化膜を形成する
工程と、半導体膜と酸化膜の上にソース・ドレイン層を
成膜し第2のマスクでパタン化する工程とを有する事を
特徴とする。In order to achieve the above object, TPT in the present invention is manufactured by the steps described below. Gate metal, gate insulating film,
A process of stacking and forming a semiconductor film and patterning it with a first mask, a process of substantially oxidizing this gate metal to form an oxide film, and a process of forming a source/drain layer on the semiconductor film and the oxide film. and patterning using a second mask.
第1図に本発明のTPTの製造方法の実施例を示す。 FIG. 1 shows an embodiment of the method for manufacturing TPT of the present invention.
まず第1図囚に示すように、基板1上にTa、T aN
x、Mo、MoSix、kl等のスパッタリング法や真
空蒸着法によって5Qnmから500nmの厚さのゲー
ト金属2を形成する。その後プラズマCVD法やスパッ
タリング法によって1100nから5QQnmの厚さの
SiNx。First, as shown in FIG.
A gate metal 2 having a thickness of 5Qnm to 500nm is formed by sputtering or vacuum evaporation of x, Mo, MoSix, kl, etc. Thereafter, SiNx with a thickness of 1100 nm to 5 QQ nm is formed by plasma CVD or sputtering.
3iQx、 TaQx等のゲート絶縁膜3を形成する。A gate insulating film 3 of 3iQx, TaQx, etc. is formed.
さらにその後プラズマCVD法等によって真性アモルフ
ァスシリコン(a−3i)等のチャネル層4とドープさ
れたa−3i等の半導体膜オーミックコンタクト層5と
からなる半導体膜9を順次積層する。その後節1のマス
クを用いて、半導体膜オーミックコンタクト層5、チャ
ネル層4、ゲート絶縁膜6、ゲート金属2をパタン化す
る。Thereafter, a semiconductor film 9 consisting of a channel layer 4 of intrinsic amorphous silicon (a-3i) or the like and a semiconductor film ohmic contact layer 5 of doped a-3i or the like is sequentially laminated by a plasma CVD method or the like. Then, using the mask of Node 1, the semiconductor film ohmic contact layer 5, channel layer 4, gate insulating film 6, and gate metal 2 are patterned.
次に第1図(B)に示すように、ゲート金属2を実体酸
化し酸化膜6を形成する。Next, as shown in FIG. 1(B), the gate metal 2 is substantially oxidized to form an oxide film 6.
実体酸化し酸化膜6を形成する手段の第1の実施例は陽
極酸化法である。ゲート金属2としてTa、MoSix
等を用い第1図(A)を用いて説明した工程の後にクエ
ン酸等で陽極酸化して酸化膜6を形成する。A first embodiment of the means for forming the oxide film 6 through substantial oxidation is an anodic oxidation method. Ta, MoSix as gate metal 2
After the process described with reference to FIG. 1A, the oxide film 6 is formed by anodic oxidation using citric acid or the like.
実体酸化し酸化膜6を形成する手段の第2の実施例は熱
酸化法である。ゲート金属2としてTa、A7!、MO
lM o S i x等を用い第1図囚を用いて説明し
た工程の後に温度400°C〜500’Cの大気、酸素
、水蒸気雰囲気中で熱酸化して酸化膜6を形成する。こ
の熱酸化工程において、a −Siからなる半導体膜9
表面がわずかに酸化されるので、この半導体膜9表面の
酸化膜をエツチング除去する。半導体膜9表面の酸化膜
の厚さは、ゲート金属2の酸化膜6に比較して極端に薄
いため、上述のエツチングにてゲート金属2の酸化膜6
はわずかにエツチングされるだけである。A second embodiment of the means for forming the oxide film 6 through substantial oxidation is a thermal oxidation method. Ta, A7 as gate metal 2! , M.O.
After the process described using FIG. 1 using lM o S i x or the like, the oxide film 6 is formed by thermal oxidation in an atmosphere of air, oxygen, or water vapor at a temperature of 400° C. to 500° C. In this thermal oxidation step, the semiconductor film 9 made of a-Si
Since the surface is slightly oxidized, the oxide film on the surface of the semiconductor film 9 is removed by etching. Since the thickness of the oxide film on the surface of the semiconductor film 9 is extremely thin compared to the oxide film 6 of the gate metal 2, the oxide film 6 of the gate metal 2 is etched by the above-described etching.
is only slightly etched.
次に第1図(C)に示すように、半導体膜オーミックコ
ンタクト層5と酸化膜6の上にソース・ドレイン層8を
成膜し第2のマスクでパタン化する。Next, as shown in FIG. 1C, a source/drain layer 8 is formed on the semiconductor film ohmic contact layer 5 and the oxide film 6 and patterned using a second mask.
ソース・ドレイン層8としては透過型ディスプレーでは
透明導電膜である例えばITOを用いる。As the source/drain layer 8, a transparent conductive film such as ITO is used in a transmission type display.
成膜法としてはスパッタリング法、真空蒸着法等で行な
い、膜厚は5Qnmから400nfT’lとする。The film formation method is a sputtering method, a vacuum evaporation method, etc., and the film thickness is 5Q nm to 400 nfT'l.
本実施例では第2のマスクでソース・ドレイン層8がパ
タン化された後同一のパタンで半導体膜オーミックコン
タクト層5もパタン化されている。In this embodiment, after the source/drain layer 8 is patterned with the second mask, the semiconductor film ohmic contact layer 5 is also patterned with the same pattern.
以上の実施例で明らかな如く、本発明では2枚マスク工
程という極めて簡単な工程で、従来例と比べ非常に光に
も強いTPTの製造方法を提供することが可能となる。As is clear from the above embodiments, the present invention makes it possible to provide a method for manufacturing TPT that is much more resistant to light than the conventional example, through an extremely simple process of a two-mask process.
第1図へ)〜(C)は本発明の薄膜トランジスタの製造
方法を工程順に示す断面図、第2図および第3図は従来
例における薄膜トランジスタの製造方法を示す断面図で
ある。
1・・・・・・基板、
2・・・・・・ゲート金属、
6・・・・・・ゲート絶縁膜、
4・・・・・・チャネル層、
5・・・・・・オーミックコンタクト層、6・・・・・
・酸化膜、
7・・・・・・オーミックコンタクト層、8・・・・・
・ソース・トンイン層、
9・・・・・・半導体膜。
第3図
ム1) to (C) are cross-sectional views showing the method of manufacturing a thin film transistor according to the present invention in order of steps, and FIGS. 2 and 3 are cross-sectional views showing a conventional method of manufacturing a thin film transistor. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate metal, 6...Gate insulating film, 4...Channel layer, 5...Ohmic contact layer , 6...
・Oxide film, 7... Ohmic contact layer, 8...
- Source tunnel layer, 9... Semiconductor film. Figure 3
Claims (5)
して成膜し第1のマスクでパタン化する工程と、該ゲー
ト金属を実体酸化し酸化膜を形成する工程と、該半導体
膜と酸化膜の上にソース・ドレイン層を成膜し第2のマ
スクでパタン化する工程とを少なくとも有する事を特徴
とする薄膜トランジスタの製造方法。(1) A step of sequentially stacking and forming a gate metal, a gate insulating film, and a semiconductor film and patterning it with a first mask, a step of substantially oxidizing the gate metal to form an oxide film, and a step of forming an oxide film by substantially oxidizing the gate metal. A method for manufacturing a thin film transistor, comprising at least the step of forming a source/drain layer on an oxide film and patterning it using a second mask.
タクト層との積層構造を有し、第2のマスクでソース・
ドレイン層がパタン化された後同一のパタンで該半導体
膜オーミックコンタクト層もパタン化される事を特徴と
する請求項1記載の薄膜トランジスタの製造方法。(2) The semiconductor film has a stacked structure of a channel layer and a semiconductor film ohmic contact layer.
2. The method of manufacturing a thin film transistor according to claim 1, wherein after the drain layer is patterned, the semiconductor film ohmic contact layer is also patterned with the same pattern.
陽極酸化法である事を特徴とする請求項1記載の薄膜ト
ランジスタの製造方法。(3) The method for manufacturing a thin film transistor according to claim 1, wherein the means for substantially oxidizing the gate metal to form an oxide film is an anodic oxidation method.
熱酸化法である事を特徴とする請求項1記載の薄膜トラ
ンジスタの製造方法。(4) The method for manufacturing a thin film transistor according to claim 1, wherein the means for substantially oxidizing the gate metal to form an oxide film is a thermal oxidation method.
る請求項1記載の薄膜トランジスタの製造方法。(5) The method for manufacturing a thin film transistor according to claim 1, wherein the semiconductor film is amorphous Si.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12569289A JPH02304938A (en) | 1989-05-19 | 1989-05-19 | Manufacture of thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12569289A JPH02304938A (en) | 1989-05-19 | 1989-05-19 | Manufacture of thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02304938A true JPH02304938A (en) | 1990-12-18 |
Family
ID=14916337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12569289A Pending JPH02304938A (en) | 1989-05-19 | 1989-05-19 | Manufacture of thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02304938A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5600153A (en) * | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
US5804838A (en) * | 1995-05-26 | 1998-09-08 | Micron Technology, Inc. | Thin film transistors |
US6204521B1 (en) | 1998-08-28 | 2001-03-20 | Micron Technology, Inc. | Thin film transistors |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61185724A (en) * | 1985-02-13 | 1986-08-19 | Sharp Corp | Production for thin film transistor |
JPH0258347B2 (en) * | 1982-11-05 | 1990-12-07 | Sankyo Gokin Chuzosho Kk |
-
1989
- 1989-05-19 JP JP12569289A patent/JPH02304938A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0258347B2 (en) * | 1982-11-05 | 1990-12-07 | Sankyo Gokin Chuzosho Kk | |
JPS61185724A (en) * | 1985-02-13 | 1986-08-19 | Sharp Corp | Production for thin film transistor |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5600153A (en) * | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
US5658807A (en) * | 1994-10-07 | 1997-08-19 | Micron Technology, Inc. | Methods of forming conductive polysilicon lines and bottom gated thin film transistors |
US5670794A (en) * | 1994-10-07 | 1997-09-23 | Micron Technology, Inc. | Thin film transistors |
US5985702A (en) * | 1994-10-07 | 1999-11-16 | Micron Technology, Inc, | Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors |
US5804838A (en) * | 1995-05-26 | 1998-09-08 | Micron Technology, Inc. | Thin film transistors |
US6204521B1 (en) | 1998-08-28 | 2001-03-20 | Micron Technology, Inc. | Thin film transistors |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101280827B1 (en) | Array substrate and method of fabricating the same | |
TW519763B (en) | Active matrix LCD panel | |
US6329672B1 (en) | Thin film transistor having a second gate metal layer preventing formation of hillocks | |
US5856858A (en) | Plastic substrates for active matrix liquid crystal display incapable of withstanding processing temperature of over 200° C and method of fabrication | |
JPH0311744A (en) | Manufacture of thin film transistor | |
KR0175390B1 (en) | Polysilicon tft and the manufacture thereof | |
WO2015096307A1 (en) | Oxide thin-film transistor, display device and manufacturing method for array substrate | |
CN105679705A (en) | Manufacturing method of array substrate | |
JP3708150B2 (en) | Thin film transistor substrate | |
JPS59113667A (en) | Manufacturing method of thin film transistor | |
JPS6349914B2 (en) | ||
CN101118881A (en) | Method for manufacturing pixel structure | |
JPH02304938A (en) | Manufacture of thin-film transistor | |
JPH01309378A (en) | thin film semiconductor device | |
JP3438178B2 (en) | Thin film transistor array and liquid crystal display device using the same | |
JPH0332231B2 (en) | ||
KR100539583B1 (en) | Method for crystallizing Silicon and method for manufacturing Thin Film Transistor (TFT) using the same | |
KR20100130523A (en) | Array substrate including thin film transistor using polysilicon and manufacturing method thereof | |
KR100390457B1 (en) | A structure of thin film transistor and a method for manufacturing the same | |
JP2862737B2 (en) | Thin film transistor and method of manufacturing the same | |
JPH01267616A (en) | lcd display | |
JP3707318B2 (en) | Liquid crystal display device and manufacturing method thereof | |
JPH03790B2 (en) | ||
JPH04106938A (en) | Thin film field-effect transistor | |
JPH02203568A (en) | Thin film transistor |