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JPH02304938A - Manufacture of thin-film transistor - Google Patents

Manufacture of thin-film transistor

Info

Publication number
JPH02304938A
JPH02304938A JP12569289A JP12569289A JPH02304938A JP H02304938 A JPH02304938 A JP H02304938A JP 12569289 A JP12569289 A JP 12569289A JP 12569289 A JP12569289 A JP 12569289A JP H02304938 A JPH02304938 A JP H02304938A
Authority
JP
Japan
Prior art keywords
film
gate metal
mask
semiconductor
ohmic contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12569289A
Other languages
Japanese (ja)
Inventor
Seigo Togashi
清吾 富樫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP12569289A priority Critical patent/JPH02304938A/en
Publication of JPH02304938A publication Critical patent/JPH02304938A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To manufacture a TFT resisting light by two masks by laminating a gate metal, a gate insulating film and a semiconductor film to form a film, patterning the film by a first mask, substantially oxidizing the gate metal to shape an oxide film, film-forming source-drain layers onto the semiconductor film and the oxide film and patterning the film of the source-drain layers by a second mask. CONSTITUTION:A gate metal 2 and a gate insulating film 3 are formed onto a substrate 1, and a semiconductor film 9 composed of a channel layer 4 and a semiconductor-film ohmic contact layer 5 consisting of doped a-Si, etc., is laminated successively. The semiconductor-film ohmic contact layer 5, the channel layer 4, the gate insulating film 3 and the gate metal 2 are patterned by using a first mask. The gate metal 2 is oxidized substantially to shape an oxide film 6, and source-drain layers 8 are film-formed onto the semiconductor-film ohmic contact layer 5 and the oxide film 6 and patterned by a second mask. The semiconductor-film ohmic contact layer 5 is also patterned by the same pattern. Accordingly, a TFT resisting even light can be manufactured through a simple process such as a two-mask process.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 液晶表示素子は低消費電力のフラットパネルディスプレ
イとして広く応用されている。中でも、スイッチング素
子を各画素に作り込んで駆動するアクティブマトリクス
方式は大容量高品質の表示素子としてテレビ、情゛報端
末等に用いられつつある。スイッチング素子としては薄
膜トランジスタ(以下TPTと記す)が使われる。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] Liquid crystal display elements are widely applied as low power consumption flat panel displays. Among these, the active matrix method, in which a switching element is built into each pixel and driven, is being used as a large-capacity, high-quality display element in televisions, information terminals, and the like. A thin film transistor (hereinafter referred to as TPT) is used as the switching element.

本発明はTPTの製造方法に関する。The present invention relates to a method for manufacturing TPT.

〔従来の技術〕[Conventional technology]

第2図、第3図に従来の最も簡単な構造のTPTを示す
FIGS. 2 and 3 show a conventional TPT with the simplest structure.

第2図はフランスのCNETグループが提案した2枚マ
スク法によるTPTである。まず、ガラス等の基板1上
に透明型ffl I T O’ (酸化インジウム)等
によるソース・ドレイン層8、半導体膜のオーミックコ
ンタクト層7が成膜され、第1のマスクでパタン化され
る。続いて、半導体膜のチャネル層4、ゲート絶縁膜6
、ゲート金属2が連続的に成膜され、第2のマスクでパ
タン化される。
Figure 2 shows TPT using the two-mask method proposed by the French CNET group. First, a source/drain layer 8 made of transparent type fflITO' (indium oxide) or the like and an ohmic contact layer 7 made of a semiconductor film are formed on a substrate 1 made of glass or the like, and patterned using a first mask. Next, the channel layer 4 of the semiconductor film and the gate insulating film 6 are formed.
, gate metal 2 is successively deposited and patterned with a second mask.

オーミックコンタクト層7は同一の第2のマスクでパタ
ン化されれば良い。
The ohmic contact layer 7 may be patterned using the same second mask.

第3図は松下電器グループが提案した2枚マスク法によ
るTPTである。まず、ガラス等の基板1上にゲート金
属2が成膜され、第1のマスクでパタン化される。続い
て、ゲート絶縁膜6、半導体膜のチャネル層4、オーミ
ックコンタクト層7が連続的に成膜され、ゲート金属2
をマスクとした裏面露光法によってチャネル層4とオー
ミックコンタクト層7とがパタン化される。最後にソー
ス・ドレイン層8が成膜され第2のマスクでパタン化さ
れる。オーミックコンタクト層7は同一の第2のマスク
でパタン化可能である。
Figure 3 shows TPT using the two-mask method proposed by the Matsushita Electric Group. First, a gate metal 2 is formed on a substrate 1 such as glass and patterned using a first mask. Subsequently, a gate insulating film 6, a semiconductor channel layer 4, and an ohmic contact layer 7 are successively formed, and a gate metal 2 is formed.
The channel layer 4 and the ohmic contact layer 7 are patterned by a back exposure method using as a mask. Finally, a source/drain layer 8 is formed and patterned using a second mask. The ohmic contact layer 7 can be patterned with the same second mask.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第2図、第3図の従来例は何れも2枚のマスクで製造可
能な優れた方法である。しかし、幾つかの゛欠点が存在
する。
The conventional examples shown in FIGS. 2 and 3 are both excellent methods that can be manufactured using two masks. However, there are some drawbacks.

第2図の従来例の欠点は光に対して弱い事である。第2
図からも明らかな如く、ガラスからなる基板1側からの
光照射に対し半導体膜のチャネル層4が全(無防備であ
り光電流によりTPTのスイッチング能力、特にOFF
特性が損なわれる。
The disadvantage of the conventional example shown in FIG. 2 is that it is weak against light. Second
As is clear from the figure, the channel layer 4 of the semiconductor film is completely defenseless against light irradiation from the side of the substrate 1 made of glass, and the photocurrent reduces the switching ability of the TPT, especially the OFF state.
properties are impaired.

10万ルクスに及ぶ太陽光下の屋外での使用に耐えるた
めにはガラス基板側に光シールド用の膜(パタン)が必
要となる。以上のように第2図の従来例では実質上は2
枚マスクでは無理であり最低3枚のマスクが必要である
In order to withstand outdoor use under sunlight of up to 100,000 lux, a light shielding film (pattern) is required on the glass substrate side. As mentioned above, in the conventional example shown in FIG.
It is impossible to do this with just one mask, and at least three masks are required.

第3図の従来例ではガラスからなる基板1側からの光に
対してはゲート金属2がシールドの役割を果たすため問
題は少ない。しかし裏面露光法を用いているため、マス
ク数は2枚であってもフォトリソ工程は3回であり工程
はそれ程簡単ではない。
In the conventional example shown in FIG. 3, there are few problems because the gate metal 2 serves as a shield against light from the glass substrate 1 side. However, since the back exposure method is used, the photolithography process is performed three times even though the number of masks is two, and the process is not that simple.

本発明は2枚マスクとい5簡単な製造法で、光にも強い
TPTの製造方法を提供する。
The present invention provides a method for manufacturing TPT that is resistant to light, using a simple manufacturing method using two masks.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため本発明におけるTPTは下記記
載の工程により製造する。ゲート金属、ゲート絶縁膜、
半導体膜を積層して成膜し第1のマスクでパタン化する
工程と、このゲート金属を実体酸化し酸化膜を形成する
工程と、半導体膜と酸化膜の上にソース・ドレイン層を
成膜し第2のマスクでパタン化する工程とを有する事を
特徴とする。
In order to achieve the above object, TPT in the present invention is manufactured by the steps described below. Gate metal, gate insulating film,
A process of stacking and forming a semiconductor film and patterning it with a first mask, a process of substantially oxidizing this gate metal to form an oxide film, and a process of forming a source/drain layer on the semiconductor film and the oxide film. and patterning using a second mask.

〔実施例〕〔Example〕

第1図に本発明のTPTの製造方法の実施例を示す。 FIG. 1 shows an embodiment of the method for manufacturing TPT of the present invention.

まず第1図囚に示すように、基板1上にTa、T aN
x、Mo、MoSix、kl等のスパッタリング法や真
空蒸着法によって5Qnmから500nmの厚さのゲー
ト金属2を形成する。その後プラズマCVD法やスパッ
タリング法によって1100nから5QQnmの厚さの
SiNx。
First, as shown in FIG.
A gate metal 2 having a thickness of 5Qnm to 500nm is formed by sputtering or vacuum evaporation of x, Mo, MoSix, kl, etc. Thereafter, SiNx with a thickness of 1100 nm to 5 QQ nm is formed by plasma CVD or sputtering.

3iQx、 TaQx等のゲート絶縁膜3を形成する。A gate insulating film 3 of 3iQx, TaQx, etc. is formed.

さらにその後プラズマCVD法等によって真性アモルフ
ァスシリコン(a−3i)等のチャネル層4とドープさ
れたa−3i等の半導体膜オーミックコンタクト層5と
からなる半導体膜9を順次積層する。その後節1のマス
クを用いて、半導体膜オーミックコンタクト層5、チャ
ネル層4、ゲート絶縁膜6、ゲート金属2をパタン化す
る。
Thereafter, a semiconductor film 9 consisting of a channel layer 4 of intrinsic amorphous silicon (a-3i) or the like and a semiconductor film ohmic contact layer 5 of doped a-3i or the like is sequentially laminated by a plasma CVD method or the like. Then, using the mask of Node 1, the semiconductor film ohmic contact layer 5, channel layer 4, gate insulating film 6, and gate metal 2 are patterned.

次に第1図(B)に示すように、ゲート金属2を実体酸
化し酸化膜6を形成する。
Next, as shown in FIG. 1(B), the gate metal 2 is substantially oxidized to form an oxide film 6.

実体酸化し酸化膜6を形成する手段の第1の実施例は陽
極酸化法である。ゲート金属2としてTa、MoSix
等を用い第1図(A)を用いて説明した工程の後にクエ
ン酸等で陽極酸化して酸化膜6を形成する。
A first embodiment of the means for forming the oxide film 6 through substantial oxidation is an anodic oxidation method. Ta, MoSix as gate metal 2
After the process described with reference to FIG. 1A, the oxide film 6 is formed by anodic oxidation using citric acid or the like.

実体酸化し酸化膜6を形成する手段の第2の実施例は熱
酸化法である。ゲート金属2としてTa、A7!、MO
lM o S i x等を用い第1図囚を用いて説明し
た工程の後に温度400°C〜500’Cの大気、酸素
、水蒸気雰囲気中で熱酸化して酸化膜6を形成する。こ
の熱酸化工程において、a −Siからなる半導体膜9
表面がわずかに酸化されるので、この半導体膜9表面の
酸化膜をエツチング除去する。半導体膜9表面の酸化膜
の厚さは、ゲート金属2の酸化膜6に比較して極端に薄
いため、上述のエツチングにてゲート金属2の酸化膜6
はわずかにエツチングされるだけである。
A second embodiment of the means for forming the oxide film 6 through substantial oxidation is a thermal oxidation method. Ta, A7 as gate metal 2! , M.O.
After the process described using FIG. 1 using lM o S i x or the like, the oxide film 6 is formed by thermal oxidation in an atmosphere of air, oxygen, or water vapor at a temperature of 400° C. to 500° C. In this thermal oxidation step, the semiconductor film 9 made of a-Si
Since the surface is slightly oxidized, the oxide film on the surface of the semiconductor film 9 is removed by etching. Since the thickness of the oxide film on the surface of the semiconductor film 9 is extremely thin compared to the oxide film 6 of the gate metal 2, the oxide film 6 of the gate metal 2 is etched by the above-described etching.
is only slightly etched.

次に第1図(C)に示すように、半導体膜オーミックコ
ンタクト層5と酸化膜6の上にソース・ドレイン層8を
成膜し第2のマスクでパタン化する。
Next, as shown in FIG. 1C, a source/drain layer 8 is formed on the semiconductor film ohmic contact layer 5 and the oxide film 6 and patterned using a second mask.

ソース・ドレイン層8としては透過型ディスプレーでは
透明導電膜である例えばITOを用いる。
As the source/drain layer 8, a transparent conductive film such as ITO is used in a transmission type display.

成膜法としてはスパッタリング法、真空蒸着法等で行な
い、膜厚は5Qnmから400nfT’lとする。
The film formation method is a sputtering method, a vacuum evaporation method, etc., and the film thickness is 5Q nm to 400 nfT'l.

本実施例では第2のマスクでソース・ドレイン層8がパ
タン化された後同一のパタンで半導体膜オーミックコン
タクト層5もパタン化されている。
In this embodiment, after the source/drain layer 8 is patterned with the second mask, the semiconductor film ohmic contact layer 5 is also patterned with the same pattern.

〔発明の効果〕〔Effect of the invention〕

以上の実施例で明らかな如く、本発明では2枚マスク工
程という極めて簡単な工程で、従来例と比べ非常に光に
も強いTPTの製造方法を提供することが可能となる。
As is clear from the above embodiments, the present invention makes it possible to provide a method for manufacturing TPT that is much more resistant to light than the conventional example, through an extremely simple process of a two-mask process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図へ)〜(C)は本発明の薄膜トランジスタの製造
方法を工程順に示す断面図、第2図および第3図は従来
例における薄膜トランジスタの製造方法を示す断面図で
ある。 1・・・・・・基板、 2・・・・・・ゲート金属、 6・・・・・・ゲート絶縁膜、 4・・・・・・チャネル層、 5・・・・・・オーミックコンタクト層、6・・・・・
・酸化膜、 7・・・・・・オーミックコンタクト層、8・・・・・
・ソース・トンイン層、 9・・・・・・半導体膜。 第3図 ム
1) to (C) are cross-sectional views showing the method of manufacturing a thin film transistor according to the present invention in order of steps, and FIGS. 2 and 3 are cross-sectional views showing a conventional method of manufacturing a thin film transistor. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate metal, 6...Gate insulating film, 4...Channel layer, 5...Ohmic contact layer , 6...
・Oxide film, 7... Ohmic contact layer, 8...
- Source tunnel layer, 9... Semiconductor film. Figure 3

Claims (5)

【特許請求の範囲】[Claims] (1)ゲート金属、ゲート絶縁膜、半導体膜を順次積層
して成膜し第1のマスクでパタン化する工程と、該ゲー
ト金属を実体酸化し酸化膜を形成する工程と、該半導体
膜と酸化膜の上にソース・ドレイン層を成膜し第2のマ
スクでパタン化する工程とを少なくとも有する事を特徴
とする薄膜トランジスタの製造方法。
(1) A step of sequentially stacking and forming a gate metal, a gate insulating film, and a semiconductor film and patterning it with a first mask, a step of substantially oxidizing the gate metal to form an oxide film, and a step of forming an oxide film by substantially oxidizing the gate metal. A method for manufacturing a thin film transistor, comprising at least the step of forming a source/drain layer on an oxide film and patterning it using a second mask.
(2)半導体膜はチャネル層と半導体膜オーミックコン
タクト層との積層構造を有し、第2のマスクでソース・
ドレイン層がパタン化された後同一のパタンで該半導体
膜オーミックコンタクト層もパタン化される事を特徴と
する請求項1記載の薄膜トランジスタの製造方法。
(2) The semiconductor film has a stacked structure of a channel layer and a semiconductor film ohmic contact layer.
2. The method of manufacturing a thin film transistor according to claim 1, wherein after the drain layer is patterned, the semiconductor film ohmic contact layer is also patterned with the same pattern.
(3)ゲート金属を実体酸化し酸化膜を形成する手段は
陽極酸化法である事を特徴とする請求項1記載の薄膜ト
ランジスタの製造方法。
(3) The method for manufacturing a thin film transistor according to claim 1, wherein the means for substantially oxidizing the gate metal to form an oxide film is an anodic oxidation method.
(4)ゲート金属を実体酸化し酸化膜を形成する手段は
熱酸化法である事を特徴とする請求項1記載の薄膜トラ
ンジスタの製造方法。
(4) The method for manufacturing a thin film transistor according to claim 1, wherein the means for substantially oxidizing the gate metal to form an oxide film is a thermal oxidation method.
(5)半導体膜はアモルファスSiである事を特徴とす
る請求項1記載の薄膜トランジスタの製造方法。
(5) The method for manufacturing a thin film transistor according to claim 1, wherein the semiconductor film is amorphous Si.
JP12569289A 1989-05-19 1989-05-19 Manufacture of thin-film transistor Pending JPH02304938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12569289A JPH02304938A (en) 1989-05-19 1989-05-19 Manufacture of thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12569289A JPH02304938A (en) 1989-05-19 1989-05-19 Manufacture of thin-film transistor

Publications (1)

Publication Number Publication Date
JPH02304938A true JPH02304938A (en) 1990-12-18

Family

ID=14916337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12569289A Pending JPH02304938A (en) 1989-05-19 1989-05-19 Manufacture of thin-film transistor

Country Status (1)

Country Link
JP (1) JPH02304938A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600153A (en) * 1994-10-07 1997-02-04 Micron Technology, Inc. Conductive polysilicon lines and thin film transistors
US5804838A (en) * 1995-05-26 1998-09-08 Micron Technology, Inc. Thin film transistors
US6204521B1 (en) 1998-08-28 2001-03-20 Micron Technology, Inc. Thin film transistors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61185724A (en) * 1985-02-13 1986-08-19 Sharp Corp Production for thin film transistor
JPH0258347B2 (en) * 1982-11-05 1990-12-07 Sankyo Gokin Chuzosho Kk

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258347B2 (en) * 1982-11-05 1990-12-07 Sankyo Gokin Chuzosho Kk
JPS61185724A (en) * 1985-02-13 1986-08-19 Sharp Corp Production for thin film transistor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600153A (en) * 1994-10-07 1997-02-04 Micron Technology, Inc. Conductive polysilicon lines and thin film transistors
US5658807A (en) * 1994-10-07 1997-08-19 Micron Technology, Inc. Methods of forming conductive polysilicon lines and bottom gated thin film transistors
US5670794A (en) * 1994-10-07 1997-09-23 Micron Technology, Inc. Thin film transistors
US5985702A (en) * 1994-10-07 1999-11-16 Micron Technology, Inc, Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors
US5804838A (en) * 1995-05-26 1998-09-08 Micron Technology, Inc. Thin film transistors
US6204521B1 (en) 1998-08-28 2001-03-20 Micron Technology, Inc. Thin film transistors

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