JP3707318B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly to a high-quality active matrix liquid crystal display device using a highly reliable thin film semiconductor element and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art An active matrix liquid crystal display device using a thin film transistor (hereinafter referred to as TFT) is known as a display device for image information and character information of OA equipment and the like. Conventionally, in this type of liquid crystal display device, high definition and high image quality are important issues along with cost reduction. In order to solve these problems, it is indispensable to improve the performance of TFT as a key device.
[0003]
When forming a high-performance TFT on an inexpensive glass substrate, for example, as described in JP-A-8-167722, a peripheral drive circuit for driving a TFT active matrix is also composed of TFTs, and the same substrate. Attempts have been made to reduce costs by accumulating on top.
[0004]
If a higher-performance peripheral drive circuit can be integrated on a glass substrate, the circuit configuration to be mounted outside and the mounting process can be simplified, so that a significant reduction in mounting cost can be expected. In order to construct a highly functional circuit, a higher performance TFT is required. Particularly, a poly-Si TFT formed on a polycrystalline silicon (hereinafter referred to as poly-Si) film is expected as a TFT for a liquid crystal display device integrated with a peripheral drive circuit. In order to form a peripheral driver circuit integrated liquid crystal display device on an inexpensive glass substrate, it is necessary to lower the process temperature for forming TFTs to at least 450 ° C. or lower. In such a low temperature process, for example, the film quality of the gate insulating film of the TFT cannot be as good as that of a thermal oxide film formed at a high temperature, so that degradation of the element due to hot carrier injection becomes a problem. In particular, with the recent introduction of high-quality poly-Si film formation technology using laser recrystallization, the carrier mobility in TFTs has improved, so the solution of device degradation due to hot carriers has become an important issue. ing. Needless to say, TFT characteristic deterioration is a problem directly related to display image deterioration such as image flicker and contrast ratio reduction through deterioration of drive circuit characteristics and pixel switching element characteristics.
[0005]
It is known that device degradation due to hot carriers is caused by a high electric field in the vicinity of the drain junction of the transistor, and it is generally practiced to prevent degradation by relaxing the drain junction electric field by devising the device structure. Yes.
[0006]
However, even if such a countermeasure on the element structure is taken, the hot carrier deterioration of the TFT cannot be completely suppressed. This is because, as described above, it is difficult to obtain a high-quality insulating film comparable to a thermal oxide film in a low temperature process.
On the other hand, several film forming methods for forming a high-quality insulating film at a low temperature have been proposed. For example, as described in JP-A-62-71276, a high-density plasma is used.
It has been proposed to form a gate insulating film by electron cyclotron resonance (ECR) plasma CVD, which is a type of CVD.
[0007]
In addition to this ECR-CVD, there are several high-density plasma CVD methods such as inductively coupled (ICP) plasma CVD and helicon plasma CVD. According to these high-density plasma CVD methods, it is known that a dense film close to a thermal oxide film can be obtained even at a low temperature around room temperature.
[0008]
[Problems to be solved by the invention]
In these insulating film forming methods using high-density plasma, the film pressure is reduced because the film is densified by ion bombardment on the film surface. Therefore, there is a problem that the directionality of film formation is strong and the coverage of the step portion is inferior. This problem becomes a serious problem for a TFT element having a general structure in which elements are separated by etching a Si film.
[0009]
That is, due to the poor step coverage of the gate oxide film, the gate-source dielectric strength is significantly reduced. Moreover, the threshold voltage of the side surface portion is reduced because the oxide film thickness is thinner in the side surface portion than in the flat surface portion. Therefore, the TFT characteristics are as if a plurality of TFTs having different threshold voltages are connected in parallel, and the current is not proportional to the channel width. Further, since a large gate electric field is applied to the thin oxide film on the side surface, there is a problem that hot carrier deterioration is accelerated in this portion. Due to such problems, the insulating film formed by high-density plasma CVD has excellent film quality at the flat portion, but is difficult to apply to an actual TFT element.
[0010]
In addition, even when an insulating film formed by such normal plasma CVD that is not high-density plasma is used, the film thickness of the side surface portion and the flat portion cannot be made completely the same. There is more or less. Such a problem becomes more apparent when the gate insulating film is made thinner in order to improve the transconductance of the TFT. Therefore, in the conventional coplanar type TFT, no matter what film forming method is used, there is a limit to making the gate insulating film thin. This means that gm improvement cannot be expected by reducing the gate length according to the scaling rule of the MOS transistor.
[0011]
An object of the present invention is to provide a liquid crystal display device having an element structure that can solve the problems of reliability and limit of performance improvement of a TFT having a sidewall in an active layer, and a manufacturing method thereof.
[0012]
[Means for Solving the Problems]
A feature of the present invention is that a plurality of semiconductor films and a first insulating layer formed on a main surface of a substrate, a first electrode opposed to at least a part of the plurality of semiconductor films via a gate insulating film, A pair of semiconductor layers having a first conductivity type or a second conductivity type formed in a part of the semiconductor film, and second and third electrodes formed to be in contact with the pair of semiconductor layers; The side surfaces of the plurality of semiconductor films have a structure in which the gate insulating film does not have a contact portion.
[0013]
Another feature of the present invention is that the plurality of semiconductor films and the first insulating layer formed on the main surface of the substrate, and the first semiconductor layer opposed to at least a part of the plurality of semiconductor films via the gate insulating film. One electrode, a pair of semiconductor layers having a first conductivity type or a second conductivity type formed on a part of the semiconductor film, a second and a second formed to be in contact with the pair of semiconductor layers; 3, and the side surface portions of the plurality of semiconductor films are in contact with only the first insulating layer and do not have contact portions with the gate insulating film. That is, the side surface of the semiconductor pattern is in contact with only the first insulating film formed on the same surface as the semiconductor film. Since the first insulating film is in the same plane as the semiconductor pattern and does not act as a gate insulating film of the transistor, a parasitic channel is not formed on the side surface of the semiconductor pattern. Therefore, the problem caused by the existence of the pattern side surface as described above is solved.
[0014]
Another feature of the present invention is that a parasitic channel is formed at a portion where the gate electrode and the semiconductor pattern intersect, so that a plurality of semiconductor films and a first insulating layer formed on the main surface of the substrate A pair of semiconductors having a first conductivity type or a second conductivity type formed on a part of the semiconductor film, a first electrode opposed to at least a part of the plurality of semiconductor films via a gate insulating film Side surfaces of the plurality of semiconductor films at least in a portion intersecting the first electrode, and a second electrode and a third electrode formed so as to be in contact with the pair of semiconductor layers. The structure is in contact with the first insulating layer and not in contact with the gate insulating film. Thereby, the same effect is acquired. The first insulating film is preferably a silicon oxide film containing phosphorus, boron, or both. This is because it becomes easy to form at a low temperature as will be described later. As a result, a glass substrate having a strain point of 720 ° C. or lower or a plastic substrate can be used as the substrate, and the cost of the entire display device can be reduced.
[0015]
Further, as a manufacturing method for forming such a structure, a step of forming a semiconductor film over substantially the entire main surface of the substrate, and a step of selectively introducing phosphorus and / or boron into a predetermined region of the semiconductor film And a step of oxidizing a predetermined region of the semiconductor film into which phosphorus or boron or both are introduced to form an insulating film, and separating the semiconductor film into a plurality of semiconductor patterns, and introducing phosphorus or boron or both A manufacturing method including at least an insulating film and a step of forming a gate insulating film on the plurality of semiconductor patterns is adopted. It is desirable to selectively introduce phosphorus, boron, or both only into the semiconductor region to be converted into an insulating film. As a result, the semiconductor film can be oxidized to form an insulating film at a low temperature at which the glass substrate can be used. As an oxidation method, a method in which the semiconductor into which phosphorus or boron or both are introduced is oxidized by being exposed to plasma containing oxygen at a temperature of 450 ° C. or lower can be applied.
[0016]
In order to completely oxidize a semiconductor film having a thickness of 50 nm or more at such a low temperature, the phosphorus or boron is converted to 1E with an acceleration energy of less than 10 keV. ¹⁶ (cm ^-2 It is desirable to introduce the above. By introducing such a large amount of impurities with low acceleration energy, the oxidation rate of the semiconductor film is remarkably increased, so that a sufficient oxidation rate can be obtained at a low temperature at which a glass substrate can be used. . As the oxidation method, in addition to the method of exposing to oxygen-containing plasma, a method of anodizing in a dilute hydrofluoric acid solution can be performed at a low temperature, so that a glass substrate can be applied. In addition, it is preferable that the thickness of the first insulating film does not exceed 1.2 times the thickness of the semiconductor pattern. The first insulating layer is preferably a silicon oxide film containing phosphorus or boron or both. The irregularities on the main surface of the plurality of semiconductor films are desirably 10 nm or less at maximum. The thickness of the gate insulating film is preferably 50 nm or less. The main surface of the one substrate is preferably covered with a silicon nitride film. The phosphorus or boron has an acceleration energy of less than 10 keV, and the implantation amount is 1E in area density. ¹⁶ (cm ^-2 Or more. Further, it is desirable to oxidize the semiconductor into which phosphorus or boron or both of them are oxidized to form an insulating film by exposure to plasma containing oxygen at a temperature of 450 ° C. or lower. In addition, it is desirable to oxidize the semiconductor into which phosphorus or boron or both are introduced to form an insulating film by anodizing in a solution.
[0017]
The main surface of the substrate is preferably insulative. The semiconductor film formed over the main surface of the substrate includes a case where an insulating film layer serving as a buffer layer for suppressing entry of impurities from the substrate is provided between the semiconductor film and the substrate. When the influence of impurities from the substrate can be ignored, a semiconductor film can be formed directly on the substrate.
[0018]
Other features of the present invention will be apparent from the following embodiments.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
(Embodiment 1)
FIG. 1 is a sectional view of a thin film transistor (TFT) used in the liquid crystal display device of the first embodiment of the present invention. The left side of FIG. 1 is a p-type TFT used for a CMOS peripheral drive circuit, the center of FIG. 1 is an n-type TFT used for a CMOS peripheral drive circuit, and the right side of FIG. 1 is an n-type used for a TFT matrix of an image display unit. It is sectional drawing of TFT.
[0021]
FIG. 2 is a plan view of a TFT element corresponding to each TFT in FIG. In FIG. 2, a cross section taken along lines AA ', BB', and CC 'is shown in FIG. 1, and a cross section taken along line DD' is shown in FIG.
[0022]
The TFT is made of SiO2 having a film thickness of 250 nm on a glass substrate 1 made of alkali-free glass having a strain point of 670 ° C. ₂ It is formed on a buffer layer 21 made of a film. The buffer layer 21 serves to prevent diffusion of impurities such as Na from the glass substrate 1. An intrinsic polycrystalline Si (hereinafter referred to as poly-Si) film 30 having a film thickness of 55 nm is formed on the buffer layer 21, and the intrinsic poly-Si film 30 is a pair of low-resistance p-type poly-Si films in the p-type TFT. The n-type TFT is in contact with a pair of high-resistance n-type poly-Si films 33, and each of the pair of high-resistance n-type poly-Si films 33 serves as a source and a drain. It is in contact with the Si film 31. The high-resistance n-type poly-Si film 33 functions as an LDD (Lightly Doped Drain) layer, has a function of relaxing the horizontal electric field in the vicinity of the drain in the poly-Si layer and suppressing the generation of hot carriers. The sheet resistance value of the high resistance n-type layer is preferably 20 KΩ to 100 KΩ, and the sheet resistance value of the low resistance poly-Si film is preferably 500 to 10,000 Ω. The above intrinsic poly-Si film, p-type and n-type poly-Si film are SiO having a film thickness substantially equal to that of the poly-Si film. ₂ This embodiment is characterized in that it is formed so as to be surrounded by the element isolation insulating film 24 made of 70nm thick SiO ₂ The gate insulating film 20 is formed so as to cover the surfaces of the poly-Si films 30, 31, 32, 33 and the element isolation insulating film 24. Therefore, as shown in FIG. 3, the side surface of the poly-Si film 30 is in contact with only the element isolation insulating film 24 and is not in contact with the gate insulating film. A gate electrode 10 is formed on the intrinsic poly-Si 30 via a gate insulating film 20. SiO to cover all the above members ₂ An interlayer insulating film 22 made of is formed. The drain electrode 12 and the source electrode 13 made of a Ti / Al / Ti three-layer metal film are connected to the p-type and n-type low-resistance poly-Si layers through contact through holes provided in the interlayer insulating film 22. ing. The Ti film below Al is provided to reduce the contact resistance between the low-resistance poly-Si film and Al, and the Ti film above Al is provided to reduce the contact resistance between the source electrode and the pixel electrode. The whole TFT element is Si with a film thickness of 500 nm. _Three N _Four The pixel electrode 14 made of ITO is connected to the source electrode 13 of the n-type TFT of the image display portion through a contact through hole provided in the protective insulating film. As in this embodiment, the poly-Si film pattern is surrounded by the element isolation insulating film 24 having substantially the same film thickness, the step at the end of the poly-Si film pattern is eliminated, and the contact between the gate insulating film and the side surface of the poly-Si film pattern is eliminated. By eliminating the portion, it is possible to prevent the occurrence of a parasitic channel due to the thin gate insulating film on the side surface of the poly-Si film pattern, and to improve the reliability of the element. Here, the element isolation insulating film 24 needs to satisfy the following requirements. First, it is necessary that the glass substrate can be formed at a usable low temperature. This is possible by adopting the manufacturing process described later. ₂ The film preferably contains impurities of phosphorus, boron, or both. In order to reduce the level difference at the end of the poly-Si film pattern, it is desirable that the film thicknesses of the poly-Si film and the element isolation insulating film are substantially equal. This can be almost achieved by directly oxidizing an unnecessary poly-Si film.
[0023]
Further, in the transmission type liquid crystal display device, the transmittance of the light transmission portion needs to be sufficiently large. Therefore, the element isolation insulating film needs to have a transmittance of 95% or more in the visible light region. This requirement is satisfied with a Si self-oxidation film. Further, in order to complete isolation between elements, the element isolation insulating film needs to have a sufficiently high specific resistance. 10 for practical use ¹² It only needs to have a specific resistance of Ω or more. This is almost satisfactory with a Si self-oxidation film.
[0024]
(Embodiment 2)
FIG. 4 is a plan view of a thin film transistor (TFT) used in the liquid crystal display device of the second embodiment of the present invention. 4, the left side is a p-type TFT used in a CMOS peripheral drive circuit, the center in FIG. 4 is an n-type TFT used in a CMOS peripheral drive circuit, and the right side in FIG. 4 is an n-type used in a TFT matrix of an image display unit. It is each a top view of TFT. 5 and 6 are cross-sectional views taken along lines EE ′ and FF ′ in FIG.
[0025]
The configuration of the second embodiment is substantially the same as that of the first embodiment, but is characterized in that the element isolation insulating film 24 is formed only around the poly-Si film pattern. Even in such a configuration, as can be seen from FIG. 6, the side surface of the poly-Si film 30 is in contact with only the element isolation insulating film 24 and is not in direct contact with the gate insulating film. The minimum width of the element isolation insulating film 24 around the poly-Si film pattern is determined by the accuracy of lithography, but in the present embodiment, it is 2 μm. An electric field from the gate electrode 10 is applied to the side surface of the poly-Si film 30 via the gate insulating film 20 and the element isolation insulating film 24, but the width of the element isolation insulating film 24 is larger than the thickness of the gate insulating film 20. The resistance of the channel formed on the side surface is sufficiently larger than the resistance of the channel formed on the main surface of the poly-Si film, which is not substantially a problem. Therefore, according to the present embodiment, as in the first embodiment, the occurrence of parasitic channels can be prevented and the element reliability can be improved.
[0026]
In the present embodiment, the element isolation insulating film 24 is formed only in the periphery of the semiconductor pattern and does not exist in the light transmission region of the display region, so that the oxidation is insufficient and SiOx (X <2). It is possible to use an element isolation insulating film whose light transmittance is not sufficiently high. Complete SiO with high transmittance for low temperature oxidation ₂ In order to form a film, long-time oxidation is required. The structure of the present invention can be formed in a relatively short oxidation time, but a suboxide film having a sufficiently low transmittance can be used as an element isolation insulating film, so that higher manufacturing efficiency can be achieved.
[0027]
(Embodiment 3)
FIG. 7 is a plan view of a thin film transistor (TFT) used in the liquid crystal display device of the third embodiment of the present invention. The left side of FIG. 7 is a p-type TFT used for a CMOS peripheral drive circuit, the center of FIG. 7 is an n-type TFT used for a CMOS peripheral drive circuit, and the right side of FIG. 7 is an n-type used for a TFT matrix of an image display unit. It is a top view of TFT.
[0028]
The configuration of this embodiment is similar to that of the second embodiment, but is characterized in that the element isolation insulating film 24 is provided only in the vicinity of the portion where the intrinsic poly-Si film 30 and the gate insulating film 20 intersect. . The width of the element isolation insulating film 24 is 3 μm. A cross-sectional view taken along the line indicated by reference sign GG ′ in FIG. 7 is substantially the same as FIG. The generation of the parasitic channel is a problem at the side surface of the portion where the intrinsic poly-Si and the gate insulating film intersect. Therefore, even with such a configuration, the effect is not different from the first and second embodiments. . Further, in this embodiment, the element isolation insulating film 24 is formed only in the periphery of the semiconductor pattern and does not exist in the light transmission region of the display region, so that the oxidation is insufficient and SiOx (X <2). It is possible to use an element isolation insulating film whose light transmittance is not sufficiently high. Complete SiO with high transmittance for low temperature oxidation ₂ In order to form a film, long-time oxidation is required. The structure of the present invention can be formed in a relatively short oxidation time, but a suboxide film such as SiOx (X <2) that does not have a sufficiently high transmittance can be used as an element isolation insulating film. Efficiency can be achieved.
[0029]
(Embodiment 4)
FIG. 8 shows an equivalent circuit of the entire display device in which the peripheral drive circuit is integrated on the same substrate together with the TFT active matrix. An active matrix section 50 made of the TFT of the present invention, a vertical scanning circuit 51 made of the TFT of the present invention for driving the active matrix section, and a video signal for one scanning line are divided into a plurality of blocks and supplied in a time-sharing manner. Each of the horizontal scanning circuit 53, data signal lines Vdr1, Vdg1, Vdb1,... For supplying the video signal Data, and a switch matrix circuit 52 for supplying the video signal to the active matrix side for each divided block.
[0030]
9 and 10 are a plan view and a cross-sectional view of a unit pixel of the active matrix portion 50 of this embodiment. A cross-sectional structure taken along an alternate long and short dash line indicated by reference numeral XX ′ in FIG. 9 corresponds to FIG. The structure of the TFT is the same as that of the first embodiment shown in FIG. The unit pixel of the active matrix portion 50 includes a gate electrode 10 formed on a glass substrate, a drain electrode 12 formed so as to intersect with the gate electrode 10, a TFT formed near the intersection of these electrodes, and the TFT The pixel electrode 14 is connected to the source electrode 13 through a contact hole TH2 provided in the protective insulating film 23. The other end of the pixel electrode 14 is connected to the capacitor electrode 15 through a contact hole TH 2 provided in the protective insulating film 23, and the capacitor electrode 15 forms an additional capacitor with the adjacent gate electrode 10.
[0031]
The vertical scanning circuit 51 and the horizontal scanning circuit 53 shown in FIG. 8 are composed of shift registers and buffers, and are driven by clock signals CL1, Cl2, and CKV. The shift register takes the timing with the two-phase clocks (Vcp1, Vcp2) and the inverted clocks (Vcp1, Vcp2), inverts and shifts the input voltage, and transfers it to the buffer. At the same time, this becomes the input voltage of the shift register corresponding to the next scanning line. The buffer outputs a pulse voltage having a predetermined value, which becomes a scanning voltage of the active matrix unit 50.
[0032]
By using the TFT of the embodiment of the present invention for the active matrix unit 50 and the drive circuit unit, a highly reliable display device without image quality deterioration can be configured, but it can also be used only for the drive circuit unit or the active matrix unit 50.
[0033]
FIG. 11 is a schematic cross-sectional view of a liquid crystal cell of a liquid crystal display device according to an embodiment of the present invention. The gate electrode 10 and the drain electrode 12 are formed in a matrix on the lower glass substrate 1 with the liquid crystal layer 506 as a reference, and the pixel electrode 14 made of ITO is driven through the TFT formed in the vicinity of the intersection. . On the counter glass substrate 508 facing the glass substrate 1 with the liquid crystal layer 506 interposed therebetween, a counter electrode 510 made of ITO, a color filter 507, a color filter protective film 511, and a light shielding film 512 for forming a light shielding black matrix pattern. Is formed. The polarizing plates 505 are formed on the outer surfaces of the pair of glass substrates 1 and 508, respectively. The liquid crystal layer 506 is sealed between a lower alignment film ORI1 that sets the orientation of liquid crystal molecules and an upper alignment film ORI2, and is sealed by a sealing material SL (not shown). The lower alignment film ORI1 is formed on the protective insulating film 23 on the glass substrate 1 side. On the inner surface of the counter glass substrate 508, a light shielding film 512, a color filter 507, a color filter protective film 511, a counter electrode 510, and an upper alignment film ORI2 are sequentially stacked. This liquid crystal display device is assembled by separately forming layers on the glass substrate 1 side and the counter glass substrate 508 side, and then overlaying the upper and lower glass substrates 1 and 508 and enclosing the liquid crystal 506 therebetween. A TFT-driven color liquid crystal display device is configured by controlling the transmission of light from the backlight BL at the pixel electrode 14 portion. By using the above-described semiconductor element of the embodiment of the present invention as the TFT for driving the pixel electrode 14 and the TFT for the driving circuit for driving the pixel electrode 14, a highly reliable and high image quality TFT transmission type liquid crystal display device is realized. it can.
[0034]
Since this embodiment is a transmissive liquid crystal display device, light is transmitted through the element isolation insulating film 24. For this reason, the element isolation insulating film 24 requires a sufficiently high light transmittance. Practically, it is sufficient to have a transmittance of 95% or more in the visible region. The element structure of the present invention can be applied not only to a transmissive liquid crystal display device but also to a reflective liquid crystal display device. In FIG. 11, a reflective liquid crystal display device can be realized by using a metal electrode with high reflectivity such as Al instead of ITO for the pixel electrode 14 and removing the polarizing plate 505 and the backlight BL at the bottom of the glass substrate 1. . However, in this case, since light does not transmit through the element isolation insulating film 24, the light transmittance of the element isolation insulating film does not matter. In view of the requirement that the leakage current between elements is sufficiently low, an insulating film with low transmittance can be used.
[0035]
(Embodiment 5)
A manufacturing process of the TFT of the embodiment shown in FIG. 1 will be described with reference to FIGS. The left side of FIGS. 12 to 17 shows the p-type TFT used in the drive circuit, and the right side of FIGS. 12 to 17 shows the manufacturing process of the n-type TFT in the drive circuit. Since the n-type TFT used in the active matrix display unit 50 has the same structure, it is not shown here.
[0036]
As shown in FIG. 12, on the alkali-free glass substrate 1 having a strain point of 670 ° C., SiO serving as a buffer insulating film ₂ A buffer layer 21 made of a film is deposited with a thickness of 300 nm by plasma CVD, and then an amorphous Si (a-Si) film is deposited with a thickness of 55 nm by plasma CVD. The buffer insulating film is SiO ₂ In addition to Si _Three N _Four Etc. can also be used. Si _Three N _Four By using, diffusion of impurities such as Na from the glass substrate 1 can be more effectively suppressed. Further, a low pressure CVD method or a sputtering method may be used to form the a-Si film. Next, the a-Si film is irradiated with XeCl excimer laser light (wavelength 308 nm) and recrystallized to obtain a polycrystalline Si (poly-Si) film 30.
[0037]
Next, as shown in FIG. 13, a photoresist pattern PR having a predetermined shape is formed on the poly-Si film by a known photolithography method. Next, phosphorus ions are implanted into the poly-Si film using the photoresist pattern PR as a mask. For the implantation, a non-mass separation type ion implantation apparatus is used, and 1% PH diluted with He is used. _Three Ions containing phosphorus extracted from the gas plasma are accelerated at an acceleration voltage of 5 kV and an implantation amount of 5 × 10 ¹⁶ (cm ^-2 ). Here, the implantation amount is the total ion amount calculated from the product of the ion current and implantation time, and the ion density of P is about 1/3 of this.
[0038]
Next, as shown in FIG. 14, the substrate surface is left O with the photoresist pattern PR remaining. ₂ By exposing to plasma, the poly-Si film implanted with phosphorus is oxidized and converted into a phosphorus glass (PSG) film to form an element isolation insulating film 24. As a result, the poly-Si film pattern that will later become a TFT can be separated without etching. As impurities to be implanted, boron other than phosphorus may be used, or both phosphorus and boron may be used. In this case, the element isolation insulating films 24 to be formed are a boron glass (BSG) film and a boron phosphorus glass (BPSG) film, respectively. Usually O ₂ Since the oxidation rate of Si by plasma is very slow at a low temperature of 150 ° C. or lower where a photoresist can be used, and the oxide film thickness to be formed is limited, all the poly-Si film 30 is oxidized to be an insulator. Is impossible. However, as in this embodiment, the poly-Si film is preliminarily 1 × 10 ¹⁶ (cm ^-2 The inventors have found that by implanting a large amount of impurities as described above, the oxidation rate is increased, and the entire poly-Si film is oxidized even at room temperature. This enables element isolation by oxidation even at a low temperature at which a glass substrate can be used. In addition to the method using plasma, the oxidation method may be anodized in a solution.
[0039]
Next, as shown in FIG. 15, SiO which becomes a gate insulating film by plasma CVD is used. ₂ The film 20 is deposited to 70 nm, and Nb is deposited to 250 nm by sputtering. With the structure of the present invention, as can be seen from FIG. 15, the surface on which the gate insulating film 20 is formed is a flat surface, and does not have the end portion of the pattern and the contact portion. Therefore, even a film having inferior step coverage can be used as the gate insulating film. In plasma CVD, it is possible to select a condition that densifies the film by increasing ion bombardment on the film surface with higher power and lower gas pressure. Furthermore, since high-density plasma CVD methods such as ECR plasma CV and helicon plasma CVD can be used, higher quality SiO ₂ Films can be formed at low temperatures. This contributes to improving the reliability of the element.
[0040]
Next, as shown in FIG. 16, after patterning the gate electrode 10 into a predetermined shape, a method of forming a predetermined photoresist pattern and implanting ions is repeated, whereby a high resistance n-type poly-Si layer 33, a low resistance is formed. An n-type poly-Si layer 31 and a low-resistance p-type poly-Si layer 32 are formed. The amount of phosphorus injected into the high resistance n-type poly-Si layer 33 is 1E. ¹⁴ (cm ^-2 ), The amount of phosphorus injected into the low resistance n-type poly-Si layer 31 is 1E. ¹⁵ (cm ^-2 ), The amount of boron implanted into the low resistance p-type poly-Si layer 31 is 1E. ¹⁵ (cm ^-2 And a mass separation type ion implantation apparatus was used. Next, the impurities are activated by heat-treating the substrate at 450 ° C. for 5 minutes. The implanted impurity is activated. As the impurity activation method, a rapid thermal annealing (RTA) method using a lamp can be used in addition to a normal heat treatment.
[0041]
Next, as shown in FIG. 17, the SiO 2 that becomes the interlayer insulating film 22 by plasma CVD is used. ₂ A film is deposited to 400 nm and a contact hole is opened. Next, a three-layer film made of Ti / Al / Ti is deposited by sputtering to a thickness of 500 nm and patterned into a predetermined shape to obtain the source electrode 13 and the drain electrode 12.
[0042]
Next, as shown in FIG. 18, Si which becomes the protective insulating film 23 by the plasma CVD method. _Three N _Four Is deposited to 500 nm and a contact hole (not shown) is opened. Finally, an ITO film is deposited to a thickness of 70 nm by sputtering and patterned into a predetermined shape to obtain a pixel electrode 14 (not shown).
[0043]
According to the present embodiment, a highly reliable TFT at a low temperature can be manufactured on an inexpensive glass substrate, so that the reliability of the liquid crystal display device can be improved and the manufacturing cost can be reduced.
[0044]
(Embodiment 6)
In the above embodiment, impurities are introduced into the Si film in advance to oxidize the poly-Si film at a low temperature. However, it is not always necessary to introduce impurities unless a photoresist is used as a mask. Hereinafter, such an embodiment will be described with reference to FIGS.
[0045]
As shown in FIG. 18, SiO 1 serving as a buffer insulating film is formed on a glass substrate 1 made of alkali-free glass having a strain point of 670 ° C. ₂ A buffer layer 21 made of a film is deposited by 300 nm by plasma CVD, and subsequently an amorphous Si (a-Si) film 301 is deposited by 55 nm by plasma CVD. Furthermore, Si is formed on a-Si by plasma CVD. _Three N _Four A film 25 is formed to a thickness of 35 nm and patterned into a predetermined shape.
[0046]
Next, as shown in FIG. 19, the substrate is heated to 350.degree. ₂ Patterned Si by exposure to plasma _Three N _Four The element isolation insulating film 24 is formed by oxidizing the a-Si film not covered with the film 25. Since the Si film has a higher oxidation rate than the poly-Si film, the entire film can be oxidized by heating the substrate without introducing impurities.
[0047]
Next, as shown in FIG. 20, patterned Si _Three N _Four With the film 25 left, XeCl excimer laser light (wavelength 308 nm) is irradiated so as to scan in the direction of the arrow in the figure, the a-Si film 301 is recrystallized, and an intrinsic poly-Si film made of polycrystalline Si Get 30. Patterned intrinsic Si _Three N _Four Since the unevenness of the surface of the intrinsic poly-Si film 30 formed by leaving the film 25 on the a-Si film and irradiating with the laser is suppressed, the intrinsic poly-Si film 30 having a flatter surface is obtained. Can do.
[0048]
Hereinafter, the steps after the step of forming the gate insulating film and the gate electrode are the same as those in the above-described embodiment, and therefore will be omitted.
[0049]
According to this embodiment, a flatter poly-Si film can be formed by using a mask for selective oxidation as it is as a protective film during laser annealing. In particular, by reducing the unevenness of the poly-Si film to 10 nm or less, a dense and high-quality oxide film can be used as the gate insulating film although the step coverage is inferior, so that the withstand voltage of the gate insulating film can be improved. Therefore, it is possible to improve the reliability of the liquid crystal display device and reduce the manufacturing cost.
[0050]
In the embodiment, an alkali-free glass substrate having a strain point (strain point temperature) of 670 ° C. is used, but the strain point temperature is not limited to 670 ° C. Since the process temperature for forming the TFT is about 450 ° C. or lower, any process that can withstand it is acceptable. Therefore, it is desirable to use a glass substrate that can withstand a process temperature of 450 ° C. at a strain point temperature of about 500 ° C. or more and about 720 ° C. or less. The cost of the glass substrate can be reduced. Since the glass substrate having a lower strain point temperature can be used as much as the process temperature is lowered, the cost of the glass substrate can be further reduced. According to the above embodiment, since a highly reliable TFT without a parasitic channel on the side surface of the Si pattern can be formed at a low temperature, a liquid crystal display device free from image quality deterioration can be manufactured at low cost.
[0051]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the liquid crystal display device which has an element structure which can solve the subject of the limit of the reliability and performance improvement which TFT which has a side wall in an active layer can provide can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a thin film transistor used in a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a plan view of a thin film transistor used in the liquid crystal display device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a thin film transistor used in the liquid crystal display device according to the first embodiment of the present invention.
FIG. 4 is a plan view of a thin film transistor used in a liquid crystal display device according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view of a thin film transistor used in a liquid crystal display device according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view of a thin film transistor used in a liquid crystal display device according to a second embodiment of the present invention.
FIG. 7 is a plan view of a thin film transistor used in a liquid crystal display device according to a third embodiment of the present invention.
FIG. 8 is an overall configuration diagram of a liquid crystal display device according to a third embodiment of the present invention.
FIG. 9 is a plan view of a pixel of a liquid crystal display device according to a third embodiment of the present invention.
FIG. 10 is a cross-sectional view of a pixel of a liquid crystal display device according to a sixth embodiment of the present invention.
FIG. 11 is a cell cross-sectional view of a liquid crystal display device according to an embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a manufacturing process of a thin film transistor used in the liquid crystal display device according to the first example of the present invention.
FIG. 13 is a cross-sectional view showing a manufacturing process of a thin film transistor used in the liquid crystal display device according to the first embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing process of a thin film transistor used in the liquid crystal display device according to the first example of the present invention.
FIG. 15 is a cross-sectional view showing a manufacturing process of a thin film transistor used in the liquid crystal display device according to the first example of the present invention;
FIG. 16 is a cross-sectional view showing a manufacturing process of a thin film transistor used in the liquid crystal display device according to the first example of the present invention.
17 is a cross-sectional view showing a manufacturing process of a thin film transistor used in the liquid crystal display device according to the first example of the invention. FIG.
FIG. 18 is a cross-sectional view showing another manufacturing process of the thin film transistor used in the liquid crystal display device according to the first example of the present invention;
FIG. 19 is a cross-sectional view showing another manufacturing process of the thin film transistor used in the liquid crystal display device according to the first example of the present invention.
FIG. 20 is a cross-sectional view showing another manufacturing process of the thin film transistor used in the liquid crystal display device according to the first example of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 10 ... Gate electrode, 12 ... Drain electrode, 13 ... Source electrode, 14 ... Pixel electrode, 15 ... Capacitance electrode, TH, TH1, TH2 ... Contact hole, 20 ... Gate insulating film, 21 ... Buffer layer, 22 ... Interlayer insulating film, 23 ... Protective insulating film, 24 ... Element isolation insulating film, 25 ... Si _Three N _Four Film 301... A-Si film 30... Intrinsic poly-Si film 31... Low resistance n-type poly-Si layer 32... Low resistance p-type poly-Si layer 33. 51: vertical scanning circuit, 53: horizontal scanning circuit, 52: switch matrix circuit.

Claims (14)

A liquid crystal display device having a pair of substrates, at least one of which is transparent, and a liquid crystal layer sandwiched between the substrates,
A plurality of semiconductor thin film patterns and a silicon oxide film formed on a main surface of one of the pair of substrates; and a first electrode opposed to at least a part of the plurality of semiconductor films via a gate insulating film; A pair of semiconductor layers having a first conductivity type or a second conductivity type formed in a part of the semiconductor film;
Second and third electrodes formed so as to be in contact with the pair of semiconductor layers, and the side surfaces of the plurality of semiconductor films are covered with a silicon oxide film different from the gate insulating film A characteristic liquid crystal display device. A liquid crystal display device having a pair of substrates, at least one of which is transparent, and a liquid crystal layer sandwiched between the substrates,
A plurality of semiconductor thin film patterns and a silicon oxide film formed on a main surface of one of the pair of substrates; and a first electrode opposed to at least a part of the plurality of semiconductor films via a gate insulating film; A pair of semiconductor layers having a first conductivity type or a second conductivity type formed in a part of the semiconductor film, and second and third electrodes formed to be in contact with the pair of semiconductor layers; Have
The liquid crystal display device, wherein side surfaces of the plurality of semiconductor thin film patterns are in contact with the silicon oxide film . A liquid crystal display device having a pair of substrates, at least one of which is transparent, and a liquid crystal layer sandwiched between the substrates,
A plurality of semiconductor films and a silicon oxide film formed on a main surface of one of the pair of substrates; a first electrode opposed to at least a part of the plurality of semiconductor films via a gate insulating film; A pair of semiconductor layers having a first conductivity type or a second conductivity type formed in a part of the semiconductor film, and second and third electrodes formed to be in contact with the pair of semiconductor layers. And at least a portion of the plurality of semiconductor films that intersects the first electrode is in contact with the silicon oxide film and is not in contact with the gate insulating film. The liquid crystal display device according to any one of claims 1 to 3,
The one substrate is a glass substrate having a strain point of 720 ° C. or lower. The liquid crystal display device according to any one of claims 1 to 3,
2. The liquid crystal display device according to claim 1, wherein the thickness of the silicon oxide film does not exceed 1.2 times the thickness of the semiconductor film. In the liquid crystal display device according to any one of claims 1 to 5, wherein the silicon oxide film, a liquid crystal display device, characterized in that those containing phosphorus or boron or both.   7. The liquid crystal display device according to claim 1, wherein the unevenness of the main surface of the plurality of semiconductor patterns is 10 nm or less at the maximum.   7. The liquid crystal display device according to claim 1, wherein the gate insulating film has a thickness of 50 nm or less.   7. The liquid crystal display device according to claim 1, wherein a main surface of the one substrate is covered with a silicon nitride film. A method for producing a liquid crystal display device having a pair of transparent substrates at least one and having a liquid crystal layer sandwiched between the substrates,
Forming a semiconductor film over substantially the entire main surface of one of the pair of substrates;
Selectively introducing phosphorus or boron or both into a predetermined region of the semiconductor film;
Oxidizing a predetermined region of the semiconductor film introduced with phosphorus or boron or both to form an insulating film, and separating the semiconductor film into a plurality of semiconductor patterns;
A method of manufacturing a liquid crystal display device, comprising at least a step of forming a gate insulating film on the plurality of semiconductor patterns and an insulating film into which phosphorus or boron or both are introduced. A method for producing a liquid crystal display device having a pair of transparent substrates at least one and having a liquid crystal layer sandwiched between the substrates,
Forming a semiconductor film over substantially the entire main surface of one of the pair of substrates;
Separating the semiconductor film into a plurality of semiconductor patterns having a predetermined shape by etching;
Selectively introducing phosphorus or boron or both into the pattern edge of the semiconductor pattern;
Oxidizing the end of the semiconductor pattern into which phosphorus or boron or both are introduced to form an insulating film;
And a step of forming a gate insulating film on the semiconductor pattern. In the manufacturing method of the liquid crystal display device in any one of Claim 9 thru | or 11,
The method for manufacturing a liquid crystal display device, wherein phosphorus or boron has an acceleration energy of less than 10 keV, and an injection amount is 1E ¹⁶ (cm ⁻² ) or more in terms of area density. In the manufacturing method of the liquid crystal display device in any one of Claim 9 thru | or 11,
A method for manufacturing a liquid crystal display device, wherein the semiconductor into which phosphorus or boron or both are oxidized is oxidized to form an insulating film by exposure to a plasma containing oxygen at a temperature of 450 ° C. or lower. In the manufacturing method of the liquid crystal display device in any one of Claim 9 thru | or 11,
A method of manufacturing a liquid crystal display device, characterized by oxidizing the semiconductor into which phosphorus or boron or both are introduced into an insulating film by anodizing in a solution.

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