JPH02284472A - Thin film transistor - Google Patents

Abstract

PURPOSE:To obtain an excellent semiconductor by forming a polycrystalline Si film and a thin SiC film thereon, obtaining a low resistance layer of source.drain in only the SiC film, and constituting a buried channel structure and a wide gap drain.source structure. CONSTITUTION:An active layer on a glass substrate 1 is constituted of polycrystalline Si carbide film 3. A gate insulating film 4 and a gate electrode 5 are formed in a gate electrode pattern. By ion implantation using the gate electrode 5 as a mask, a shallow source-drain region is formed in the polycrystalline Si carbide film in the self alignment manner. After a passivation film 6 is formed, a contact hole is formed, and a source-drain electrode 7 is formed. Thereby field effect mobility is increased, OFF-current is decreased, leak current is reduced, and high breakdown strength is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor formed on an insulating substrate by a low-temperature process with high mobility, high breakdown voltage, and low leakage current.

[Conventional technology]

In recent years, research into the technology of fabricating thin-film active devices on glass substrates has been intensified, with the aim of applying it to a variety of applications, including large-area transmission type liquid crystal displays and contact type image sensors. Among them, a can form a film uniformly over a large area.
-3i:H is already being applied at the product level. However, a-8i:H has a very low mobility, which limits its field of application. In other words, it can be applied as optical sensors and switching devices, but if you try to simultaneously create peripheral circuits to drive these devices, the required speed will be low because the mobility is about 1/1000 of that of single crystal silicon. It is not possible to manufacture a drive circuit for Currently, such drive circuits are fabricated on silicon wafers and connected to thin film devices by wire bonding.

However, from the viewpoint of manufacturing costs and wiring yields, it will be necessary to make all the films thinner in the future. This requires a means to fabricate a high-mobility thin film on a glass substrate.

Recently, it has become possible to obtain single crystal silicon on a glass substrate. However, this requires a fairly high-temperature process, and other parts, including the glass substrate, are exposed to high temperatures. As a result, the glass substrate used has to be made of a material with high heat resistance, and problems such as damage to other parts arise. Therefore, research is being conducted in various places to create thin film active devices with uniformly high mobility using low-temperature processes. As one of these, research and development is being conducted on polycrystalline silicon thin film transistors (TPT).

FIG. 5 shows the structure of a conventional planar thin film transistor. First, a gate insulating film 4. After forming the gate electrode 5, the gate electrode is patterned. Thereafter, ion implantation or laser doping is performed using the gate electrode 5 as a mask, followed by metal wiring to form the source/drain electrodes 7. Furthermore, by making the thin film semiconductor layer (polycrystalline silicon film) 2, which serves as the active layer, ultra-thin to 500 Å or less, the performance of the transistor has been significantly improved, and recently, the field effect mobility has been improved to 1.00 c at low temperatures.
Performance of nf/V,s or higher can now be obtained.

[Problem to be solved by the invention]

In a normal planar structure thin film transistor, a channel is formed between the active layer and the gate insulating film layer, and carriers propagate through this channel. Here, manufacturing polycrystalline silicon oxide films usually requires a low-temperature process, so
A silicon oxide film formed by CVD or the like is used as the gate insulating film.

However, the quality of this insulating film is poorer than that of the thermal oxide film normally used in the Sz process, and the level density at the interface is particularly high. For this reason, there is a large amount of scattering at the interface, which is caused by TPT.
This is one of the factors that limits the performance of Furthermore, polycrystalline silicon TPTs have a problem in that they have a higher leakage current than normal MO3 field effect transistors (MOSFETs) or amorphous silicon FETs. A large amount of leakage current is a problem both in liquid crystal switcher devices and in manufacturing drive circuits. In particular, since there are many applications for driving devices that require high voltage such as liquid crystals and EL, devices with high breakdown voltage and low leakage current are required. However, ordinary planar polycrystalline silicon TPTs have a problem in that leakage current increases rapidly, especially when a high electric field is applied.

An object of the present invention is to obtain a device structure that is improved in terms of withstand voltage and leakage current without causing deterioration in controllability of the number of steps, mobility, and threshold value.

[Means to solve the problem]

The gist of this invention is a thin film semiconductor layer and a gate insulating film layer provided on an insulating substrate.

In a thin film transistor consisting of a gate electrode and an O, source, and drain electrode, the thin film semiconductor layer is a two-layer film consisting of a polycrystalline silicon film and a thin SiC film (silicon carbide film). This thin film transistor is characterized in that it has a buried channel structure and a wide gap drain/source structure by forming source/drain low resistance layers only in the SiC film.

[Effect]

When the active layer of TPT is composed of a two-layer film of polycrystalline silicon and silicon carbide (SiC), the band gap of silicon carbide is larger than that of silicon. A channel is formed at the film/semiconductor device interface, but in this invention, the channel is formed not at the gate insulating film/semiconductor interface, but at the polycrystalline silicon/silicon carbide interface (see Figure 2).
a)). Therefore, it is possible to manufacture a TPT with high mobility because it is not affected by the gate insulating film interface. Since the polycrystalline silicon/silicon carbide interface can be easily formed by continuous film formation, a good interface can be obtained. In addition, this TPT has the advantage that it is effective in reducing leakage current because the low resistance layers of the source and drain are formed using a SiC film (silicon carbide film) having a large band gap. This will be discussed in detail next.

In conventional planar TPTs, when a voltage is applied between the source and drain, a high electric field is applied to the drain end.
The field emission current between the band gaps at this point causes leakage current.

Here, in polycrystalline silicon, such leakage current between bands is small, so it usually does not pose a problem.

However, in polycrystalline silicon, there are many grain boundary traps in the band gap, and leakage current between bands easily flows through these traps (see Figure 3 (b). As a result, leakage current increases rapidly when high voltage is applied. is observed.Such leakage current is unavoidable in polycrystalline silicon due to its nature.Moreover, this current depends on the electric field applied between the depletion layers at the drain end.According to the structure of the present invention, , 3rd
As shown in the band diagram shown in Figure (a), a SiC film with a large band gap is used for the portion forming the depletion layer at the end of the train. Therefore, leakage current, which is teno emission current, can be suppressed through the trap level. Since the emission current depends on the gap exponentially, it can be significantly reduced by slightly widening the gap.

〔Example〕

The invention will now be described in detail with reference to embodiments shown in the accompanying drawings. FIG. 1 is a structural diagram showing an embodiment of the present invention. The active layer of the glass substrate 1''2 is composed of a polycrystalline silicon film 2 and a polycrystalline silicon carbide film 3. Thereafter, a gate insulating film 4° and a gate electrode 5 are formed into a gate electrode pattern, and shallow source/drain regions (
(not shown) was formed in a polycrystalline silicon carbide film. After forming the passivation film 6, contact holes were formed and source/drain electrodes 7 were formed.

Figure 4 shows the characteristics of the actually manufactured thin film transistor. It shows the change in drain current due to gate voltage.

The solid line shows the TPT manufactured according to the present invention, and the broken line shows the characteristics of the TPT manufactured using the conventional method. In this way, it was found that the field effect mobility was high, the off-state current was reduced, and the leakage current was greatly improved. In the conventional planar structure thin film transistor (TPT),
Although a rapid increase in leakage current is observed as the drain voltage increases, such a rapid increase in leakage current is not observed in the TPT according to the present invention. In particular, a significant improvement in leakage current was obtained under high voltage driving. The breakdown voltage is 30V or more, and the leakage current is 1o-10 or less even when a voltage of 30V is applied. As a result, a TPT with higher mobility, higher withstand voltage, and lower leakage current than conventional TPT was created.

〔Effect of the invention〕

As described in detail above, the thin film transistor according to the present invention could be manufactured through simple steps and with good reproducibility. This structure also made it possible to obtain a thin film transistor with high breakdown voltage, low leakage current, and high-speed operation.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. 2 and 3 are diagrams comparing the band diagrams of the channel and drain ends of the structure according to the present invention and the conventional structure, respectively, and FIG. 4 is a diagram showing the characteristics of the transistor manufactured according to the present invention. FIG. 5 is a diagram showing the structure of a conventional polycrystalline thin film transistor. 1...Glass substrate, 2...Semiconductor layer (
polycrystalline silicon film), 3...semiconductor layer p (Si
C film), 4...gate insulating film, 5...
Gate electrode, 6...passivation film, 7.
·····electrode. Agent: Susumu Uchihara, patent attorney (fl)

Claims (1)

[Claims] From the thin film semiconductor layer provided on the insulating substrate, the gate insulating film layer on the thin film semiconductor layer, the gate electrode on the gate insulating film, and the source/drain electrodes connected to the source/drain regions in the thin film semiconductor layer. In the constructed thin film transistor, a two-layer film consisting of a polycrystalline silicon film and a thin SiC (silicon carbide film) film on top of the polycrystalline silicon film is used as the thin film semiconductor layer, and low resistance layers of the source and drain are formed using S.
A thin film transistor characterized in that it has a buried channel structure and a wide gap drain and source structure by being formed only in an iC film.