CN100373633C

CN100373633C - Asymmetric Thin Film Transistor Structure

Info

Publication number: CN100373633C
Application number: CNB031545874A
Authority: CN
Inventors: 陈坤宏
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2003-08-20
Filing date: 2003-08-20
Publication date: 2008-03-05
Anticipated expiration: 2023-08-20
Also published as: CN100481515C; CN1585137A; CN101118930A

Abstract

The present invention provides an asymmetric thin film transistor structure, which includes a substrate, a semiconductor layer and a gate disposed on the substrate. The semiconductor layer includes a first lightly doped region and a first heavily doped region disposed on one side of the gate, and a second lightly doped region and a second heavily doped region disposed on the other side of the gate. A first interface is included between the first lightly doped region and the first heavily doped region, and a second interface is included between the second lightly doped region and the second heavily doped region, and the spacing between the first interface and a first gate sidewall adjacent thereto is not equal to the spacing between the second interface and a second gate sidewall adjacent thereto.

Description

Asymmetric thin-film transistor structure

Technical field

(thin film transistor, TFT) structure refer to a kind of LCD (liquid crystal display, asymmetric thin-film transistor structure LCD) especially to the invention provides a kind of asymmetric thin-film transistor.

Background technology

The active layer of thin-film transistor is made up of semi-conducting material, and high electron mobility can be provided, and therefore has been widely used in the various functional circuit design.For example, Thin Film Transistor-LCD (TFT-LCD) has used a large amount of thin-film transistors in two big functional circuit designs such as its image element circuit and peripheral drive circuit.Because the function of image element circuit and peripheral drive circuit and operational circumstances are also inequality, so its tft characteristics demand separately also is not quite similar.Aspect image element circuit, because thin-film transistor mainly is intended for the switch element of pixel, the anglec of rotation that provides suitable voltage to control liquid crystal molecule, so its special reduction leakage current (off-current) that needs are to keep the electric charge that is stored in the pixel storage capacitor.

Please refer to Fig. 1, Fig. 1 is the generalized section of an existing thin-film transistor structure.Thin-film transistor 10 includes a substrate 12, and semi-conductor layer 14 is located at substrate 12 surfaces, and a gate insulator 16 is located at semiconductor layer 14 surfaces, and a grid 18 is located at gate insulator 16 surfaces.Semiconductor layer 14 includes two lightly doped drains, and (lightly doped drain, LDD) 20,22 and two source/

drains

24,26 are symmetrically set in the both sides of grid 18, then are defined as a channel region 28 between the lightly doped

drain

20 and 22.

The light doping section that lightly doped

drain

20 and 22 utilizes N type dopant to form is used for reducing the leakage current of thin-film transistor 10, and near the too high thermoelectronic effect that causes of electric field avoiding draining.Yet be subjected to the lower influence of doping content, lightly doped

drain

20 and 22 resistance also relatively are higher than the source/

drain

24 and 26 of both sides, therefore cause the series resistance of 24,26 of drain electrode and source electrodes to increase easily, and then produce problems such as electron mobility and the reduction of whole element operating rate.In this case, desire is improved the leakage phenomenon of thin-film transistor, must sacrifice the operating rate of element just unavoidablely, therefore how in electron mobility and two kinds of element characteristics of leakage current, accept or reject, a significant consideration when just becoming the design ldd structure.

Please refer to Fig. 2 to Fig. 5, Fig. 2 to Fig. 5 shows the graph of relation of the length of lightly doped drain for starting voltage, electron mobility and the leakage current of thin-film transistor element characteristics such as (near the electric current I d the drain electrode of flowing through when comprising the electric current I off that records when transistor is closed or the work of transistor reverse biased) respectively.Shown in each curve chart, when increasing progressively between in 0 to 3 micron of the length of the lightly doped drain 20 of channel region both sides and 22, the starting voltage value Vt of thin-film transistor can increase thereupon, and electron mobility can decrease, and leakage current Ioff or Id also can decrease.By above-mentioned curve chart as can be known, when adjusting the length of lightly doped drain, still be difficult to take into account simultaneously two kinds of element characteristics of electron mobility and leakage current, can't effectively improve the electrical property of element.

Summary of the invention

Therefore, purpose of the present invention promptly in that a kind of asymmetric thin-film transistor structure is provided, can be improved problems such as electron mobility and leakage current simultaneously.

In a preferred embodiment of the invention, this thin-film transistor structure includes a substrate; Semi-conductor layer is located on this substrate, this semiconductor layer includes a channel region, one first light doping section and one first heavily doped region are located at a side of this channel region, one second light doping section and one second heavily doped region are located at the opposite side of this channel region, and wherein include one first interface between this first light doping section and this first heavily doped region, include a second contact surface between this second light doping section and this second heavily doped region; And one grid be located on this substrate, this grid includes a first side wall and one second sidewall, and wherein spacing and the spacing between this second sidewall and this second contact surface between this first side wall and this first interface is unequal.

Because thin-film transistor structure of the present invention includes asymmetric light doping section (lightly doped drain), therefore can moderately increase the length of lightly doped drain, with effective reduction leakage current further in drain electrode one side comparatively responsive to leakage problem.In addition, the present invention can also further shorten the length of lightly doped drain in source electrode one side, even remove the ldd structure of source side fully, with the series resistance between effective reduction drain electrode and source electrode, improve the operating rate of electron mobility and whole element.

Description of drawings

Fig. 1 is the generalized section of an existing thin-film transistor structure;

Fig. 2 is the graph of relation of the starting voltage and the LDD length of a thin-film transistor;

Fig. 3 is the graph of relation of the electron mobility and the LDD length of a thin-film transistor;

Fig. 4 is the leakage current of a thin-film transistor and the graph of relation of LDD length;

Fig. 5 is the leakage current comparison diagram with thin-film transistor of Different L DD length;

Fig. 6 is the generalized section of a thin-film transistor structure of first embodiment of the invention;

Fig. 7 to Fig. 9 makes the method schematic diagram of a thin-film transistor for the present invention;

Figure 10 is the generalized section of a thin-film transistor structure of second embodiment of the invention;

Figure 11 is the generalized section of a thin-film transistor structure of third embodiment of the invention;

Figure 12 is of the present invention one single its leakage current comparison diagram of LDD structural membrane transistor AND gate a pair of LDD structural membrane transistor.

Description of reference numerals

10 thin-film transistors, 12 substrates

14 semiconductor layers, 16 gate insulators

18 grids, 20 lightly doped drains

22 lightly doped drains, 24 source/drains

26 source/drains, 28 channel regions

30 thin-film transistors, 32 substrates

34 semiconductor layers, 36 gate insulators

38 grids, 40 lightly doped drains

42 lightly doped drains, 44 source/drains

46 source/drains, 48 channel regions

49, the interface of 50 lightly doped drains and source/drain interpolar

51,52 gate lateral walls

54,56 screens

A, A ' grid central point (or raceway groove central point) are to the distance of gate lateral wall

B, B ' lightly doped drain length

C, C ' grid central point (or raceway groove central point) are to the distance at interface between lightly doped drain and source/drain

Embodiment

Please refer to Fig. 6, Fig. 6 is the generalized section of a thin-film transistor structure of first embodiment of the invention.Thin-film transistor 30 is used as the pixel switch element of a LCD, however the present invention be not limited thereto, thin-film transistor 30 also can be applicable to other associated electrical product of other circuit design of LCD.In addition, thin-film transistor 30 is N type thin-film transistors in a preferred embodiment of the invention, yet in other embodiments of the invention, thin-film transistor 30 also can be a P type thin-film transistor.Thin-film transistor 30 includes a substrate 32, and semi-conductor layer 34 is located at substrate 32 surfaces, and a gate insulator 36 is located at semiconductor layer 34 surfaces, and a grid 38 is located at gate insulator 36 surfaces.Wherein semiconductor layer 34 includes two unequal lightly doped drains 40 of length and 42, and two source/

drains

44,46 are located at the both sides of grid 38.Lightly doped

drain

40,42 and source/

drain

44,46 are N type doped region, and wherein lightly doped

drain

40 and 42 length approximately respectively between 0 to 3.5 micron.Grid 38 is made of electric conducting materials such as metal material or doped polycrystalline silicon.In addition, be defined as a channel region 48 between the lightly doped

drain

40 and 42.

Include an interface 49 between lightly doped drain 40 and the source/drain 44, include an interface 50 between lightly doped drain 42 and the source/drain 46, grid 38 then includes left and right sides wall 51 and 52.In order to illustrate further the interelement relation of thin-film transistor 30, be A with gate lateral wall 51 to the distance definition between a central point of grid 38 in the present embodiment, gate lateral wall 52 to the distance definition between the central point of grid 38 is A ', the length of lightly doped drain 40 is defined as B, the length of lightly doped drain 42 is defined as B ', interface 49 to the distance definition between the central point of grid 38 is C, interface 50 to the distance definition between the central point of grid 38 is C ', and A=A ' wherein, B ≠ B ', C=C '.

In the structure of thin-film transistor 30, the two

side

51 and 52 of grid is stacked over lightly doped

drain

40 and 42 tops respectively, that is to say that grid 38 parts are covered in lightly doped

drain

40 and 42 tops.Yet in other embodiments of the invention, the two side of grid might not all will be covered in the lightly doped drain top, and the relative position of grid and lightly doped drain interpolar can show that the electrical property design requirement is adjusted.

Please refer to Fig. 7 to Fig. 9, Fig. 7 to Fig. 9 shows the method schematic diagram of making thin-film transistor 30.As shown in Figure 7, at first provide substrate 32, and form semiconductor layer 34 in substrate 32 surfaces in regular turn, and in semiconductor layer 34 surface coverage gate insulators 36.Form a screen 54 in gate insulator 36 surfaces afterwards, be used for defining the source electrode of thin-film transistor 30 and the position of drain electrode.Carry out an ion implantation technology subsequently, in the semiconductor layer 34 of screen 54 both sides, form two N ⁺Doped region 44 ' and 46 '.

As shown in Figure 8, after removing screen 54, next form screens 56 in gate insulator 36 surfaces in addition, be used for defining the position of the lightly doped drain of thin-film transistor 30.Carry out an ion implantation technology subsequently again, in the semiconductor layer 34 of screen 56 both sides, to form two N-doped regions 40 ' and 42 ' with different length.Then as shown in Figure 9, remove screen 56, and utilize a heat treatment to activate to inject doped region 40 ', 42 ', 44 ' and 46 ' ion, to finish the making of lightly doped

drain

40,42 and source/

drain

44,46 simultaneously.Last again in the pattern of gate insulator 36 surface definition grids 38, promptly finish the making of thin-film transistor 30.

Because the present invention can utilize technologies such as little shadow and etching to come the position of explication screen 56, therefore can control the position and the length of lightly doped drain 40 and 42.In addition, the present invention also can utilize technologies such as little shadow and etching to control the relative position of 40,42 of grid 38 and lightly doped drains when the pattern of definition grid 38.

Please refer to Figure 10, Figure 10 is the generalized section of a thin-film transistor structure of second embodiment of the invention.In this embodiment, all component labellings are all identical with the asymmetric thin-film transistor structure shown in first embodiment, have only the relative position of 40,42 of grid 38 and lightly doped drains different.As shown in figure 10, grid 38 positions in the present embodiment are not symmetrical in the central point of channel region 48, but two lightly doped

drains

40 and 42 length are then for identical and be symmetrical in the central point of channel region 48 simultaneously, therefore be A with gate lateral wall 51 to the distance definition between a central point of channel region 48 in the present embodiment, gate lateral wall 52 to the distance definition between the central point of channel region 48 is A ', the length of lightly doped drain 40 is defined as B, the length of lightly doped drain 42 is defined as B ', interface 49 to the distance definition between the central point of channel region 48 is C, interface 50 to the distance definition between the central point of channel region 48 is C ', and A ≠ A ' wherein, B=B ', C=C '.

Please refer to Figure 11, Figure 11 is the generalized section of a thin-film transistor structure of third embodiment of the invention.This embodiment directly removes the lightly doped drain 42 in the asymmetric thin-film transistor shown in first embodiment, and is all identical with the asymmetric thin-film transistor structure shown in first embodiment as for other all component labellings.Generally speaking, when thin-film transistor cuts out, still have voltage (electric field) to exist between drain electrode end and the substrate, therefore be easy to generate leakage current.That is to say, the leakage problem of thin-film transistor is mainly comparatively responsive with the drain electrode near zone, therefore present embodiment utilizes lightly doped drain 40 to reduce near the leakage current of drain electrode, lightly doped drain as for contiguous source region is then removed, with the series resistance between effective reduction drain electrode and source electrode, improve the operating rate of electron mobility and whole element.The leakage current that the two LDD structural membrane transistors of single LDD structural membrane transistor AND gate first embodiment of present embodiment produce can be with reference to the comparison diagram (near the electric current I d the drain electrode of flowing through during the work of transistor reverse biased) of Figure 12, as for element characteristics such as the starting voltage of two kinds of thin-film transistors and electron mobilities more then can be with reference to the curve chart right side part of figure 2 with Fig. 3.Generally speaking, the thin-film transistor of single LDD structure still can reach the advantage of improving leakage current and electron mobility simultaneously.

Because characteristics of the present invention utilize the relative position between lightly doped drain and grid to form asymmetric thin-film transistor structure, to reach purposes such as reducing leakage current, therefore the present invention does not limit and only can be applied to the above-mentioned thin-film transistor structure of going up gate type (top-gate), more can be applied to the thin-film transistor structure of existing low gate type (bottom-gate) simultaneously.In last gate type thin-film transistor structure, grid is located at the semiconductor layer top, and in the thin-film transistor structure of low gate type, grid is located at the semiconductor layer below.Therefore the present invention can be further makes structures such as gate insulator and grid on prior to substrate in the manufacturing process of low gate type thin-film transistor, cover an insulating barrier and have lightly doped drain, the isostructural semiconductor layer of source/drain in the grid top more afterwards, and utilize the relative position between its lightly doped drain and grid to form dissymmetrical structure, and then reach the present invention and reduce purposes such as leakage current.

Compared to existing symmetric form thin-film transistor structure, thin-film transistor structure of the present invention includes asymmetric lightly doped drain, therefore can moderately increase the length of lightly doped drain further in drain electrode one side comparatively responsive, reduce leakage current to have to leakage problem.In addition, the present invention can also further shorten the length of lightly doped drain in source electrode one side, even remove the ldd structure of source side fully, with the series resistance between effective reduction drain electrode and source electrode, improve the operating rate of electron mobility and whole element.

The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. An asymmetric thin film transistor structure comprising:

a substrate;

A semiconductor layer is arranged on the substrate, the semiconductor layer includes a channel region, a first lightly doped region and a first heavily doped region are sequentially arranged on one side of the channel region, a second lightly doped region The impurity region and a second heavily doped region are sequentially arranged on the other side of the channel region, and a first interface is included between the first lightly doped region and the first heavily doped region, and the second A second interface is included between the lightly doped region and the second heavily doped region; and

A grid is arranged on the substrate, the grid includes a first side wall and a second side wall, and wherein the distance between the first side wall and the first interface is the same as the distance between the second side wall and the first side wall The spacing between the two interfaces is not equal.

2. The TFT structure of claim 1, wherein the gate is disposed above the semiconductor layer.

3. The TFT structure of claim 1, wherein the gate is disposed under the semiconductor layer.

4. The TFT structure of claim 1, wherein the first sidewall is stacked with the first lightly doped region.

5. The TFT structure of claim 1, wherein the second sidewall is stacked with the second lightly doped region.

6. The thin film transistor structure of claim 1, wherein the first lightly doped region and the second lightly doped region serve as a lightly doped drain of the thin film transistor.

7. The thin film transistor structure of claim 1, wherein the first heavily doped region and the second heavily doped region serve as a source and a drain of the thin film transistor.

8. The TFT structure of claim 1, wherein the length of the first lightly doped region is between 0 and 3.5 microns.

9. The thin film transistor structure of claim 1, wherein the length of the second lightly doped region is between 0 and 3.5 microns.

10. The thin film transistor structure of claim 1, wherein the semiconductor layer comprises N-type dopants.

11. The thin film transistor structure of claim 1, wherein the semiconductor layer comprises a P-type dopant.

12. The TFT structure of claim 1, wherein the gate is a metal layer.

13. The thin film transistor structure of claim 1, wherein the gate is formed of doped polysilicon.