KR100815894B1 - Manufacturing Method of CMOS Polycrystalline Silicon Thin Film Transistor of Ldd Structure - Google Patents

Abstract

The present invention comprises the steps of stacking the buffer layer and the amorphous silicon layer on the insulating substrate in order; Heat treating the amorphous silicon at 400 to 500 ° C. for 2 hours in an N ₂ atmosphere to dehydrogenate and crystallize, and then patterning to form a first semiconductor layer and a second semiconductor layer; Performing and activating n-doping (LDD doping) having a doping concentration of 10 ¹² to 9 × 10 ¹² , 9 × 10 ¹³ to 10 ¹⁴ atomic number / cm 2 only in the predetermined region of the first semiconductor layer; After sequentially forming a gate insulating film and a gate electrode on the partial region and the undoped region of the LDD doped layer of the first semiconductor layer, n + doping having a doping concentration of 10 ¹⁵ atomic number / cm 2 is performed to form the first source / drain region. Forming a; Sequentially forming a gate insulating film and a gate electrode over a predetermined region of the second semiconductor layer, and then performing p + doping to form a second source / drain region; Activating the first and second source / drain regions; A method of manufacturing a CMOS thin film transistor having a GOLDD structure, comprising: forming a source / drain electrode connected to the first and second source / drain regions;

In the present invention, there is no difference in grain characteristics between the LDD doped region, the doped region and the channel layer, and the entire region of the semiconductor layer, and thus, a GOLDD structure CMOS polycrystalline silicon thin film transistor having excellent device characteristics and uniformity characteristics, such as leakage current reduction, is provided. To provide.

Thin Film Transistors, Polycrystalline Silicon, CMOS, LDD

Description

Method of fabricating CMOS Poly Silicon TFT having LDD structure

1A to 1F are cross-sectional views illustrating a manufacturing process of a CMOS polycrystalline silicon thin film transistor having a conventional LDD structure.

2A to 2G are cross-sectional views of a manufacturing process of a LDD structure CMOS polycrystalline silicon thin film transistor according to the present invention.

3A is a graph showing device characteristics of a polycrystalline silicon thin film transistor of a conventional LDD structure.

3B is a graph showing device characteristics of a polycrystalline silicon thin film transistor having an LDD structure according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 100: insulation board

2, 102: buffer layer

3a, 106a: LDD doped layer

3b, 4b, 106b, 108b: channel layer

3c, 106c: n + doped layer (source / drain region)

4a, 108a: p + doped layer                 

9, 112: gate insulating film

11, 114: gate electrode

19, 122: source / drain electrodes

The present invention relates to a method of manufacturing a polycrystalline silicon thin film transistor, and more particularly, to a method of manufacturing a complementary metal oxide semiconductor (CMOS) polycrystalline silicon thin film transistor having a gated overlapped lightly doped drain (GOLDD) structure.

In an active matrix liquid crystal display device using a thin film transistor as a switching element, a pixel driving thin film transistor is formed for each pixel to drive each pixel, and a thin film transistor for driving the pixel driving is used to operate a scan line and a signal line. A thin film transistor for a driving circuit that applies a signal to a data line is formed.

Among the thin film transistors, polycrystalline silicon thin film transistors can be manufactured at a temperature similar to that of amorphous silicon thin film transistors due to the development of laser crystallization technology, and have higher electron or hole mobility than the amorphous silicon thin film transistors. Complementary Metal-Oxide Semiconductor (CMOS) thin film transistors having a channel can be implemented to be simultaneously formed on the large glass substrate for the driving circuit and the pixel driving.

However, in the case of NMOS transistors among the CMOS polycrystalline silicon thin film transistors, since silicon (P) is generally used as a doping ion, silicon crystals are relatively larger in terms of mass than boron (B) used as a doping ion when fabricating a PMOS thin film transistor. The damage zones are generated to cause damage zones, which are not completely recovered even in a subsequent activation process.

Due to the presence of such a damaged region, when the electron is accelerated from the source region to the drain region, a hot carrier stress, in which electrons flow into the gate insulating layer or the MOS interface, is generated and the electron mobility is reduced, thereby reducing the circuit driving. It has a fatal effect on the stability of the operation, and also has a problem that the off current (Off Current) is large.

In order to solve this problem, the offset between the gate and the source / drain region to form an undoped region is provided to reduce the off current by reducing the electric field applied to the junction due to the large resistance of this region. Structure), a method of forming a lightly doped drain (LDD) to reduce off current and minimize on current reduction by doping a portion of a source / drain region at low concentration (LDD structure).

Hereinafter, a general manufacturing method of a CMOS polycrystalline silicon thin film transistor having a conventional LDD structure, particularly a GOLDD (Gate Overlapped Lightly Doped Drain) structure, will be described in detail with reference to the accompanying drawings.                         

1 is a cross-sectional view of a general manufacturing process of a CMOS polycrystalline silicon thin film transistor in which a GOLDD, that is, a gate and an LDD region overlap.

First, as shown in FIG. 1A, a buffer layer 2 is formed on a substrate 1, amorphous silicon is deposited on the buffer layer 2, and then patterned into two islands to form a semiconductor layer 5. At this time, the n-type thin film transistor TFT and the p-type thin film transistor TFT are formed in the patterned two semiconductor layers 3 and 4, respectively.

The buffer layer 2 is made of an insulating material such as silicon oxide (SiO _x ), and serves to prevent foreign matter of the substrate 1 from penetrating into amorphous silicon in a subsequent process.

Thereafter, as shown in FIG. 1B, after the first photoresist layer 7 is formed on the front surface of the substrate, the semiconductor layer 4 of the predetermined central portion region and the p-type TFT region of the semiconductor layer 3 of the n-type TFT region is formed. Pattern to cover the entire area. Thereafter, a lightly doped drain (LDD) doping, ie, lightly doped drain (LDD) doping, is performed on the entire surface of the substrate to form the n-doped layer 3a. At this time, the undoped region becomes the channel layer 3b.

Thereafter, as shown in FIG. 1C, after the first photoresist layer 7 is removed, the amorphous silicon formed of the semiconductor layer 5 is crystallized by a laser annealing process.

Thereafter, as shown in FIG. 1D, the gate insulating film 9, the gate electrode 11, and the second photoresist layer 13 are sequentially formed, and in the case of the n-type TFT region, the channel layers 3b and n The gate insulating film 9 and the gate electrode 11 are patterned so that predetermined regions of the doped layer 3a overlap, and in the case of the p-type TFT region, the entire semiconductor layer regions 4 are patterned so as to overlap.

The gate insulating layer 9 may be an insulating material layer such as silicon oxide or silicon nitride (SiN _x ), and the gate electrode 11 may be formed of AlNd or a double layer of AlNd and Mo.

Thereafter, the first source / drain region 3c is formed in the n-type TFT region by doping n + ions onto the entire surface of the substrate. In this process, the n-type TFT region overlaps the gate electrode 11 and the LDD doped region 3a to form a GOLDD structure.

Thereafter, the second photoresist layer 13 is removed, and as shown in FIG. 1E, after the third photoresist layer 15 is laminated, the n-type TFT region is patterned so that all regions overlap. In the p-type TFT region, the gate insulating film 9 and the gate electrode 11 are patterned so that only a predetermined region in the center portion of the semiconductor layer 4 remains.

Thereafter, the second source / drain region 4a is formed in the p-type TFT region by doping p + ions, and the undoped region becomes the channel layer 4b. The first source / drain region 3c and the second source / drain region 4a are activated.

Thereafter, as shown in FIG. 1F, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate to form the interlayer insulating film 17, and then the predetermined portions of the first and second source / drain regions 3c and 4a are formed. A contact hole is formed in the interlayer insulating layer 17 to expose the portion. Thereafter, source / drain electrodes 19 connected to the first and second source / drain regions 3c and 4a are formed through the contact holes, thereby completing a CMOS thin film transistor having a GOLDD structure and a p-type thin film transistor. do.

In the conventional GOLDD CMOS thin film transistor manufacturing method, the amorphous silicon is crystallized after LDD doping in the n-type TFT region of the GOLDD after forming the semiconductor layer, thereby crystallizing between the center and the end of the LDD doped region. Characteristic differences occur, causing leakage current and nonuniformity, and when the crystallization energy is high, dopants in the doped regions are segregated, resulting in a problem of deterioration of device uniformity.

Figure 3a is a graph showing the deterioration of the device characteristics of the conventional GOLDD CMOS thin film transistor caused by the problem, it can be seen that the threshold voltage, S-factor and leakage current are all large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is that there is no difference in grain characteristics between LDD doped regions and between doped regions and channel layers. The present invention provides a GOLDD structure CMOS polycrystalline silicon thin film transistor.

In order to achieve the above object, the present invention comprises the steps of laminating a buffer layer and an amorphous silicon layer on the insulating substrate in order; Heat treating the amorphous silicon at 400 to 500 ° C. for 2 hours in an N ₂ atmosphere to dehydrogenate and crystallize, and then patterning to form a first semiconductor layer and a second semiconductor layer; Performing and activating n-doping (LDD doping) having a doping concentration of 10 ¹² to 9 × 10 ¹² , 9 × 10 ¹³ to 10 ¹⁴ atomic number / cm 2 only in the predetermined region of the first semiconductor layer; After sequentially forming a gate insulating film and a gate electrode on the partial region and the undoped region of the LDD doped layer of the first semiconductor layer, the first source / drain region is subjected to n + doping with a doping concentration of 10 ¹⁵ atoms / cm 2. Forming a; Sequentially forming a gate insulating film and a gate electrode over a predetermined region of the second semiconductor layer, and then performing p + doping to form a second source / drain region; Activating the first and second source / drain regions; A method of manufacturing a CMOS thin film transistor having a GOLDD structure includes forming a source / drain electrode connected to the first and second source / drain regions.

That is, in the present invention, by performing LDD doping after crystallizing the amorphous silicon, there is no difference in grain characteristics between the LDD doping region and between the LDD doping region and the channel layer, and the separation of the dopant does not occur, thereby enabling stable device characteristics. Do.

Hereinafter, a method of manufacturing a CMOS polycrystalline silicon thin film transistor having an LDD structure according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a CMOS polycrystalline silicon thin film transistor having an LDD structure according to the present invention.

First, as shown in FIG. 2A, the buffer layer 102 and the amorphous silicon layer (a-Si: H) 104 are sequentially stacked on the insulating substrate 100 using chemical vapor deposition.

The buffer layer 102 is to prevent the impurity component of the insulating substrate 100 from diffusing into the amorphous silicon layer 104. The buffer layer 102 may be formed of a silicon oxide film (SiO _x ) or silicon nitride (SiN _x ). Do.

The amorphous silicon layer 104 is preferably formed of a SiH ₄ and H ₂ mixed gas by using a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition) method.

Thereafter, hydrogen (H ₂ ) contained in the amorphous silicon layer 104 causes defects in the crystallization process in the future, so that the amorphous silicon layer is dehydrogenated. At this time, the amorphous silicon (a-Si: H) has a chemically weak bond and can remove the hydrogen component contained in the amorphous silicon by heat treatment. Therefore, the dehydrogenation process is preferably heat-treated for about 2 hours at a temperature of 400 to 500 ℃ in N ₂ atmosphere so that the hydrogen components in the amorphous silicon to fly to the gas state.

After the dehydrogenation process, the amorphous silicon layer 104 is polycrystallized by using a laser, and as shown in FIG. 2B, two islands are patterned to form semiconductor layers 106 and 108. In this case, n-type TFTs and p-type TFTs are formed in the patterned two semiconductor layers 106 and 108 through post-processes, respectively.

Thereafter, as shown in FIG. 2C, after forming the first photoresist layer 110 on the front surface of the substrate, the semiconductor layer 108 of the predetermined central portion region and the p-type TFT region of the semiconductor layer 106 of the n-type TFT region is formed. Pattern to cover the entire area. Thereafter, n-doped lightly doped drain (LDD) doping is performed on the entire surface of the substrate to form the n-doped layer 106a. At this time, the undoped region becomes the channel layer 106b.

The LDD doping material is preferably phosphorus (P), and the doping concentration is preferably 10 ¹² to 10 ¹⁴ atoms / cm ² .

Thereafter, as shown in FIG. 2D, the first photoresist layer 110 is removed and the LDD doped layer is activated.

Thereafter, as shown in FIG. 2E, the gate insulating layer 112, the gate electrode 114, and the second photoresist layer 116 are sequentially formed, and in the case of the n-type TFT region, the channel layer 106b and n The gate insulating layer 112 and the gate electrode 114 are patterned so that a predetermined region of the doped layer 106a overlaps, and in the case of the p-type TFT region, the entire semiconductor layer region 108 is patterned so as to overlap.

In this case, the gate insulating film 112 is preferably deposited by using a chemical vapor deposition method, such as silicon oxide or silicon nitride, the gate electrode 114 is AlNd, Mo, or an alloy of AlNd and Mo, such as It is preferable to deposit a conductive material using the sputtering method.

Thereafter, n + doping is performed on the entire surface of the substrate to form the first source / drain regions 106c in the n-type TFT region. In this process, the n-type TFT region overlaps the gate electrode 112 and the LDD doped region 106a to form a GOLDD structure.

In this case, the n + doping is preferably a concentration of 10 ¹⁵ atomic number / cm ² .

Thereafter, the second photoresist layer 116 is removed, and as shown in FIG. 2F, after the third photoresist layer 118 is laminated, the n-type TFT region is patterned so that all regions overlap. In the p-type TFT region, the gate insulating film 112 and the gate electrode 114 are patterned so that only a predetermined region in the center portion of the semiconductor layer 108 remains. Thereafter, p + ions are doped to form a second source / drain region 108a in the p-type TFT region. At this time, the undoped region becomes the channel layer 108b.

In this case, the p + doping material is preferably boron (B), the doping concentration is preferably 10 ¹⁵ atoms / cm ² .

Thereafter, the third photoresist layer 118 is removed, and the first source / drain region 106c and the second source / drain region 108a are activated.

Thereafter, as shown in FIG. 2G, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate to form the interlayer insulating film 120, and then the predetermined portions of the first and second source / drain regions 106c and 108a are formed. A contact hole is formed in the interlayer insulating layer 120 to expose the portion. After that, a source / drain electrode 122 connected to the first and second source / drain regions 106c and 108a is formed through the contact hole, thereby forming a CMOS polycrystalline silicon thin film transistor having a GOLDD structure and a p-type thin film transistor. To complete.

In this case, the source / drain electrodes may be formed of AlNd, Mo, or a double layer of AlNd and Mo.

The device characteristics of the LDD structured thin film transistor according to the present invention as described above are shown in the graph shown in FIG. That is, the thin film transistor of the LDD structure according to the present invention has no difference in grain characteristics in the doped region and the channel region, and thus, as shown in FIG. 3B, the threshold voltage, the S-factor, and the leakage current are small, and thus excellent device characteristics are obtained. .

CMOS polycrystalline silicon thin film transistor of the LDD structure according to the present invention as described above crystallizes the amorphous silicon layer used as the channel layer of the thin film transistor with a polycrystalline silicon layer before performing the LDD doping, between the central portion and the peripheral portion of the doped region, and There is no difference in grain characteristics between the doped region and the channel region, resulting in excellent device characteristics and uniformity.

Claims (9)

Stacking a buffer layer and an amorphous silicon layer on the insulating substrate in order; Heat treating the amorphous silicon at 400 to 500 ° C. for 2 hours in an N ₂ atmosphere to dehydrogenate and crystallize, and then patterning to form a first semiconductor layer and a second semiconductor layer; Performing and activating n-doping (LDD doping) having a doping concentration of 10 ¹² to 9 × 10 ¹² , 9 × 10 ¹³ to 10 ¹⁴ atomic number / cm 2 only in the predetermined region of the first semiconductor layer; After sequentially forming a gate insulating film and a gate electrode on the partial region and the undoped region of the LDD doped layer of the first semiconductor layer, the first source / drain region is subjected to n + doping with a doping concentration of 10 ¹⁵ atoms / cm 2. Forming a; Sequentially forming a gate insulating film and a gate electrode over a predetermined region of the second semiconductor layer, and then performing p + doping to form a second source / drain region; Activating the first and second source / drain regions; Forming a source / drain electrode connected to the first and second source / drain regions. Stacking a buffer layer and an amorphous silicon layer on the insulating substrate in order; Heat-treating the amorphous silicon at 400 to 500 ° C. for 2 hours in an N ₂ atmosphere, and then dehydrogenating it to crystallize to form a polycrystalline silicon layer; Patterning the polycrystalline silicon layer into two islands to form a first semiconductor layer and a second semiconductor layer; Stacking a first photoresist layer on the substrate and patterning the first photoresist layer to cover a predetermined region of the first semiconductor layer and an entire region of the second semiconductor layer; N-doping (LDD doping) having a doping concentration of 10 ¹² to 9 × 10 ¹² and 9 × 10 ¹³ to 10 ¹⁴ atoms / cm 2 on the entire surface of the substrate to form an LDD doping layer and a channel layer on the first semiconductor layer. Forming; Activating the LDD doped layer; After stacking a gate insulating film, a gate electrode, and a second photoresist layer on the entire surface of the substrate, the gate insulating layer, the gate electrode, and the second photoresist layer are stacked, and then patterned to cover a predetermined region and a channel layer among the LDD doped layers on the first semiconductor layer. Patterning to cover; Forming a first source / drain region in the first semiconductor layer by performing n + doping with a doping concentration of 10 ¹⁵ atoms / cm 2 on the entire surface of the substrate; Stacking a third photoresist layer on the entire surface of the substrate, patterning the semiconductor substrate to cover an entire region of the first semiconductor layer, and patterning the semiconductor substrate to cover a predetermined region of the second semiconductor layer; P + doping the entire surface of the substrate to form a second source / drain region in the second semiconductor layer; Activating the first and second source / drain regions; Forming an interlayer insulating film on the entire surface of the substrate and then forming contact holes to expose predetermined portions of the first and second source / drain regions; Forming a source / drain electrode connected to the first and second source / drain regions through the contact hole. delete The method according to claim 1 or 2, The gate electrode or the source / drain electrode is a CMOS thin film transistor manufacturing method, characterized in that consisting of AlNd, Mo, or a double layer of AlNd and Mo. The method according to claim 1 or 2, The doping material of the LDD doped layer is a CMOS thin film transistor manufacturing method, characterized in that the phosphorous (P). delete delete The method according to claim 1 or 2, And a doping material during p + doping of the second source / drain region is boron (B). The method according to claim 1 or 2, And a doping concentration during p + doping of the second source / drain region is 10 ¹⁵ atomic number / cm ² .

Images