CN100395875C - Method for manufacturing thin film transistor and structure thereof - Google Patents

Abstract

The invention provides a thin film transistor on a substrate. The thin film transistor at least comprises: a buffer layer on the substrate; the first polycrystalline silicon layer and the second polycrystalline silicon layer are positioned on the buffer layer, wherein the first polycrystalline silicon layer is provided with a first grid region, a light doped region and a first heavy doped region, the second polycrystalline silicon layer is provided with a second grid region and a second heavy doped region, the light doped region and the first heavy doped region are sequentially surrounded outside the first grid region, and the second heavy doped region is surrounded outside the second grid region; a drain/source electrode in the first heavily doped region and the second heavily doped region; lightly doping in the lightly doped region; a gate oxide layer on the first polysilicon layer, the second polysilicon layer and the buffer layer; and the first grid and the second grid are positioned on the grid oxide layer and are respectively positioned above the first grid region and the second grid region.

Description

Manufacturing method and structure of thin film transistor

technical field

The present invention relates to a manufacturing method for forming a thin film transistor and its structure, more particularly, to a manufacturing method for forming a lightly doped thin film transistor and its structure.

Background technique

Low Temperature Poly-Silicon (LTPS) technology uses an excimer laser as a heat source. After the laser passes through the projection system, it will generate a laser beam with uniform energy distribution, which is projected on the glass substrate with an amorphous silicon structure. When the glass substrate After the amorphous silicon structure absorbs the energy of the excimer laser, it will transform into a polysilicon structure. Since the entire processing process is completed below 600 ° C, it can be applied to general glass substrates.

Although the manufacture of low-temperature polysilicon thin films is much more complicated than that of amorphous silicon thin films, low-temperature polysilicon thin films have the following advantages:

1. Since the low-temperature polysilicon technology can increase the electron mobility to 200 (cm ² /V·sec), it is conducive to the miniaturization of thin-film transistor components. In this way, the panel aperture ratio can be increased, the display brightness can be increased, and the power consumption rate can be reduced. .

2. Low-temperature manufacturing is beneficial to the use of glass substrates, so the production cost can be greatly reduced.

3. Low-temperature polysilicon technology enables the manufacture of CMOS directly on the glass substrate.

4. Low-temperature polysilicon technology enables part of the driving circuit to be fabricated on the glass substrate. Therefore, the circuit on the printed circuit board is relatively simple, so it can save the area of the printed circuit board and increase the integration density of the module.

Therefore, liquid crystal displays formed by low-temperature polysilicon thin films are becoming more and more important.

Contents of the invention

In view of this, the object of the present invention is to provide a manufacturing method and structure for forming a thin film transistor.

The thin film transistor of the present invention includes a first-type transistor and a second-type transistor on a substrate, wherein the first-type transistor has a first gate region, a lightly doped region, and a first heavily doped region, and the second-type transistor has a second a gate region and a second heavily doped region, the outside of the first gate region sequentially surrounds the lightly doped region and the first heavily doped region, and the outside of the second gate region surrounds the second heavily doped region, the method at least include:

forming a buffer layer on the substrate;

forming a first polysilicon layer and a second polysilicon layer on the buffer layer, wherein the first polysilicon layer and the second polysilicon layer correspond to the first type transistor and the second type transistor;

Forming the first heavily doped into the first heavily doped region, using the photoresist covering the first gate region, the lightly doped region and the second polysilicon layer as a shield, and implanting the first heavily doped formed by impurities;

Depositing a gate oxide layer onto the first polysilicon layer, the second polysilicon layer and the substrate; forming a lightly doped region into the lightly doped region utilizing The photoresist is shielded and formed by injecting the first light dopant;

forming a second heavily doped into the second heavily doped region, which is formed by using the photoresist covering the first polysilicon layer and the second gate region as a shield, and implanting the second heavily doped;

activating the first heavily doped, lightly doped, and second heavily doped, wherein the direction of light irradiation is parallel to the direction of implanted ions; and

A first gate and a second gate are formed on the gate oxide layer and are located on the first polysilicon layer and the second polysilicon layer respectively.

The method for forming a thin film transistor of the present invention also includes:

forming a patterned interlayer dielectric layer on the gate oxide layer, the first gate and the second gate, the patterned interlayer dielectric layer selectively exposing the first heavily doped, the second heavily doped, a first grid and a second grid;

forming electrodes to electrically connect the exposed first heavily doped, second heavily doped, first gate and second gate;

forming a protective layer with a pattern on the inner dielectric layer and the electrode, the protective layer with a pattern exposing a part of the electrode of the first type transistor located in the pixel area;

forming a patterned flat layer onto the ILD layer, the patterned flat layer having the same pattern as the patterned protective layer; and

A transparent electrode is formed to electrically connect the exposed part of the electrode of the first type transistor.

In order to make the above-mentioned purposes, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Description of drawings

1 to 11 show the manufacturing process of the low-temperature polysilicon thin film transistor of the present invention.

Detailed ways

The invention provides a manufacturing method and structure for forming a low-temperature polysilicon thin film transistor.

First, please refer to FIG. 1 , a buffer layer 102 and a polysilicon layer 104 are sequentially formed on a substrate 100, and then a patterned photoresist (not shown in the figure) is formed, and the photoresist Etching is performed for masking, thereby forming a polysilicon layer 104 as shown in FIG. 1 .

The substrate 100 in the present invention can be made of glass or plastic material, and the thickness of the polysilicon layer 104 is about 200-1000 angstroms, which is formed by crystallization annealing the amorphous silicon layer formed on the buffer layer 102 by using an excimer laser. form. The leftmost polysilicon layer 104 is used to form the NMOS transistor in the CMOS transistor, and the middle polysilicon layer 104 is used to form the PMOS transistor in the CMOS transistor, and the rightmost polysilicon layer 104 is used to form the NMOS transistor in the pixel area. transistor.

The buffer layer 102 can be made of silicon oxide or silicon nitride, and it is used as a thermal insulation layer, that is, the buffer layer 102 can keep the temperature of the substrate 100 from rising too much during the annealing process when the polysilicon layer 104 is irradiated by an excimer laser. high and deformed.

Then, in FIG. 2, a patterned photoresist 105 is formed on the substrate 100 through a photolithography process, and the photoresist 105 completely covers the PMOS transistor region where the CMOS transistor is to be formed, and the NMOS transistor to be formed The gate region and the lightly doped region of the region. And using the photoresist 105 as a shield, implant a heavy concentration of phosphorus impurities into the substrate 100, and the dose is about 1×10 ¹⁹ /cm ³ to 1×10 ²² /cm ³ to form the source/drain 104a, 104b, 104c and 104d into NMOS transistors.

Then, referring to FIG. 3 , the remaining photoresist 105 is removed, and the gate oxide layer 106 is formed on the buffer layer 102 and the polysilicon layer 104, the thickness of the gate oxide layer 106 is about 500˜1500 angstroms, and Its material can be silicon dioxide. Next, utilize a photolithography process to form a photoresist 107 with a pattern on the gate oxide layer 106. The photoresist 107 completely covers the PMOS transistor region where the CMOS transistor is to be formed, and the gate where the NMOS transistor region is to be formed. polar region. And using the photoresist 107 as a shield, implant light-concentration phosphorus impurities into the substrate 100, and the dose is about 1×10 ¹⁹ /cm ³ to 1×10 ²² /cm ³ to form lightly doped 104m, 104n, 104x and 104y into NMOS transistors.

Then, in FIG. 4, the remaining photoresist 107 is removed, and a photoresist 109 with a pattern is formed on the gate oxide layer 106 by a photolithography process again, and the photoresist 109 covers the entire The NMOS transistor region, and the gate region of the PMOS transistor. And using the photoresist 109 as a shield, inject a heavy concentration of boron impurities into the substrate 100, and the dose is between 1×10 ¹⁶ /cm ³ and 1×10 ¹⁹ /cm ³ to form the source of the PMOS transistor /drains 104i and 104j.

Obviously, the embodiments of the present invention are not limited to forming lightly doped NMOS transistors, and forming lightly doped PMOS transistors can also be used as another embodiment of the present invention. At this time, photoresist 105 and photo The implantation step performed by the photoresist 107 for shielding is respectively implanted with heavy concentration and light concentration of boron impurities, and the implantation step is performed by using the photoresist 109 for shielding, and heavy concentration of phosphorus impurities is implanted.

However, the crystal lattice of the polysilicon layer 104 has been destroyed during the implantation process, and the crystal lattice must be rearranged in the presence of impurities to activate the implanted doping. Therefore, excimer laser irradiation is used to make the crystal lattice and impurities Complete the rearrangement process, as shown in Figure 5. The activation process of the present invention is performed before forming the gate, therefore, the laser can be directly irradiated only from the front of the substrate 100 to make the degree of activation sufficient, instead of irradiating from the front and back of the substrate 100 at the same time.

Next, referring to FIG. 6, a conductive layer is deposited on the gate oxide layer 106, and a gate layer 108 is formed by using photolithography and etching processes. The gate layer 108 can be made of molybdenum (Mo), chromium (Cr) and titanium /aluminum/titanium (Ti/Al/Ti) composition.

Next, in FIG. 7, an interlayer dielectric layer 110 is formed on the entire substrate 100, and several openings are formed in the interlayer dielectric layer 110 and the gate oxide layer 106 by using photolithography and etching processes, these The openings may expose the gate 108 and some of the source/drains 104a, 104b, 104c, 104d, 104i, and 104j. This embodiment shows the case where the openings are all located on the source/drain electrodes 104a, 104b, 104c, 104d, 104i and 104j.

Then, in FIG. 8, a conductive layer is formed on the interlayer dielectric layer 110, and fills the openings in the interlayer dielectric layer 110 and the gate oxide layer 106, and then photolithography and etching processes are used to form An electrode 112 may be electrically connected to the source/drain electrodes 104a, 104b, 104c, 104d, 104i, and 104j. When the openings in the ILD layer 110 and the gate oxide layer 106 simultaneously expose the gate 108 , the electrode 112 is also electrically connected to the gate 108 .

Next, in FIG. 9, a protective layer 114 is formed on the electrode 112 and the interlayer dielectric layer 110, and an opening is formed in the protective layer 114 of the pixel area by using photolithography and etching processes, and the opening exposes the pixel area. The electrode 112. In FIG. 10, a flat layer 116 is formed on the protective layer 114 to fill the openings in the protective layer 114, and then photolithography and etching processes are used to form openings in the flat layer 116 and the protective layer 114 in the pixel area. The planarization layer 116 is to prevent stray capacitance from being generated. It should be noted that the photolithography mask of the patterned protection layer 114 and the planarization layer 116 are the same photolithography mask.

Finally, in FIG. 11, a conductive layer composed of indium tin oxide (ITO) is formed on the planar layer 116, and fills the openings in the protective layer 114 and the planar layer 116, and then photolithography and etching processes are used, A transparent electrode 118 that can be electrically connected to the electrode 112 of the pixel area is formed to complete the fabrication of a low temperature polysilicon thin film transistor.

The manufacturing method disclosed in the above embodiments of the present invention only directly irradiates laser light from the front side of the substrate 100 to activate impurities, and has a lightly doped implantation process to form lightly doped NMOS transistors or PMOS transistors.

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, and any person skilled in the art should be able to make various changes without departing from the spirit and scope of the present invention. Changes and modifications, so the protection scope of the present invention should be defined by the claims.

Claims (20)

1. A method for forming a first-type transistor and a second-type transistor on a substrate, wherein the first-type transistor has a first gate region, a lightly doped region and a first heavily doped region, and the second-type transistor has a first Two gate regions and a second heavily doped region, the outside of the first gate region sequentially surrounds the lightly doped region and the first heavily doped region, and the outside of the second gate region surrounds the second heavily doped region, the method Include at least: forming a first polysilicon layer and a second polysilicon layer on the substrate, wherein the first polysilicon layer and the second polysilicon layer correspond to first-type transistors and second-type transistors; Forming the first heavily doped into the first heavily doped region, using the photoresist covering the first gate region, the lightly doped region and the second polysilicon layer as a shield, and implanting the first heavily doped formed by doping; Depositing a gate oxide layer on the first polysilicon layer, the second polysilicon layer and the substrate; forming light doping into the lightly doped region, wherein the photoresist covering the first gate region and the second polysilicon layer is used as a shield, and formed by implanting the first lightly doped; forming a second heavily doped region into the second heavily doped region, wherein the photoresist covering the first polysilicon layer and the second gate region is used as a shield, and implanted with a second heavily doped substance form; activating the first heavily doped, the lightly doped and the second heavily doped, wherein the direction of light irradiation is parallel to the direction of implanted ions; and A first gate and a second gate are formed on the gate oxide layer and respectively located above the first polysilicon layer and the second polysilicon layer. 2. The method according to claim 1, further comprising a step of forming a buffer layer on the substrate before the step of forming the first polysilicon layer and the second polysilicon layer. 3. The method according to claim 1, further comprising: after the step of forming the first gate and the second gate onto the gate oxide layer: forming a patterned interlayer dielectric layer on the gate oxide layer, the first gate and the second gate, the patterned interlayer dielectric layer selectively exposing the first heavily doped, the second heavily doped, a first gate and a second gate; and Electrodes are formed to electrically connect the exposed first heavily doped, second heavily doped, first gate and second gate. 4. The method according to claim 3, characterized in that, after the step of forming electrodes, further comprising: forming a protective layer with a pattern on the inner dielectric layer and the electrode, the protective layer with a pattern exposing a part of the electrode of the first type transistor located in the pixel area; and A transparent electrode is formed to electrically connect the exposed part of the electrode of the first type transistor. 5. The method according to claim 4, characterized in that, before the step of forming a transparent electrode, further comprising: A patterned flat layer and a patterned protective layer having the same pattern are formed on the interlayer dielectric layer. 6. A thin film transistor on a substrate, the thin film transistor comprising at least: a buffer layer located on the substrate; The first polysilicon layer and the second polysilicon layer are located on the buffer layer, wherein the first polysilicon layer has a first gate region, a lightly doped region and a first heavily doped region, and the second polysilicon layer The layer has a second gate region and a second heavily doped region, the first gate region outerly surrounds the lightly doped region and the first heavily doped region in sequence, and the second gate region outerly surrounds the second heavily doped region ; a drain/source located in the first heavily doped region and the second heavily doped region; Lightly doped, located in a lightly doped region; a gate oxide layer directly on the first polysilicon layer, the second polysilicon layer and the buffer layer; The first gate and the second gate are located on the gate oxide layer and above the first gate region and the second gate region respectively. 7. The thin film transistor according to claim 6, wherein the thickness of the first polysilicon layer and the second polysilicon layer is about 200˜1000 angstroms. 8. The thin film transistor according to claim 6, wherein the thickness of the gate oxide layer is about 500˜1500 angstroms. 9. The thin film transistor according to claim 6, wherein the first gate and the second gate are composed of one of molybdenum, chromium or titanium/aluminum/titanium. 10. The thin film transistor according to claim 6, wherein the drain/source of the first heavily doped region contains phosphorus impurities, and the drain/source of the second heavily doped region contains boron impurities. 11. The thin film transistor according to claim 6, wherein the drain/source of the first heavily doped region has boron impurities, and the drain/source of the second heavily doped region has phosphorus impurities. 12 . The thin film transistor according to claim 6 , wherein the drain/source of the first heavily doped region contains impurities between 1×10 ¹⁹ /cm ³ and 1×10 ²² /cm ³ . 13 . The thin film transistor according to claim 6 , wherein the drain/source of the second heavily doped region contains impurities between 1×10 ¹⁹ /cm ³ and 1×10 ²² /cm ³ . 14. The thin film transistor according to claim 6, wherein the light doping contains impurities between 1×10 ¹⁶ /cm ³ and 1×10 ¹⁹ /cm ³ . 15. The thin film transistor of claim 6, further comprising: an interlayer dielectric overlying the first gate, the second gate, and the gate oxide; and A plurality of electrodes, which penetrate the gate oxide layer and the inner layer dielectric layer, and are electrically connected with the first gate, the second gate and the drain/source. 16. The thin film transistor according to claim 15, wherein the thickness of the interlayer dielectric layer is about 2000˜7000 angstroms. 17. The thin film transistor as claimed in claim 15, wherein the electrode is composed of one of molybdenum, chromium or titanium/aluminum/titanium. 18. The thin film transistor of claim 15, further comprising: a protective layer over the inner dielectric layer and electrodes; and The transparent electrode is located on the protection layer of the pixel area, and is electrically connected to the electrode through the protection layer. 19. The thin film transistor as claimed in claim 18, wherein the transparent electrode is made of indium tin oxide. 20. The thin film transistor of claim 18, further comprising: The flat layer is located between the protective layer and the transparent electrode.

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