JPH022632A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a highly accurate, fine insulating gate field effect transistor superior in quality through a limited process by forming lead-out electrode layers on source and drain regions with a polysilicon film on field regions and implanting ions by the use of resist patterns as masks, thereby forming the source and drain regions and taking possible steps in the same manner. CONSTITUTION:After forming extraction electrode layers 35a on source and drain regions with a polysilicon film on field regions 33 of both sides of an active region, source and drain regions 43 are formed by driving ions by the use of resist patterns 39 and 40 as masks. After that, side walls 46a for mutual connection are formed at side wall parts of the extraction electrode layers 35a. After forming a gate insulating film 44, a gate electrode 48a is formed through the whole formation with the polysilicon film and etchback so as to flatten the surface by burying an interval between the side walls 46a which are covered by a gate insulating film 47. After that, metal wiring layers 52 which are connected to the gate electrode 48a as well as the lead-out electrode layers 35a are formed by forming layer insulation films 49 and contact holes 51.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an insulated gate field effect transistor.

(Prior Art) A conventional method of manufacturing an insulated gate field effect transistor will be described with reference to FIG. 2 (al to fhl).

First, channel stop ion implantation and field oxidation are performed on a semiconductor substrate 1 to form a channel stop layer 2 and a field oxide film 3. By forming this field oxide film, the substrate 1 is divided into an active region where transistors are formed and a field region other than the active region.

An oxide film 4 is formed on the entire surface of the substrate 1 to serve as a gate insulating film of the transistor. Next, ion implantation 5 is performed to control the threshold value, and impurity 6 is implanted into the active slope of the substrate 1 (Fig. 2 (a)). Form layer 7. The polysilicon layer 7 is subjected to phosphorus diffusion to lower its resistance. (FIG. 2(b)) Furthermore, a resist pattern 8 is formed on the polysilicon layer 7 using ordinary photolithography.
(FIG. 2(C)) Using the resist pattern 8 as a mask, the polysilicon layer 7 and oxide film 4 are etched to form a gate electrode 7a, and an oxide film (gate insulating film) is formed only below the gate electrode 7a. 4 (Figure 2 (d))
Thereafter, as shown in the figure, after removing the resist pattern 8, ion implantation 9 is performed to form source/drain regions, and impurities 10 are implanted into the source/drain forming regions in the active region.

At this time, the concentration of impurity 10 is made higher than that of impurity 6. At this time, in order to improve the ion implantation distribution, the source
A thin oxide film 11 is formed in advance on the surface of the drain formation region. This thin IIK oxide layer 11 is also formed on the surface of the gate electrode 7a at the same time.

Next, by performing annealing to activate the impurities 6 and IO, a threshold control region 12 and source/drain regions 13 are formed in the active region of the substrate 1 (FIG. 2(e)).

Next, an interlayer insulating film 14 is formed on the entire surface, and a resist pattern 15 is formed on it (FIG. 2(f)).Then, using the resist pattern 15 as a mask, the interlayer insulating film 14 and thin oxide film II are etched. By this, source/drain regions 13 and gate electrodes 7a are formed in these regions.
A contact hole 16 is formed on the top (Fig. 2 fgl)
Then, after removing the resist pattern 15, contact reflow is performed to smooth the edges of the contact hole 16. Then, as shown in FIG.・
An impurity 18 is formed in the contact hole portion of the drain region 13.
Enter.

Next, a heat treatment is performed to activate the impurity 18, thereby forming a deep layer 19 with a high concentration in the contact hole portion of the source/drain region 13 (FIG. 2 (hl),
Finally, by performing aluminum vapor deposition and buttering,
Source/drain region 1 through contact hole 16
3 and gate electrode #1j7a are formed as shown in FIG. 2 [hl].

(Problems to be Solved by the Invention) However, the conventional manufacturing method as described above has the following drawbacks.

■ The gate length is determined by the photolithography process shown in FIG. 2(c) and the subsequent processing and etching processes, but due to the conversion difference between the two processes, it was not possible to obtain a fine gate length with high accuracy.

■ Aluminum wiring 20 directly from source/drain region 13
In order to bring out this, contact ion implantation 17 (formation step of highly doped deep layer 19) is required to prevent penetration of aluminum in source/drain regions 13.

■ Aluminum wiring 20 directly from source/drain region I3
In order to draw out the contact hole 16 and aluminum wiring 20
Miniaturization of transistors is limited by the formation limit of .

■ Contact hole 16 due to miniaturization of transistors
Since the diameter of the wiring becomes smaller and the aspect ratio becomes higher, embedding of the wiring material becomes insufficient.

■ Contact reflow is required to fully embed the wiring material, but this reflow allows the interlayer insulating film 1
A problem arises of autodoping of impurities from No. 4 into the contact portion.

■ Due to the severe level differences on the surface, it was not possible to accurately form patterns such as forming contact holes 16 and aluminum wiring 20.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a highly precise and fine insulated gate field effect transistor in a small number of steps.

(Means for Solving the Problems) In the present invention, after separating a semiconductor substrate into an active region and a field region, by forming a first polysilicon III on the entire surface and patterning, a source and a field region are formed on both sides of the active region. A drain extraction electrode layer is formed using the remaining first polysilicon film, and then a resist pattern is formed to cover the gate formation region and field region in the active region, and ions are implanted using the resist pattern as a mask. , a source/drain region is formed in the source/drain forming region in the active region, and then, after removing the resist pattern, a second polysilicon film is formed on the entire surface and anisotropically etched to form a second polysilicon film on the source/drain region. After forming a sidewall for interconnection on the sidewall portion of the extraction electrode layer, and then forming a gate insulating film on the surface of the extraction electrode layer, the surface of the sidewall, and the exposed surface of the substrate in the active region, a third By forming a polysilicon film on the entire surface and etching back, a gate electrode is formed to fill the space between the sidewalls covered with the gate insulating film and flatten the surface, and then an interlayer insulating film is formed on the flat surface. A contact hole is opened on the gate electrode and a pair of extraction electrode layers, and a metal wiring layer is formed.

(Function) In the manufacturing method described above, the gate length is determined only by the resist pattern forming process when forming the source/drain regions, that is, the photolithography process. Further, the source/drain regions are drawn out onto the field region using polysilicon and connected to metal wiring. Furthermore, after the gate electrode formation is completed, the surface becomes flat.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1 (al to fm+).

First, channel stop ion implantation and field oxidation are performed on the semiconductor substrate 31 in the same manner as in the prior art to form a channel stop N32 and a field oxide film 33. As a result, the surface of the substrate 31 is divided into an active area and a field area. Approximately 200 people formed a thin oxide film 34 for ion implantation and as an etching stopper for polysilicon on the substrate 31 divided into both regions, and then formed a polysilicon film 35 on top of it using the LPCVD method.
00 people. Then, the polysilicon film 3
5, phosphorus is diffused using a known diffusion technique to lower the resistance so that it can be used as a source/drain extraction "Fit" pole layer, and then a resist pattern 36 is formed on the polysilicon film 35 using a known photolithography technique.

(FIG. 1(a)) Then, using the resist pattern 36 as a mask, the polysilicon film 35 is subjected to reactive ion etching (RIB>
By dry etching, the 8-layer polysilicon IIW 35 is left only as source/drain extraction electrode layers 35a on the field regions on both sides of the active region (FIG. 1(b)).Next, as shown in the same figure, the resist After removing the pattern 36, ion implantation 37 is performed through the thin oxide film 34 to control the threshold voltage of the transistor, and impurities 38 are implanted into the active region of the substrate 31.

Next, a process to determine the gate length is performed using a known photolithography technique, but since the step difference is large, a multilayer resist process was adopted here. First, as shown in FIG.
After coating about 12,000 layers of PMMA39 on the entire surface and flattening the surface, positive resist 40 is coated on top.
812000 Nested coating. After patterning the positive resist 40 as shown in FIG. 1(c), PM is applied to the same pattern as shown in FIG. 1(fdl).
The MA 39 is also patterned to cover the gate formation region and field region in the active region with a two-layer resist pattern. Then, using the two-layered resist pattern as a mask, impurity 4I for source/drain formation is ion-implanted (42) at a higher concentration than the impurity 38 only into the source/drain formation region of the active region that is not covered by the resist pattern. Type more.

After that, after removing the resist pattern, an annealing process is performed.The impurity 41.38 is activated by this annealing process, and a source/drain region 43 is formed in the active region of the base +ff131 in the source/drain formation region.
Further, a threshold control region 44 is formed in the gate formation region between them (see tel in FIG. 2). At this time,
An oxide film 45 is formed on the surface of the extraction electrode layer 35a.

Thereafter, this oxidized IyA 45 and the thin oxide film 34 in the active region are removed to expose the surfaces of the extraction electrode layer 35a, source/drain region 43, and threshold control region 44, and then polysilicon Ta 46 is deposited on the entire surface. Form to 0 thickness for about 3000 people (1st U!J (f+)
At this time, the well-known doped LPCVD method is used to generate the polysilicon film 46. Furthermore, the first 500 names will be non-doping, and the remaining 2,500 will be doped. This is to prevent impurities from being supplied to the threshold control area 44. Doping was performed using phosphine.

Thereafter, the entire surface of the polysilicon M, 46 is etched by known anisotropic dry etching (RrE). Then, as shown in FIG.
Only the side wall portion a remains as a side wall 46a. This sidewall 46a allows the source/drain formation 43 to be extended? It scratch layer 35a is electrically connected.

Next, by performing thermal oxidation, a gate insulating film (SiO2 film) 47 is formed on the surface of the extraction electrode layer 35a, the surface of the sidewall 46a, and the exposed surface of the substrate in the active region.
(Fig. 1(h)). At this time, if thermal oxidation is performed at 850°C for 25 minutes in a wet a,'J atmosphere,
On the surfaces of the lead electrode layer 35a and the sidewall 46a (both of which have a phosphorus concentration of 6X10"/-) made of polysilicon, a gate insulating film 47 of 500% Si is formed, and a single silicon active region substrate is exposed. 100 A as the same gate insulation M47 on the surface
A 5ift thick film is formed. In addition, thermal oxidation can be performed with wet 0. If the process is carried out at 850° C. for 45 minutes in an atmosphere, the surface of the extraction electrode layer 35a and the sidewall 468 will have a
A SiO □ film with a thickness of 0.000 mm is formed. Further, a 200 5iO1 film is formed on the exposed surface of the substrate. During this thermal oxidation, the phosphorus concentration in the sidewall 46a is made uniform, and the ohmic properties between the sidewall 46a and the source/drain region 43 are improved.

Next, a polysilicon film 48 for forming a gate electrode is formed on the entire surface of the substrate 31 by a known LPCVD method to a thickness of about 6,000, and phosphorus is diffused to lower the resistance. )) After that, a resist (not shown) is coated to fill in the steps of polysilicon #48, and then the gate wall on the extraction electrode layer 35a is removed! ! polysilicon film 4 until film 47 is exposed.
8 and resist etch back using RIE dry etching technology, the gate is completely removed! A polysilicon film 48 is formed only between the sidewalls 46a covered with 47.
, and form the gate electrode 48a (Fig. 1 (Jl)
By forming the gate electrode, the space between the sidewalls 46a is filled and the surface becomes flat.

After that, an interlayer insulating film 49 is formed on the flattened gate electrode 48a and extraction electrode layer 35a (7) LPC
At this time, the interlayer insulating film 49 may be a film that is difficult to reflow because the lower layer is flattened. In Step II, a resist pattern 50 is formed on the interlayer insulating film 49 as shown in the figure.

Then, by dry etching the interlayer insulating film 49 and the gate insulating pattern 47 using the resist pattern 50 as a mask, contact holes 51 are formed on the gate electrode 148a and the extraction electrode layer 35a, respectively.
is opened, and then the resist pattern 50 is removed (first
Figure (1)).

Thereafter, by performing aluminum evaporation and patterning of approximately 7,000 layers, an aluminum wiring layer 52 is formed which is connected to each of the gate electrode 48a and the pair of extraction electrode layers 35a through the contact hole 51 (see FIG. 1 ((2)).
)) This completes the insulated gate field effect transistor.

(Effects of the Invention) According to the manufacturing method of the present invention as detailed above, the following effects can be obtained.

■ The only process to determine the gate length is the photolithography process, and the gate length is determined without worrying about the conversion difference with etching, so the gate length can be formed with fine coal, and fine gate lengths can also be easily formed. can get.

■ The source and torlein regions are drawn out onto the field region using polysilicon, and the metal wiring is connected to the polysilicon lead electrode layer, so a deep layer with a height of 1 degree is formed at the contact part of the source and drain regions. The ion implantation process for this purpose can be omitted.

■ The source/drain regions are drawn out using polysilicon onto the field region, contact holes are opened in the interlayer insulating film above the field region, and metal wiring is formed, so the reduction of the transistor area is achieved by forming contact holes and metal wiring. It is no longer influenced by limitations and can be further downsized. Further, the contact hole can be made large without being affected by the reduction in size of the transistor portion, and therefore the 7 aspect ratio can be made small, so that the wiring material can be sufficiently filled.

(2) Since the surface can be flattened after the formation of the gate electrode is completed, subsequent pattern formation such as formation of contact holes for the intercostal insulating film and formation of aluminum wiring can be performed with high precision.

■ Since the surface is flattened when the gate electrode is formed, it is possible to use a film that is not doped with impurities and is difficult to reflow as the interlayer insulating film, and the source/drain contact holes can be made large above the field region. Since a contact reflow process is not required, auto-doping of impurities from the interlayer insulating film into the contact portion can be completely eliminated.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process sectional view showing a conventional method for manufacturing an insulated gate field effect transistor. 31... Semiconductor substrate, 33... Field oxide film,
35... Polysilicon film, 35a... Leading electrode layer, 36... Resist pattern, 39... PMMA,
40...Positive resist, 42...Ion implantation, 4
3... Source/drain region, 46... Polysilicon film, 46a... Side wall, 47... Gate insulation; 1, 48... Polysilicon film, 48a... Gate electrode, 49... ...Interlayer insulating film, 51...Contact portion, 52...Aluminum wiring. Fig. 1 46: Polysilicon @ Fig. Conventional manufacturing method Fig. 2

Claims (1)

[Claims] (a) After separating the semiconductor substrate into an active region and a field region, by forming and patterning a first polysilicon film on the entire surface, source and drain extraction electrodes are formed on the field region on both sides of the active region. (b) forming a resist pattern to cover the gate formation region and field region in the active region, and implanting ions using the resist pattern as a mask; (c) After that, the resist pattern is removed and a second step is performed.
(d) forming a sidewall for interconnection on the source/drain region and on the sidewall portion of the extraction electrode layer by forming a polysilicon film on the entire surface and performing anisotropic etching; (e) forming a gate insulating film on the surface of the electrode layer, the surface of the sidewalls, and the exposed surface of the substrate in the active region; (f) After that, an interlayer insulating film is formed on the flat surface, and a gate electrode and a pair of gate electrodes are formed on this interlayer insulating film. A method for manufacturing a semiconductor device, comprising the steps of: forming a contact hole on an extraction electrode layer; and (g) forming a metal wiring layer connected to a gate electrode and an extraction electrode layer through the contact hole.