TWI229875B - Method of fabricating deep trench capacitor and memory device having the same - Google Patents

Abstract

A method of fabricating deep trench capacitor is disclosed. A deep trench is formed in a substrate, and then a doped region is formed around the bottom portion and lower portion of the deep trench. A dielectric layer is formed in the deep trench covering the doped region, and then a first conductive layer is formed between the dielectric layer in the deep trench. A collar oxide layer is formed on the middle portion of the deep trench, and a second conductive layer is formed between the collar oxide layer in the deep trench. An insulating layer is formed in the deep trench and the insulating layer is removed partially to expose one side of the second conductive layer and the collar oxide layer. A single side buried strap is formed in the other side of the deep trench covering the second conductive layer and the collar oxide layer and exposing the insulating layer.

Description

1229875 V. Description of the invention (1) Field of the invention The present invention relates to a method for manufacturing a memory element, and more particularly to a method for manufacturing a memory element with a deep trench capacitor. Prior art With the continuous miniaturization of components, the size of components has gradually decreased. For memory components with capacitors, the space for capacitors can be made smaller and smaller. Trench-type capacitor memory element is a component that uses the space in the substrate to make a capacitor to gain area, so it is very suitable for the current market demand. A method for manufacturing a trench capacitor is known. As shown in FIG. 1A, a doped region 8 is first formed at the lower edge of the deep trench 6 and the periphery of the bottom, and a dielectric layer is formed in the deep trench 6 at the periphery of the doped region. 10, then, a first polycrystalline silicon layer 12 is formed in the deep trenches 6 between the dielectric layers 10, and then a collar oxide layer 16 is formed on the middle surface of the deep trenches 6, and the collar oxide layer 1 A second polycrystalline silicon layer 18 is formed in the deep trench 6 between 6. Next, please continue to refer to FIG. 1A to form a single side buried strap in the deep trench 6. A method of forming a single-sided buried band is, for example, forming a third polycrystalline silicon layer 2 2 in the deep trench 6, and then forming a conformal silicon nitride layer 22 and an amorphous silicon layer 24 on the substrate 6. Then, a unilateral tilted ion implantation process 26 is performed to dope the amorphous silicon layer on one side to form a doped amorphous silicon layer 24a. Thereafter, referring to FIG. 1B, an etching process is performed to etch and remove the amorphous silicon layer 24 by using the difference in etching rate between the doped amorphous silicon layer 24a and the amorphous silicon layer 24. Then, using the doped amorphous silicon layer 24a as an etching mask,

13099twf.ptd Page 7 1229875 V. Description of the invention (2) Etching removes the silicon nitride layer 22 and the polycrystalline silicon layer 20 on the other side of the deep trench. Thereafter, referring to FIG. 1C, the doped amorphous silicon layer 24a and the silicon nitride layer 22 are removed by wet etching, and the polycrystalline silicon layer 20 is exposed. This polycrystalline silicon layer 20 is It is a unilateral burial zone. Thereafter, an isolation layer 27 is formed in the deep trench 6 and then the subsequent processes are performed. In the above-mentioned conventional method, the steps of forming a single-sided buried band are complicated, and when the unilateral inclined ion implantation process 26 is performed, since the size of the deep trench 6 is smaller and smaller, it is easy to cause a scattering effect ( sca 11 eringeffect), so that the implanted ions bounce to the other side, and the amorphous silicon layer on the other side is also doped, so that the buried band formed by subsequent etching is not one-sided, but is isolated. The problem. In addition, when the doped polycrystalline silicon layer and the silicon nitride layer are removed by etching, the under-oxidation phenomenon of the pad oxide layer 3 and the underlying substrate 2 is liable to affect subsequent processes. In addition, when the isolation layer 26 is filled, since the height and width are relatively high, the formed isolation layer 27 is often formed with voids 28, which causes isolation problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a memory element having a deep trench capacitor, which can reduce the step of forming a single-sided buried band. Another object of the present invention is to provide a method for manufacturing a memory device having a deep trench capacitor, which can be applied to the next generation.

13099twf.ptd Page 8 1229875 V. Description of the invention (3) Another object of the present invention is to provide a method for manufacturing a memory device with a deep trench capacitor, which can avoid the formation of holes in the isolation layer on the top of the trench. The invention provides a method for manufacturing a deep trench capacitor. The method first forms a deep trench in a substrate, and forms a doped region on the lower edge of the deep trench and the periphery of the bottom, and forms a dielectric on the periphery of the doped region in the deep trench. An electrical layer, and then a first conductive layer is formed in the deep trench between the dielectric layers; then, a collar oxide layer is formed on the middle surface of the deep trench; and a second conductive layer is formed in the deep trench between the collar oxide layer . Thereafter, an insulating layer is formed on the upper part of the deep trench to cover the second conductive layer and the collar oxide layer. Then, the insulating layer on the side of the deep trench is removed to expose part of the second conductive layer and part of the collar oxide layer. Then, a single-sided buried tape is formed on the upper part of the other side of the deep trench to cover the second conductive layer and the collar oxide layer that are not covered by the insulating layer and expose the insulating layer. Therefore, the method for manufacturing a deep trench capacitor according to the present invention can reduce the number of steps for forming a single-side buried band. The manufacturing method of the deep trench capacitor of the present invention can be applied to the next generation. The manufacturing method of the deep trench capacitor of the present invention can avoid the formation of holes in the isolation layer above the trench. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed explanation is as follows: Implementation:

13099twf.ptd Page 9 1229875 V. Description of the Invention (4) The following embodiments use dynamic random access memory to describe the memory element with a trench capacitor of the present invention. However, it is not intended to limit the present invention. Referring to FIG. 2A, first, a mask layer is sequentially formed on the substrate 100. The mask layer is, for example, an oxide layer 102 and a silicon nitride layer 104. A method for forming the pad oxide layer 102 is, for example, a thermal oxidation method. A method for forming the silicon nitride layer 104 is, for example, a chemical vapor deposition method. Thereafter, the pad oxide layer 102 and the silicon nitride layer 104 are patterned, and the substrate 100 is etched to form a plurality of deep trenches 106 in the substrate 100. Next, please continue to refer to FIG. 2A. A doped region 108 is formed in the bottom 100 of the deep trench 10 and the substrate 100 at the lower periphery, which is used as an external electrode of the capacitor. Thereafter, a dielectric layer 110 is formed at the bottom and the lower surface of the deep trench 108, and a first conductive layer 112 is formed in the deep trench 106 between the dielectric layers 110. The method for forming the dielectric layer 110 and the first conductive layer 112 is, for example, firstly sequentially forming a thin dielectric layer and a conductive material layer filling the deep trenches 106 on the substrate 100, such as a silicon oxide layer and A layer of doped polycrystalline silicon layer, and then a chemical mechanical polishing process is used to remove the conductive material layer covering the silicon nitride layer 104, and then etch back a part of the conductive material layer located in the deep trench 106 In order to form the first conductive layer 1 12, the dielectric layer located above the silicon nitride layer 104 and above and in the middle of the deep trenches 106 is etched away, leaving the dielectric around the first conductive layer Π2. Layer 110. After that, a tempering process is performed to repair the first conductive layer 1 12. At this time, the middle and upper sidewall surfaces of the deep trench 10 6 will form an oxide layer due to tempering. This oxide layer will be used in the subsequent etching process. An oxide layer 1 1 4 will be formed later.

13099twf.ptd Page 10 1229875 V. After the description of the invention (5), please continue to refer to FIG. 2A. A collar oxide layer 1 1 6 is formed on the periphery of the oxide layer 1 1 4 in the middle of the deep trench 1 106, and the collar is oxidized. A second conductive layer 1 1 8 is formed in the deep trench 10 106 between the layers 1 1 6. The formation method is, for example, forming a collar oxide layer formed by a chemical vapor deposition method on the oxide layer formed after the above-mentioned tempering process, and then performing an etch-back to remove the oxide layer other than the 106 side wall of the deep trench. With collar oxide layer. Then, a conductive material layer is formed on the substrate 100, for example, a doped polycrystalline stone layer, and then a chemical mechanical polishing process is performed to remove the conductive material layer on the surface of the silicon nitride layer 104, and then Etching back is performed to leave a second conductive layer 1 1 8 in the middle of the deep trench 10 6. Thereafter, the oxide layer and the collar oxide layer are etched again to leave the oxide layer 114 and the collar oxide layer 116 on the periphery of the second conductive layer 118. Thereafter, referring to FIG. 2B, an insulating layer 1 2 0 is formed on the upper portion of the deep trench 1 106. The method for forming the insulating layer 120 is, for example, forming an insulating material on the substrate 100, such as a silicon oxide layer, so as to cover the silicon nitride layer 104 and filling the deep trenches 106. Then, Etching back is performed so that the remaining insulating material forms the aforementioned insulating layer 120. Then, a photoresist layer 1 2 2 is formed on the substrate 100. The photoresist layer 1 2 2 has an opening 1 2 4. The opening 1 24 is the same as the top of the deep trench 1 06, but is not aligned with the deep trench 1 06, so that the insulating layer 1 2 0 on the side of the deep trench is covered. The photoresist layer 1 2 2 can be patterned by exposing it with a photomask, and then developing to form the opening 1 2 4. The above photomask is the same pattern as the photomask used to define the deep trench 106, and when the exposure is performed, the photomask needs only to be slightly shifted to transfer the pattern to the photoresist layer. After development, openings 1 2 4 are formed, as shown in FIG. 3. Thereafter, please refer to FIG. 2C, and remove the exposed portions of the openings 1 2 4 of the photoresist layer 1 2 2

13099twf.ptd Page 11 1229875 V. Description of the invention (6) The insulating layer 1 2 0 exposes part of the second conductive layer 1 1 8, the collar oxide layer 1 1 6 and the oxide layer 1 1 4 and exposes them in the deep. An insulation layer 120a is left on one side of the trench 106. After that, the photoresist layer 122 is removed. After that, referring to FIG. 2D, a single-sided buried band 126 is formed on the other side of the deep trench 106. In this step, a conductive material layer can be formed on the substrate 100 to cover the insulating layer 12 a, the second conductive layer 1 1 8 not covered by the insulating layer, the collar oxide layer 1 1 6 and the oxide layer 1 1 4. Then, the conductive material layer is etched back to expose the insulating layer 120a, and a single-sided buried tape 126 is formed on the other side of the deep trench 106 to complete the fabrication of the internal electrode of the capacitor. Thereafter, referring to FIG. 2E, the pad oxide layer 102 and the silicon nitride layer 104 are removed. Then, an isolation layer 1 2 8 is formed in the deep trench 106, and then a gate dielectric layer 130, a gate conductor layer 140, and a source / drain region 150 are formed on the substrate 100 according to the above. According to the embodiment, in the method for forming a single-sided buried tape in the present invention, the insulating layer is partially removed, and then the conductive material is filled to form it. When the insulation layer is partially removed, the lithography process is performed with a photomask having the same pattern as the deep trench. During exposure, the deep trench pattern on the photomask is slightly offset from the deep trench formed in the substrate. The purpose can be achieved, therefore, the control of its stacking is very easy, and the process steps are very simple, and there is no scattering effect. On the other hand, since there is a gate between two adjacent trench capacitors in the present invention, the substrate below the gate has enough space to manufacture a larger-sized capacitor. Therefore, the method of the present invention can be used to manufacture The next generation of deep trench capacitors meets the needs of miniaturization.

13099twf.ptd Page 12 1229875 V. Description of the invention (7) In addition, since the deep trench has an insulating layer when forming the isolation layer, its height and width are relatively low, and there is no problem of hole formation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

13099twf.ptd Page 13 1229875 Brief Description of Drawings Figure 1 A-1 C is a sectional view showing the manufacturing process of a conventional deep trench capacitor. 2A-2E are cross-sectional views illustrating a manufacturing process of a memory element having a trench capacitor according to an embodiment of the present invention. Fig. 3 is a top view of Fig. 2B. Schematic mark description:

2, 1 00: substrate 3, 10 2: pad oxide layer 6, 10 6: deep trench 8, 10 8: doped region 1 0, 1 1 0: dielectric layer 1 2, 1 8, 2 0 : Conductive layer 16, 1 1 6: collar oxide layer 2 2, 1 0 4: nitride nitride layer 2 4: amorphous silicon layer 2 4 a: doped amorphous silicon layer 2 6: unilateral ion implantation 27 1.28: Isolation layer 28: Hole

112, 118126: conductive layer 1 1 4: oxide layer 1 2 0, 1 2 0 a: insulating layer 1 2 2: photoresist layer

13099twf.ptd Page 14 1229875 Brief description of the drawing 124 Opening 126 Single-side buried tape 130 Gate dielectric layer 140 Gate conductor layer 150 Source / >

13099twf.ptd Page 15

Claims (1)

1229875 VI. Scope of patent application 1. Provided in the Yu Yu electric layer; the Yu Yu layer and the deoxidized layer on the edge of the insulating layer. 2. A method for manufacturing the deep, deep, deep, deep, deep and deep collar oxygen removal part to expose the base of the deep ditch covered by the deep; the bottom layer of the ditch of the bottom ditch; the formation layer of the ditch in the ditch; A method for manufacturing the capacitor of the type that covers the trench, the method includes: forming a deep trench; forming a doped region at the peripheral edge of the lower part and the bottom part; forming a dielectric layer at the peripheral edge of the lower side part and the bottom part; A first conductive middle portion is formed between the dielectric layers at the bottom to form a collar oxide layer; a second conductive layer is formed between the collar oxide layers; an insulating layer is formed on the upper portion to cover the second conductive edge layer, so that Part of the second conductive layer, part of the collar, and the upper part form a single-sided buried band to cover the second conductive layer and the collar oxide layer and expose the deep trench capacitor described in item 1 of the absolute range The step of removing a part of the insulation layer includes: if applying for a patent, the first cover layer is formed on the substrate, the first cover layer has a first opening, and the deep trench is removed. The pattern of the first opening and the top of the deep trench is not the same, so that part of the insulating layer is exposed; the insulating layer exposed by the first opening of the curtain layer but the first cover is removed from the first cover Curtain layer 13099twf.ptd Page 16 1229875_ VI. Scope of patent application 3. The method for manufacturing a deep trench capacitor as described in item 2 of the scope of patent application, wherein the insulation layer exposed from the opening of the first cover layer is removed The method is dry etching. 4. The method for manufacturing a deep trench capacitor according to item 2 of the scope of patent application, wherein the method of forming the deep trench in the substrate comprises: sequentially forming a pad oxide layer and a silicon nitride layer on the substrate. Forming a second cover screen layer on the substrate, the second cover screen layer having a second opening, the pattern of the second opening is the same as that of the first opening of the first cover screen layer, and the exposed portion is exposed; The silicon nitride layer; and etching the silicon nitride layer exposed by the opening, the pad oxide layer and the substrate underneath to form the deep trench. 5. The method for manufacturing a deep trench capacitor according to item 1 of the scope of patent application, wherein the method of forming the insulating layer on each of the deep trenches includes: forming an insulating material layer on the substrate to cover the substrate And filling the deep trench; and etching back the insulating material layer to form the insulating layer. 6. The method for manufacturing a deep trench capacitor according to item 1 of the scope of patent application, wherein the method of forming the single-sided buried strip on the upper part of the deep trench includes: forming a conductive material layer on the substrate to cover The insulating layer, the second conductive layer and the collar oxide layer that are not covered by the insulating layer; and etch back the conductive material layer to expose the insulating layer to form the single-sided buried tape. 13099twf.ptd Page 17 1229875 VI. Patent application method for manufacturing a memory element with a deep trench capacitor The method includes providing a deep trench based on the deeper than the deeper base; forming a deep trench in the bottom; a trench A doped region is formed at the lower edge of the bottom and the periphery of the bottom; a dielectric layer is formed at the lower side wall of the trench and the periphery of the bottom; a first conductive layer is formed between the lower part of the trench and the bottom of the trench and deeper than each of the trenches A collar oxide layer is formed in the middle of the trench; a conductive layer is formed between the collar oxide layer in the deep trench and the oxide layer on the collar removal portion is exposed on the deep insulation layer and the base layer is covered by the base layer and the base electrode. 8. The memory element as described includes: an insulating layer is formed on the upper part of the deep trench to cover the second oxide conductive layer; the insulating layer is divided so that part of the second conductive layer and part of the collar come out; the trench A single-sided buried band is formed on the upper part to cover the second conductive layer and the collar oxide layer that are not covered by the cover; a gate dielectric layer is formed on the bottom; a gate dielectric layer is formed on the gate dielectric layer Step plurality of electrode conductors on both sides of the source substrate and patterning the gate layer is formed in the range of item 7 patenting of a method for manufacturing a deep trench capacitor, wherein the portion of the insulating layer removed; patterned gate conductor layer 13099twf.ptd Page 18 1229875-There is a layered curtain cover-the first layer of the curtain cover-the first shape of the upper bottom and the foundation of the foundation to apply for the special application, but six, "the layer with the same edge phase", the shape comes to the picture The lulu ev of the top of the trousers of the trousers of the trousers must not open the ditch, the deep part, the part, and the mouth, so that the floor opens, and the curtain covers the ditch, the deep part, and the Haikou δ ancient mouth. Except for the items described in the previous section and the detailed description of capacitor-type electrical trenches 8. The first layer of curtains covers the first section of the special application, which should be removed. The layer law curtain engraved with the surname in one form should be used in addition to the removal of the Chinese side of the law. The layer law margin party made the exposed part of the system to make a note of the yuan. Yuan Remembrance of 1 note Fan Li specially invited the Chinese-made French-made container-containing electric trench-type deep canal. The trench is formed in a deep shape with a base and a bottom. The forming order of the pads is based on the bottom: including the second and the second D of the package that have the same layer-shaped curtain cover in France. The first layer of the curtain and the first cover of the cover-shaped second image are opened. Bottom of the base, the mouth of the second party to the next and cut in layers. The deep and exposed shape of the nitrogen channel of the chemical canal is the reason why; οJ layer open bottom crushed the second base, the nitrogen should be etched by the oxygen removal etch pad to expose the bare 1It 1 note The deep grooves in the trenches on the canals can be formed into electrical forms. The deep grooves in the canals have deep grooves. Each of the items described in Section 7 should be filled in. Fan Li specially invited the application made by the French to fill in the foundation and cover it with Layer material edge insulation-: This layer is enclosed in a rectangular base, and the edge insulation layer should be formed with the layer material and edge insulation. 13099twf.ptd Page 19 1229875 VI. Application for patent scope 1 2. The method for manufacturing a memory element with a deep trench capacitor as described in item 7 of the scope of patent application, wherein the single trench is formed on the upper part of the deep trench The method of forming includes: forming a conductive material layer on the substrate to cover the insulating layer, the second conductive layer and the collar oxide layer not covered by the insulating layer; and etch back the conductive material layer to make the The insulating layer is exposed to form the single-sided buried tape. 1 3. The method for manufacturing a memory element with a deep trench capacitor as described in item 7 of the scope of the patent application, wherein the single-sided buried band is formed on the upper part of the deep trench and the gate dielectric layer is formed on the substrate. Between the steps, a step of forming an isolation layer above the deep trench is further included. 13099twf.ptd Page 20