JPH02262825A - Controlling circuit for semiconductor chopper device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control circuit for a semiconductor chopper device in which two sets of chopper circuits alternately repeat chopping operations every cycle.

[Conventional technology]

As the main circuit diagram and the fault detection section circuit diagram of the control circuit of this type of conventional chopper device, the ones illustrated in FIG. 4 and FIG. 5, respectively, are known.

In FIG. 4, 1 is a DC power supply and 2 is a breaker.

In addition, the 2Mi chopper circuit surrounded by the dotted chain line in the figure is
The cylinder 1 and the second chopper circuit are hereinafter referred to as the cylinder 1 and the second chopper circuit, each of which is constructed by connecting a series connection of a reverse conduction type auxiliary thyristor 5, a commutation reactor 6, and a commutation capacitor 7 to the main thyristor 4, and Both circuits are connected in parallel through the circuit breaker 2 on their respective input and output sides, and are controlled by a control circuit 3 to alternately repeat the chopping operation. Further, 8 is a charging resistor for accelerating charging to the capacitor 7, 9 is a freewheel diode, 1
0 is a filter reactor, 11 is a filter resistor, 12 is a filter capacitor, and 13 is a load.

Next, in FIG. 5, 14 and 15 are first and second chopper failure detection circuits corresponding to the first and second chopper circuits, respectively, and the output voltages of the corresponding chopper circuits are input to the stop point. A chopper failure signal is output by the arc failure detection timer. 16 is the both failure detection circuit 14
an OR gate 17 which receives the output failure signals of and 15 as input;
is a monostable circuit that receives the output signal of the OR gate and outputs a gate lock signal for both the first and second chopper circuits, and the gate lock signal ensures that the chopper circuit is healthy for a certain period of time from the time of failure. The gate drive signal of the chopper circuit is locked to freeze its ignition and extinguishing operations, thereby ensuring a charge in the commutation capacitor 7 and preventing a commutation failure accident from spreading to the healthy chopper circuit.

Reference numeral 18 is an on-delay timer which delays the activation command for both the failure detection circuits 14 and 15 for a certain period of time.
This is to prevent erroneous failure detection during the period of unstable operation when starting the chopper device.

[Problem to be solved by the invention]

In a chopper device configured as described above, in which two sets of chopper circuits are connected in parallel and the chopping operation is repeated alternately, if one chopper circuit fails in commutation, the failed chopper circuit is disconnected from the main circuit and the remaining healthy chopper circuit is disconnected from the main circuit. However, during the period from when a failure is detected until the failed chopper circuit is disconnected from the main circuit, the failed chopper circuit is fully conductive and a healthy chopper circuit cannot be maintained. A bypass circuit will be configured. As a result, the current flowing through the above-mentioned healthy chopper circuit decreases, and if the healthy chopper circuit repeats firing and extinguishing, the charge in the commutating capacitor becomes insufficient and even the healthy chopper circuit begins to flow. There is a possibility of flow failure. For this reason, a gate lock signal from the chopper failure detection circuit locks the gate drive signal of a healthy chopper circuit for a certain period from the time of failure, freezes the ignition and extinguishing operations, and secures the charge of the commutation capacitor. During the gate lock period, a healthy chopper circuit is in an extinguished state, and a timer for detecting ignition failure in the failure detection circuit starts operating. Therefore, if the operating time of the monostable circuit for gate locking is longer than the set time of the ignition failure detection timer, the failure detection circuit will erroneously detect the healthy chopper circuit as being in an ignition failure state. Therefore, in order to prevent this false detection, the operating time of the monostable circuit must be shorter than the set time of the failure detection timer. However, the commutating capacitor cannot be sufficiently charged in such a short period of time, and therefore, conventionally, as shown in FIG. Charging was completed within the lock period.

The installation of the charging resistor increases the size of the chopper device and increases the temperature inside the device due to resistance heat generation, resulting in an increase in cost due to these countermeasures.

In view of the above, an object of the present invention is to provide a control circuit for a chopper device that reliably prevents erroneous detection of a failure state as described above and eliminates the need for the charging resistor.

[Means to solve the problem]

In order to achieve the above object, the control circuit of the semiconductor chopper device of the present invention has two sets of chopper circuits connected in parallel, and the two sets of semiconductors repeat chopping operations alternately every cycle. In the chopper device, when a failure occurs in one of the chopper circuits, a failure detection signal is received from the failure detection circuit, and the above-mentioned operation is performed for a period sufficient to complete the required charging of the commutating capacitor of the other healthy chopper circuit. A means is provided to issue a command to stop the failure detection operation of the failure detection circuit in a healthy chopper circuit, or instead of a command to stop the failure detection operation of the failure detection circuit in the other healthy chopper circuit when one of the chopper circuits fails as described above. The gate lock operation of the chopper circuit on the fault side continues, and means is provided for issuing a failure detection operation stop command to each of the failure detection circuits in the two sets of chipper circuits for a period similar to the failure detection operation stop command. shall be.

[Effect]

According to the present invention, when either the first or second chopper failure detection circuit detects a failure, the failure detection operation of the remaining failure detection circuit is locked during the gate lock period. Therefore, the operation time of the monostaple circuit for gate locking can be set according to the charging time of the commutation capacitor without being restricted by the timer setting time of the failure detection circuit. 8 is also unnecessary.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 are circuit diagrams of a failure detection section of a chopper device control circuit showing an embodiment of the present invention, and FIG. 3 is an operation time chart of FIG. 2.

Note that in FIGS. 1 and 2, the same reference numerals are given to components having the same functions as in the prior art embodiment shown in FIG. 5.

In the circuit shown in FIG. 5, FIG. 1 shows two sets of two-man-powered AND gates 20 that share a gate lock signal and input the first or second chipper failure signal, and the output signals of both AND gates. A 2Mi off-delay timer 19 is provided as an input, and the outputs of the two timers are sent to the first and second chopper failure detection circuits 14 and 1, respectively.
This is input as a failure detection operation lock signal for 5.

Now, if the first chopper failure detection circuit 14 detects a failure, a first chopper failure signal is output. This failure signal is input to the monostable circuit 17 via the OR gate 16, and is output as a gate lock signal for a predetermined time (charging time of the commutating capacitor). Further, the first chopper failure signal and the gate lock signal are ANDed by an AND gate 20, and input to the second chopper failure detection circuit 15 via an off-delay timer 19 to lock its failure detection operation. Thereby, even if the second chopper circuit stops its operation until the commutation capacitor is completely charged, it is possible to prevent erroneously detecting a failure.

Next, in the circuit diagram shown in FIG. 5, FIG. 2 is provided with an AND gate 21 which receives the start command signal S1 and the gate lock signal St, and outputs the output signal of the AND gate when starting the chopper device as described above. The output signal S of the timer 18, the signal S, The pattern of change between and 82 is as shown in the time chart shown in FIG.

As shown in FIG. 3, when the chopper circuit failure occurs, the output signal S8 of the monostable circuit 17 in the case of FIG. During this period, the failure detection operation is locked as described above.

〔Effect of the invention〕

According to the present invention, since the gate lock time can be set according to the charging time of the commutating capacitor without considering the timer time of the failure detection circuit, the charging resistor for accelerating charging of the commutating capacitor is removed from the main circuit. can do. This makes it possible to downsize and reduce the cost of the chopper device, and by removing an extra heat source, it is possible to prevent adverse effects on other devices in the device. Furthermore, by providing a timer that uses the gate lock signal as one of its operating conditions, even if the control system and controlled system cannot follow up immediately after the gate lock is released.

By appropriately setting the timer time according to the characteristics of the control system and controlled system, it is possible to prevent false detection of failures due to disturbances or delays in the output waveform immediately after gate lock is released, and more stable control is possible. becomes.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing an embodiment of the present invention, and FIG.
The figure is the operation time chart of Figure 2, Figure 4 is the main circuit diagram of the chopper device using the conventional control circuit, and Figure 5 is an example of the conventional technology corresponding to Figures 1 and 2. FIG. 1... DC power supply, 2... Breaker, 3... Control circuit, 4... Main power supply risk, 5... Auxiliary power supply risk,
6... Commutation reactor, 7... Commutation capacitor, 8
...charging resistor, 9...freewheel diode,
10... Filter reactor, 11... Filter resistor, 12... Filter capacitor, 13... Load,
14...First chopper failure detection circuit, 15...Second
Chopper failure detection circuit, 16...OR gate, 17.
... Mono staple circuit, 18... On-delay timer, 19... Off-delay Figure 3

Claims (1)

[Claims] 1) In a semiconductor chopper device that includes two sets of chopper circuits connected in parallel and in which the two sets of circuits repeat chopping operations alternately every cycle, a failure occurs in one of the chopper circuits. In response to a failure detection signal from the failure detection circuit, the failure detection operation of the failure detection circuit in the other healthy chopper circuit is stopped for a period sufficient to complete the required charging in the commutating capacitor of the other healthy chopper circuit. A control circuit for a semiconductor chopper device, comprising means for issuing a command. 2) In the control circuit for the semiconductor chopper device according to claim 1, when one chopper circuit fails, instead of issuing a failure detection operation stop command of the failure detection circuit in the other healthy chopper circuit, the gate of the failure side chopper circuit is sent. A semiconductor chopper device characterized in that the locking operation continues and means is provided for issuing a failure detection operation stop command to each of the failure detection circuits in the two sets of chopper circuits for a period similar to the failure detection operation stop command. control circuit.