JPH0956177A - Gate signal generation circuit for power converter - Google Patents

Abstract

(57) [Summary] [Structure] Means for feeding back the actual firing state of the semiconductor element forming each arm to the gate signal generating circuit,
Means 1 for comparing the gate signal and the element firing state to detect the mismatch, means 2 for detecting the logic abnormality of the element firing state, means 3 for detecting the logic abnormality of the gate signal, and these detected Means for passing the signal of the other phase to the gate signal generation circuit of the other phase, and when the gate signal of the own phase or the other phase does not match the element firing state, or the logic abnormality of the element firing state or the logic abnormality of the gate signal occurs. Means for masking the gate signal command to turn off or turn on all the elements, and means 52 for ensuring a non-wrap period and a minimum pulse width for the masked signal are provided. [Effect] With the PWM inverter device or the converter device, it is possible to detect an element failure and a failure of the gate signal generating circuit itself, and further to perform a protective operation immediately when the failure occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter for converting direct current into alternating current or alternating current into direct current, and more particularly,
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit that generates a gate signal that controls the conduction state of semiconductor elements that form a PWM (pulse width modulation) inverter and converter.

[0002]

[Prior art]

(1) According to Japanese Patent Laid-Open No. 3-218253, the gate signal of the semiconductor element is fed back to the control device side, and the signal is compared with the gate signal transmitted to the gate of the semiconductor element. A power conversion device that separately detects whether the semiconductor element is abnormal or the gate signal transmission path is abnormal is described.

(2) In Japanese Unexamined Patent Publication No. 61-293180, when a failure of at least one GTO thyristor among the GTO thyristors constituting the power converter is detected, another normal GTO thyristor is forcibly extinguished. At the same time, it is stated that the protective operation is for the purpose of forcibly igniting all the GTO thyristors when the anode current of the GTO thyristors reaches an overcurrent during the forced extinction.

[0004]

In the gate signal generating circuit of the PWM inverter device or the converter device, each semiconductor element (hereinafter, referred to as an element) of the power converter according to the switching command received from the PWM controller.
Generates a gate signal that controls the firing state of the.

In a PWM inverter device or converter device, a set in which one of a plurality of elements connected in series is selectively turned on (for example, a set of a positive arm and a negative arm of a two-level inverter, or a three-level inverter). Outer positive and inner negative arms and inner positive and outer negative arms. For the above set, when one element turns on and the other turns on, turning off one gate signal and turning on the other gate signal simultaneously turns on the turn-off time of the element and the turn-on time. Since it is longer, there is a period in which both elements are conducting at the same time, which short-circuits the power supply. In order to prevent this, first turn off the gate signal of one element, then wait for a time longer than the turn-off time of the element, and then turn off the element that was on until now, and then turn off the other element. Turn on the gate signal. This difference in the change timing of the gate signal is called a non-wrap period or dead time.

The gate signal generation circuit performs an operation of ensuring a non-wrap period for the gate signal of each element. However, as in the examples of the prior art, the element failure detection function and protection when a failure occurs are provided. Some also have functions.

In the conventional gate signal generating circuit such as the prior art (1), in order to secure the non-wrapping period, after the gate signal of one element is turned off and a predetermined time has passed, the other is irrespective of the actual ignition state of the element. The gate signal of the device was turned on. In this method, even if the gate signal of the element that was initially on was changed to off, but it actually remained on due to an element failure, the gate of the other arm will not be released after a certain period of time. To turn the signal on,
There was a problem of causing an arm short circuit failure in which the power supply is short-circuited.

In the prior art (2), when the device cannot be turned off due to the device failure, the protection operation is performed and the inverter device is stopped. On the contrary, when the device cannot be turned on, the operation is performed without protection. Therefore, there is a possibility that a healthy element may be destroyed due to overcurrent. Also, depending on the capacity of the inverter device and the type of semiconductor element, the operation of turning on all the elements when an overcurrent occurs during the protection operation cannot be said to be appropriate protection, and rather causes a healthy element destruction. It can cause.

Furthermore, none of the conventional techniques checks the gate signal output from the gate signal generating circuit, and even if a gate signal of a logic that causes an arm short circuit due to a failure of the gate signal generating circuit itself is output. , It is not possible to detect it and take protective action.

Although not described in the prior art,
If the gate signal is changed again after the gate signal is changed and before the state of the element is determined, the element may be destroyed.

An object of the present invention is a power conversion device for converting alternating current and direct current by using a semiconductor element. First, the ignition state fed back from the element is monitored, and the element cannot be turned off due to the element failure. In either case or when it cannot be turned on, the protection operation is immediately performed when a failure is detected.Second, the failure of the gate signal generation circuit itself is detected and the protection operation is performed when the failure occurs. Securing a minimum pulse width and non-wrap period for the gate signal in both cases of operation and protection operation during failure, and generating a gate signal that does not lead to direct destruction of the element. The purpose of the present invention is to provide a gate signal generation circuit that minimizes damage to an element at the time of failure by performing a protective operation according to the type of the element that constitutes the device at the time of occurrence.

[0012]

In order to achieve the above object, the present invention provides a means for feeding back an actual firing state of a semiconductor element forming each arm to a gate signal generating circuit, a gate signal and an element firing state. To detect the discrepancy, a means to detect an abnormality in the logic of the element firing state, a means to detect an abnormality in the logic of the gate signal, and a gate signal of another phase generated from these detected failure signals. A means for passing the signal to and from the circuit, and to turn off or turn on all elements when there is a mismatch between the self-phase or other-phase gate signal and the element firing state, a logic abnormality in the element firing state, or a logic abnormality in the gate signal. Further, means for masking the gate signal command and means for ensuring a non-wrap period and a minimum pulse width for the masked signal are provided.

[0013]

[Function] Detects the mismatch between the gate signal and the element firing state,
By masking the gate signal command so as to turn off all the elements when a mismatch occurs, the protection operation can be performed and the inverter device can be stopped when the elements cannot be turned off or cannot be turned on. Further, by providing the means for detecting the logical abnormality of the element firing state, the protection operation can be performed without waiting for the detection of the disagreement, especially when an emergency such as an arm short circuit is required.

By providing means for detecting an abnormality in the logic of the gate signal, a logic which cannot occur when the gate signal generating circuit is normal is detected, and a gate signal command is issued to turn off all the elements when the abnormality occurs. By masking, the power conversion device can be stopped even when an abnormality occurs in the gate signal generation circuit.

By arranging the gate signal rationality ensuring means for ensuring the non-wrap period and the minimum pulse width in the gate signal in the final stage of the gate signal generating circuit, in any case regardless of normal operation or failure, It is possible to secure the minimum pulse width and the non-wrap period in the gate signal.

[0016]

Embodiments of the present invention will be described with reference to FIGS. 1 to 11 by taking a case of a three-phase two-level inverter as an example.

FIG. 1 shows a gate signal generating circuit for one phase, which receives a gate signal command S and generates gate signals Gp and Gn for controlling the switching states of the respective elements forming the positive and negative arms in accordance with the gate signal command S. In addition, element firing states FGp, F
Gn is received, and this is used for failure detection and reflected in the protection operation. Here, the subscript p corresponds to the positive arm, and n corresponds to the negative arm.

The logic of S is that the positive arm is on when S = 1,
Negative arm off, defined as positive arm off and negative arm on when S = 0. The logic of Gp and Gn is Gp (G
It is defined as off when n) = 1 and on when Gp (Gn) = 0. The logic of FGp and FGn is the same as that of Gp and Gn.

An example of the structure of the gate signal / element firing state mismatch detection means 1 is shown in FIG. The logic of the disagreement signal CFD is
It is defined as 1 when normal and 0 when disagreement occurs. Basically, the gate signal of each element and EXNOR of the element firing state should be taken to detect the discrepancy between the two signals, but in an actual device, the element firing state returns after the gate signal is output. Since there is a time lag before they arrive, a short-term mismatch is tolerated, and it is considered that an element failure has occurred when a mismatch that continues beyond the allowable period occurs.

In FIG. 2, EXNOR of the gate signal Gp of the positive arm and the element firing state FGp, and the gate signal Gn of the negative arm and the element firing state FGn of EXNOR are first taken, and these are taken as the mismatch period counters (n bits) 11p and 11n. Clear signal. As a result, when a mismatch occurs, a period in which the outputs Q0 to Qn of the mismatch period counters 11p and 11n continue to be mismatched is obtained. The period during which the mismatch is allowed is set in advance in the mismatch allowable period setting means 12, and this value is compared with the outputs of the mismatch period counters 11p and 11n. The output of the comparator is defined as 0 when the value of the mismatch period counter becomes larger than the mismatch allowable period set value. When the comparator output becomes 0, it is latched 14p, 14
By storing them in n and taking the AND of these, the mismatch signal CFD becomes 0 when a mismatch occurs in either the positive or negative arm. It is assumed that the outputs of the latches 14p and 14n do not return to 1 once they have become 0 until a reset signal is given.

Next, FIG. 3 shows a structural example of the element firing state logic abnormality detecting means 2. In the case of a two-level inverter, the positive and negative arms are turned on at the same time, that is, the element firing states FGp and FGn.
Is a prohibited item (arm short circuit). Therefore, the OR of FGp and FGn is taken, and when this output becomes 0, this is stored in the latch 21, and this is made the firing state logic abnormality occurrence signal FFAIL. FFAI
The logic of L is defined as 1 when it is normal and 0 when a logic error occurs. Once the FFAIL signal has become 0, it does not return to 1 until the reset signal is input. FF
With the AIL signal, it is possible to immediately detect a failure such as an arm short circuit that must be protected immediately without waiting for the detection of the discrepancy between the gate signal and the element firing state, and perform the protection operation.

Next, FIG. 4 shows a configuration example of the gate signal logic abnormality detecting means 3. The configuration is the same as that of the element firing state logic abnormality detection means 2 of FIG. When the logic of the gate signal is checked by this means and a logic that cannot occur under normal conditions is detected, the gate signal logic abnormality occurrence signal GFAIL is set to 0. Once the GFAIL signal also becomes 0, it does not return to 1 until the reset signal is input. As a result, the failure of the gate signal generating circuit itself can be detected, and the protection operation can be performed when the failure occurs.

FIG. 5 shows an example of the configuration of the failure protection logic setting means 4. The gate signal command S is separated into the gate signal commands for the positive and negative arms, and the mismatch signal CFD, element firing state logic abnormality occurrence signal FFAIL, gate signal logic abnormality occurrence signal GF
When either of the AIL becomes 0, the gate signal command is masked so that the elements of the positive and negative arms are turned off, thereby performing the protection operation of stopping the inverter device.

The minimum required function of the gate signal generating circuit is to secure a non-wrap period when the gate signal is turned on and to secure a minimum pulse width of the gate signal. Generally, the turn-off time of the switching element is longer than the turn-on time. Therefore, when the gate signals Gp and Gn are simultaneously switched with the change of the gate signal command S, the element of one arm is turned on before the element of the other arm is turned on. , Arm short circuit occurs. Therefore, the gate signal of the element that has been in the on state until then is turned off, and the gate signal of the other element is turned on after a time Td sufficient for actually turning off the element has elapsed. Td is called a non-wrap period or dead time. Further, if the gate signal is changed once and then changed again before the state of the element is determined, the element may be destroyed. Therefore, for the gate signal, sufficient times Ton and Toff for ensuring the element state are secured. Ton is called the minimum on-time, Toff is called the minimum off-time, and the two are collectively called the minimum pulse width.

FIG. 6 shows an example of the structure of the gate signal reasonableness ensuring means 5 for ensuring the non-wrap period and the minimum pulse width. It comprises a non-lap period ensuring means 51 and a minimum pulse width ensuring means 52. The correspondence between the input and the output of the non-lap period securing means 51 is as shown in FIG. That is, when the gate signal is changed from the off state to the on state, the non-lap period Td is set and then the on state is set. On the contrary, when transitioning from the on state to the off state, the off state is immediately set. The correspondence between the input and output of the minimum pulse width securing means 52 is as shown in FIG. That is, when the ON pulse width is shorter than the preset minimum ON time Ton, the width of the ON pulse is extended to Ton. As for the off pulse width, the minimum off time T
Extend to off (= Ton + 2Td). By arranging the gate signal rational ensuring means at the final stage of the gate signal generating circuit, the non-wrap period and the minimum pulse width can be ensured in the gate signal in any case regardless of the normal operation and the protection operation. .

An embodiment obtained by expanding the embodiment of FIG. 1 is shown in FIG. In the embodiment of FIG. 1, the protection operation is performed for each phase individually, and the protection operation is performed immediately after the detection of the failure phase, but the other phases continue to operate as they are, and thus three-phase imbalance occurs. there's a possibility that. Therefore, as shown in FIG. 9, means for passing the mismatch signal, the element firing state logic abnormality occurrence signal, and the gate signal logic abnormality occurrence signal to the gate signal generation circuit of the other phase is provided, and the failure protection logic setting means 4A shown in FIG. As in the configuration example of 1, the gate signal command is masked so that all the elements are turned off even when an abnormality occurs in another phase, and the inverter device is stopped.

The above is the basic embodiment. For example,
In a large-capacity inverter device that uses GTO thyristors as elements, the short-circuit current when an arm short circuit occurs is limited to a certain value by the anode reactor of the GTO thyristor, so all elements are turned on and one phase of the short-circuit current flows. A protective action to avoid concentration is also conceivable. Since the arm short circuit can be detected by the logic abnormality in the element firing state, in such a case, all elements are protected by the failure protection logic setting means 4A as shown in FIG. 11 when the element firing state logic abnormality occurs. Mask the gate signal command to turn on.

On the other hand, in the case of an inverter using an element having no anode reactor, such as an IGBT, there is no limiter for the short-circuit current. If all the elements are turned on when the arm is short-circuited as in the configuration example of FIG. Since there is a possibility of destruction, it is desirable to configure the failure protection logic setting means as shown in FIG.

According to the above-described embodiment, the protection operation is performed before the overcurrent is reached in both the case where the element cannot be turned off due to the element failure and the case where the element cannot be turned on.
Detect the failure of the gate signal generation circuit itself, perform protection operation when a failure occurs, regardless of normal operation or failure,
In any case, ensure a minimum pulse width and non-wrap period for the gate signal, and perform a protective operation according to the type of semiconductor element that constitutes the device to minimize damage to the element even in the event of a failure. Is possible. Although the embodiment of the two-level inverter has been described here, the present invention is also applicable to a multi-level inverter or converter having three or more levels.

[0030]

EFFECTS OF THE INVENTION In a power conversion device for converting direct current into multi-phase alternating current using a semiconductor element, or vice versa, it is possible to prevent an element from failing to turn on or not turning on due to an element failure. Performing protective action before reaching the current, detecting failure of the gate signal generating circuit itself,
Protective action when a failure occurs, ensuring minimum pulse width and non-wrap period in the gate signal in any case, regardless of normal operation or failure, protective action according to the type of elements that make up the device By performing the above, it becomes possible to minimize the damage of the element even in the case of a failure.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a gate signal / element firing state mismatch detection means.

FIG. 3 is an explanatory diagram of a device firing state logic abnormality detecting means.

FIG. 4 is an explanatory diagram of a gate signal logic abnormality detecting means.

FIG. 5 is an explanatory diagram of a failure protection logic setting means.

FIG. 6 is an explanatory diagram of a gate signal rationality ensuring means.

FIG. 7 is an explanatory diagram showing an operation of a non-wrap period ensuring unit 51.

FIG. 8 is an explanatory diagram showing the operation of the minimum pulse width securing means 52.

FIG. 9 is a block diagram of another embodiment of the present invention.

FIG. 10 is an explanatory diagram of a failure protection logic setting means 4A.

FIG. 11 is another explanatory diagram of the failure protection logic setting means 4A.

[Explanation of symbols]

1 ... Gate signal / element firing state mismatch detection means, 2 ... Element firing state logic abnormality detection means, 3 ... Gate signal logic abnormality detection means, 4, 4A ... Fault protection logic setting means, 5 ... Gate signal rational Securing means.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mutsuhiro Terunuma 1070 Igemo, Hitachinaka City, Ibaraki Prefecture Stock Company Hitachi Ltd. Mito Plant

Claims (8)

[Claims] 1. A power converter for converting direct current into multi-phase alternating current using a semiconductor element or vice versa,
In a logic circuit that generates a gate signal that controls the conduction state of each semiconductor element according to a gate signal command given from a PWM control device, a gate signal that controls the conduction state of the semiconductor element by binary value of ON or OFF; Means for transmitting the actual ignition state of the semiconductor element between the gate signal generation circuit and the gate drive circuit of each of the semiconductor elements in binary of ON or OFF, and the gate signal and the actual point for each of the semiconductor elements. The failure of the semiconductor element is detected by monitoring the combination of the gate signal / element firing state mismatch detection means for detecting the failure of the semiconductor element by comparing the arc states, and the logic of the firing state of each semiconductor element. An element firing state logic abnormality detecting means for detecting, and a gate signal of each semiconductor element which is an output of the gate signal generating circuit. Gate signal logic abnormality detecting means for detecting a failure of the gate signal generating circuit by monitoring a combination of logics, and a gate signal command as an input, and referring to the results of each failure detection, all the semiconductors when a failure occurs A non-wrap period and a minimum pulse width are secured for the failure protection logic setting means for performing a protection operation by masking the gate signal command to turn the element off or on and the output of the failure protection logic setting means. A gate signal generation circuit for a power conversion device, comprising: 2. The gate signal / element firing state non-coincidence detection means according to claim 1, wherein the means for detecting the non-coincidence occurrence of each gate signal and the corresponding element firing state are provided with a period for allowing the non-coincidence in advance. A means for setting, a counter for counting the period in which a mismatch occurs, a comparator for comparing the output of the counter and the set value of the mismatch allowable period setting means, and detecting that the mismatch period exceeds the set value. A gate signal generating circuit having a latch for storing the output of the comparator, and means for outputting a mismatch signal when the mismatch period exceeds a set value in any of the semiconductor elements. 3. The gate according to claim 1, wherein the element firing state logic abnormality detecting means detects a combination of logics of element firing states that cannot occur during normal operation and stores a result thereof. Signal generation circuit. 4. The gate signal generation circuit according to claim 1, wherein the gate signal logic abnormality detecting means detects a combination of gate signal logics that cannot occur during normal operation and stores a result thereof. 5. The failure protection logic setting means according to claim 1, wherein all of the semiconductor elements are activated by generation of any one of a mismatch signal, an element firing state logic abnormality occurrence signal and a gate signal logic abnormality occurrence signal. A gate signal generation circuit having means for masking a gate signal command so as to turn off. 6. The mismatch signal which is the output of the gate signal / element firing state mismatch detection means, and the element firing state logic abnormality occurrence signal which is the output of the element firing state logic abnormality detection means according to claim 1. And a means for transferring the gate signal logic abnormality occurrence signal output from the gate signal logic abnormality detecting means to the gate signal generation circuit of another phase. 7. The failure protection logic setting means according to claim 6, wherein the self-phase mismatch signal, the element firing state logic abnormality occurrence signal, the gate signal logic abnormality occurrence signal, or the other phase mismatch signal or element point. A gate signal generation circuit provided with means for masking a gate signal command so as to turn off all semiconductor elements when either an arc state logic abnormality occurrence signal or a gate signal logic abnormality occurrence signal is generated. 8. The failure protection logic setting means according to claim 6, wherein either a self-phase mismatch signal or a gate signal logic abnormality occurrence signal, or another phase mismatch signal or a gate signal logic abnormality occurrence signal is generated. Gate signal to turn off all semiconductor elements, and to turn on all semiconductor elements by the occurrence of the self-phase element firing state logic abnormality occurrence signal or the other phase element firing state logic abnormality occurrence signal. A gate signal generation circuit having means for masking a command.