JPH02250440A - Frame synchronizing multiplex processing system - Google Patents

Abstract

PURPOSE:To attain batch processing of a multi-frame by applying synchronization protection with the result of collation of a pattern collation section and a frame pattern of a pattern type storage section, outputting multi-frame number information of a received data, storing the received data based on the multi- frame number and reading the data in the timing managed internally. CONSTITUTION:A frame synchronizing detection section 7 applies synchronizing detection based on frame bit location information a3 from a multiplex processing control section 1, pattern type information a7 from a pattern type storage section 2, and pattern detection information b3 from a pattern collation section 6 and outputs a multi-frame number b3 representing to which order number of multi- frame a frame bit during reception and a data bit corresponding thereto corresponds to a multi-frame phase management buffer 8. The multi-frame phase management buffer 8 stores a reception data (b) according to the multi- frame number b4 and the frame bit location information a4. Thus, batch processing is attained to plural multi-kind of multi-frame.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frame synchronization method, and more particularly to a frame synchronization multiplexing method that can perform batch processing when a plurality of different types of separate multiframes for subrate multiplexing are required. .

[Conventional technology]

-i, the frame synchronization method is a method in which frames are synchronized by inserting a fixed pattern of frame bits on the transmitting side and detecting the pattern on the receiving side.

Conventionally, since there was no need to use many types of frame patterns, the transmitting side device and the receiving side device were made to have the same structure. Therefore, conventionally, a single pattern of frame bits has been inserted and transmitted, and this single pattern has been used on the receiving side to achieve frame synchronization.

[Problem to be solved by the invention]

In the conventional frame synchronization method, frame synchronization is achieved using a single frame pattern, which has the following drawbacks.

Today, when high-speed digital lines are frequently used, multi-frames for subrate multiplexing with various types of patterns are used, and it is no longer possible to handle them with the same equipment.

Therefore, when performing frame synchronization of the multi-frames in the same device, a new dedicated frame synchronization circuit must be installed in the device, which poses a problem in terms of cost.

The purpose of this invention is to solve the above-mentioned conventional problems.
An object of the present invention is to provide a frame synchronization multiple processing method that can collectively process multiple frames having many types of frame patterns.

[Means to solve the problem]

The frame synchronization multiple processing method of the present invention includes a pattern type storage section that stores various frame patterns indicating frame bit positions of each multiframe on the receiving side, and a frame pattern of the pattern type storage section and a frame pattern of received data. A frame synchronization detection section that performs synchronization protection processing based on the matching results of the pattern matching section and the frame pattern of the pattern type storage section and outputs multi-frame number information of received data; It is equipped with a multi-frame phase management buffer that stores received data based on the multi-frame number from the transmitter and reads it out at internally managed timing, and a frame bit insertion unit that inserts various frame patterns into the transmitted data on the transmitter side. It is characterized by having

〔Example〕

Embodiments of the invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a frame synchronous multiple processing system according to an embodiment of the present invention.

In the frame-synchronized multiple processing system of this embodiment, there are a multiple processing control section 1, a pattern type storage section 2, which constitutes the receiving side. Pattern information output unit 3. Multi-stage shift register section 4. Bit mask gate 5, pattern matching section 6. It includes a frame synchronization detector 7, a multiframe phase management buffer 8, and a frame bit inserter 9 provided on the transmitting side.

The multiprocessing control unit l receives frame bit position information a, ~a
4 respectively in the pattern type storage section 2. Multi-stage shift register section 4. Frame synchronization detection unit 7゜has the function of sending out a phase management control signal a and multiframe phase information a6 to the multiframe phase management buffer 8 and frame bit insertion unit 9, respectively. .

The pattern type storage unit 2 stores various frame patterns corresponding to each multi-frame. This pattern type storage unit 2 stores pattern type information a corresponding to frame bit position information a when frame bit position information al indicating the frame bit position of a multi-frame is input.

It has a function to output.

The pattern information output unit 3 outputs pattern information a8 and unnecessary bit mask information a of the received multi-frame based on the pattern type information a from the pattern type storage unit 2 to the pattern matching unit 6. It has a function of sending data to the bit mask gate 5.

The multi-stage shift register section 4 receives the received data b based on the frame bit position information a2 from the multiprocessing control section 1.
Multi-dimensionally manage data indicating frame bit positions from among them, and create a multi-frame data string of frame bit positions.
It has a function of outputting to the bit mask gate 5.

The bit mask gate 5 generates a data string based on the unnecessary bit mask information from the pattern information output section 3.

It has a function of masking unnecessary bits and outputting the masked data as pattern b2 of received data.

The pattern matching section 6 has a function of matching the pattern b2 of the received data with the pattern information a8, and outputting pattern detection information S indicating the matching result to the frame synchronization detection section 7.

The frame synchronization detection unit 7 receives frame bit position information a3+ from the multiprocessing control unit 1 and pattern type information a? from the pattern type storage unit 2. + Synchronization is detected based on the pattern detection information b3 from the pattern matching unit 6, and the multiframe number b4 indicating the multiframe number of the received frame bit and the corresponding data bit is stored in the multiframe phase management buffer. It has a function to output to 8.

The multi-frame phase management buffer 8 receives the multi-frame number ba from the frame synchronization detection section 7, the frame bit position information a4 from the multi-processing control section 1, and the received data b.
It has a function of inputting the received data b according to the multi-frame number b4 and the frame bit position information a4. Moreover, the multi-frame phase management buffer 8 is
It has a function of managing and outputting the phase of received data b based on the phase management control signal a from the multiprocessing control unit 1.

On the other hand, the frame bit insertion unit 9 on the transmitting side has a function of inserting a frame pattern into the transmission data C based on the multiframe phase information a6 from the multiprocessing control unit l and the pattern type information a from the pattern type storage unit 2. has.

Next, the frame synchronization operation shown in this embodiment will be explained.

The received data b received on the receiving side is input to the multi-stage shift register section 4 and the multi-frame phase management buffer 8.

At the same time as the received data b is input to the multi-stage shift register section 4, the frame bit position information a1 to a4 is sent from the multi-processing control section 1 to the pattern type storage section 2. Multi-stage shift register section 4. Frame synchronization detection unit 7. - sent to the multiframe phase management buffer 8;

The multi-stage shift register section 4 receives input received data b.
and frame bit position information a2, a multi-frame stage data string indicating the frame bit position is output to the bit mask gate 5.

In parallel with this, the pattern type storage section 2 outputs pattern type information a7 corresponding to the frame focus position information a1 to the pattern information output section 3 and the frame synchronization detection section 7.

The pattern information output unit 3 outputs pattern type information a? It sends pattern information a8 corresponding to , to the pattern matching section 6, and outputs unnecessary bit mask information a to the bit mask gate 5.

The multi-frame stage data string S is masked with unnecessary bits by the bit mask gate 5 and pattern b! and input it to the pattern matching section 6.

Pattern bt of received data b and pattern information a.

The pattern matching section 6 performs matching with the pattern matching section 6, and pattern detection information indicating the result is output to the frame synchronization detection section 7.

The frame synchronization detection unit 7 detects the synchronization of the received data b based on the pattern detection information S, the pattern type information a, and the frame bit position information a3, and transfers the multiframe number b4 of the received data b to the multiframe phase management buffer. Output to 8.

The multi-frame phase management buffer 8 stores the received data b based on the multi-frame number b4 and the frame bit position information a4, performs phase management on the received data b based on the phase management control signal as, and outputs the result.

On the other hand, when inserting frame bits into a multiframe on the transmitting side, the frame bit insertion unit 9 inserts a frame into a frame into a multiframe based on the multiframe phase information a corresponding to the transmission data C and the pattern type information a. This is accomplished by inserting a pattern.

〔Effect of the invention〕

Since this invention is configured as described above, it is possible to perform batch processing on a plurality of multi-type multi-frames, and as a result, a new synchronization circuit can be added even when facing devices other than the same device. The effect is that it is not necessary.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a frame synchronous multiple processing system according to an embodiment of the present invention. 1...Multi-processing control unit 2...Pattern type storage unit 3...Pattern information output unit 4...Multi-stage shift register unit 5...Bit mask gate 6...Pattern matching unit 7...Frame synchronization detection unit 8...Multi-frame phase management buffer 9...
・Frame bit insertion part

Claims (1)

[Claims] (1) On the receiving side, a pattern type storage section that stores various frame patterns indicating the frame bit position of each multiframe, and a pattern matching section that matches and compares the frame pattern of the pattern type storage section and the frame pattern of the received data. , a frame synchronization detection section that performs synchronization protection processing using the matching result of this pattern matching section and the frame pattern of the pattern type storage section, and outputs multiframe number information of received data; and a multi-frame phase management buffer for storing received data based on the timing and reading it out at internally managed timing, and a frame bit insertion section on the transmitting side for inserting various frame patterns into the transmitted data. Frame synchronized multiple processing method.