JP3010634B2 - Frame synchronous multiplex processing - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization system, and more particularly to a frame synchronization multiplexing system capable of collectively processing a plurality of different multi-frames for subrate multiplexing. .

[Conventional technology]

In general, the frame synchronization system is a system in which frame bits of a fixed pattern are inserted on the transmission side and pattern detection is performed on the reception side to synchronize frames.

Conventionally, since it was not necessary to use various types of frame patterns, the transmitting device and the receiving device had the same structure. Therefore, conventionally, a single pattern of frame bits is inserted and transmitted, and the receiving side uses this single pattern to perform frame synchronization.

[Problems to be solved by the invention]

In the conventional frame synchronization method, frame synchronization is achieved by a single frame pattern, and thus has the following disadvantages.

Nowadays, high-speed digital lines are frequently used, and multi-frames for sub-rate multiplexing having various types of patterns are used, and the same device cannot cope with them.

Therefore, when the same device is used to synchronize the multi-frames, a dedicated frame synchronization circuit must be newly installed in the device, which causes a problem in terms of cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a frame synchronous multiplex processing method capable of collectively processing multi-frames having various types of frame patterns in order to solve the above-mentioned conventional problems.

[Means for solving the problem]

In the frame synchronous multiplexing processing method of the present invention, a pattern type storage unit for storing various frame patterns indicating a frame bit position of each multi-frame on a receiving side, a frame pattern of the pattern type storage unit and a frame pattern of received data are stored. A pattern matching unit that performs matching and comparison; a frame synchronization detection unit that performs synchronization detection of received data based on the matching result of the pattern matching unit and the frame pattern of the pattern type storage unit and outputs multiframe number information of the received data; A multi-frame phase management buffer for storing received data based on the multi-frame number from the synchronization detection unit and reading out the data at an internally managed timing, and a frame bit input unit that inserts various frame patterns into the transmission data on the transmission side. It is characterized by having.

〔Example〕

 An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a frame synchronous multiplex processing method according to an embodiment of the present invention.

In the frame synchronous multiplex processing method of this embodiment,
A multiplex processing control unit 1, a pattern type storage unit 2, a pattern information output unit 3, and a multi-stage shift register unit constituting the receiving side
4, a bit mask gate 5, a pattern matching unit 6, a frame synchronization detection unit 7, a multi-frame phase management buffer 8, and a frame bit insertion unit 9 provided on the transmission side.

The multiplex processing control unit 1 includes frame bit position information a _{1 to} a ₄
Are the pattern type storage unit 2 and the multi-stage shift register unit, respectively.
4. The frame synchronization detecting section 7 sends the frame management control signal a ₅ and the multi-frame phase information a ₆ to the multi-frame phase management buffer 8, and sends them to the multi-frame phase management buffer 8 and the frame bit inserting section 9, respectively. Has functions.

The pattern type storage unit 2 stores various frame patterns corresponding to each multi-frame. This pattern type storage unit 2 has a function of outputting the pattern type information a ₇ that if you enter a frame bit position information a ₁ showing a frame bit position of the multi-frame corresponding to the frame bit position information a _1.

The pattern information output unit 3 sends the received multi-frame pattern information a ₈ and the unnecessary bit mask information a ₉ to the pattern matching unit 6 and the bit mask gate 5 based on the pattern type information a ₇ from the pattern type storage unit 2. It has the function of sending.

The multi-stage shift register unit 4 receives the received data b based on the frame bit position information a ₂ from the multiplex processing control unit 1.
Out of the data indicating the frame bit position is multifaceted, and the multi-frame stage data string b _{1 of the} frame bit position is managed.
Is output to the bit mask gate 5.

Bitmask gate 5 has a function of outputting a data string b ₁ as the pattern b ₂ of the received data is unnecessary bits masked by unnecessary bit mask information from the pattern information output unit 3.

Pattern matching unit 6 has a function of outputting the pattern detection information b ₃ indicating the comparison result matches a pattern b ₂ and the pattern information a ₈ of the received data to the frame synchronization detection unit 7.

The frame synchronization detection unit 7 detects synchronization based on frame bit position information a ₃ from the multiplex processing control unit 1, pattern type information a ₇ from the pattern type storage unit 2, and pattern detection information b ₃ from the pattern matching unit 6. And outputs to the multi-frame phase management buffer 8 a multi-frame number b ₄ indicating the number of the frame bit being received and the corresponding multi-bit data bit.

The multi-frame phase management buffer 8 receives the multi-frame number b ₄ from the frame synchronization detector 7, the frame bit position information a ₄ and the received data b from the multiplex processing controller 1, and receives the multi-frame number b ₄ and the frame bit. It has a function to continue to store the received data b according to the position information a _4. The multi-frame phase control buffer 8 has a function of outputting to manage the phase of the received data b based on the phase OAM signals a ₅ from multiprocessing control unit 1.

On the other hand, the transmission-side frame bit insertion unit 9 inserts a frame pattern into the transmission data c based on the multi-frame phase information a ₆ from the multiplex processing control unit 1 and the pattern type information a ₇ from the pattern type storage unit 2. Has functions.

Next, a frame synchronization operation according to this embodiment will be described.

The received data b received on the receiving side is input to the multi-stage shift register unit 4 and the multi-frame phase management buffer 8.

Multi-stage shift register unit at the same time as the input of the received data b to 4, the frame bit position information a ₁ ~a ₄ are each pattern type storage unit 2 from the multiprocessing control unit 1, a multi-stage shift register unit 4, the frame synchronization detector 7. The data is sent to the multi-frame phase management buffer 8.

The multi-stage shift register unit 4 outputs a multi-frame stage data sequence b ₁ indicating the frame bit position to the bit mask gate 5 based on the input received data b and the frame bit position information a ₂ .

This pattern type storage unit 2 in parallel outputs pattern type information a ₇ corresponding to the frame bit position information a ₁ in the pattern information output section 3 and the frame synchronization detection unit 7.

The pattern information output unit 3 sends the pattern information a ₈ corresponding to the pattern type information a ₇ to the pattern matching unit 6 and outputs the unnecessary bit mask information a ₉ to the bit mask gate 5.

The multi-frame stage data string b ₁ is subjected to unnecessary bit masking by the bit mask gate 5 and input to the pattern matching unit 6 as a pattern b ₂ .

Matching a pattern b ₂ and the pattern information a ₈ of the received data b is performed by the pattern matching unit 6, the pattern detection information b ₃ indicating the result is output to the frame synchronization detection unit 7.

The frame synchronization detection unit 7 performs synchronous detection of the received data b based on the pattern detection information b ₃ and the pattern classification information a ₇ and the frame bit position information a _3, received data b of the multi-frame number b ₄ multiframe phase Management buffer 8
Output to

In multi-frame phase management buffer 8 performs storage of the received data b based on the multi-frame number b ₄ and the frame bit position information a _4, by performing the phase control of the received data b based on the phase OAM signals a ₅ Output.

On the other hand, when the transmitting side inserts frame bits into a multi-frame, the frame bit inserting section 9 inserts a frame bit into the transmission data c based on the multi-frame phase information a ₆ and the pattern type information a ₇ corresponding to the transmission data c. This is achieved by inserting a pattern.

〔The invention's effect〕

Since the present invention is configured as described above,
Batch processing can be performed on a plurality of multi-type multi-frames, and as a result, there is an effect that it is not necessary to add a new synchronization circuit even when facing other than the same device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a frame synchronous multiplex processing method according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Multiprocessing control part 2 ... Pattern type storage part 3 ... Pattern information output part 4 ... Multi-stage shift register part 5 ... Bit mask gate 6 ... Pattern matching part 7 ... Frame synchronization detection part 8 ... ... Multi-frame phase management buffer 9 ... Frame bit insertion unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04J 3/06 H04L 7/08

Claims (1)

(57) [Claims] 1. A pattern type storage unit for storing various frame patterns indicating a frame bit position of each multi-frame on a receiving side, and a pattern matching unit for comparing and comparing a frame pattern of the pattern type storage unit with a frame pattern of received data. And a synchronization detection of the received data based on the matching result of the pattern matching unit and the frame pattern of the pattern type storage unit.
A frame synchronization detecting unit that outputs multi-frame number information of the received data; and a multi-frame phase management buffer that stores the received data based on the multi-frame number from the frame synchronization detecting unit and reads the data at an internally managed timing. A frame synchronous multiplexing processing method characterized in that the transmitting side is provided with a frame bit input unit for inserting various frame patterns into transmission data.