JPH02245736A - Liquid crystal display device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a liquid crystal display device, and particularly to an active matrix type liquid crystal display device using thin film transistors and the like.

[Conventional technology 1 Acty! - A matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is constantly driven (duty ratio 1.0), so compared to the so-called simple matrix method, which uses a time-division opening method, the active method has better co-contrast, especially in color. It is becoming an indispensable technology. A typical switching element is a thin film transistor (TPT). In a conventional active matrix liquid crystal display device, a silicon nitride film is formed directly on an ITO film (transparent conductive film), as disclosed in Japanese Patent Application Laid-Open No. 151516/1983. In addition, in the conventional method of manufacturing an active matrix liquid crystal display device, after forming the source electrode and drain electrode with an opaque conductive film, when a silicon nitride film is formed directly on the ITO film, the silicon nitride film Since the ITO film is formed in a reducing atmosphere, when forming the silicon nitride film, the ITO film is reduced and the adhesion between the ITO film and the silicon nitride film deteriorates. When water enters between the silicon film and a potential difference occurs between adjacent conductive films,
The conductive film is ionized and corroded. In addition, when a transparent pixel electrode made of an ITO film is provided after forming a source electrode and a drain electrode with an opaque conductive film, when forming the source electrode and drain electrode, the insulating film used as the gate insulating film is Since the surface is contaminated, the adhesion between the insulating film used as the gate insulating film and the transparent pixel electrode becomes poor, so when forming the transparent pixel electrode, the ITO film peels off along with the resist, damaging the transparent pixel electrode. This results in point defects, and the amount of side etching increases when forming the transparent pixel electrode, resulting in a reduction in the area of the transparent pixel electrode. This invention was made in order to solve the above-mentioned problems, and provides a method for manufacturing a liquid crystal display device in which the conductive film does not corrode, a liquid crystal display device in which point defects do not occur, and the transparent pixel electrode does not become small. The purpose is to provide. [Means for Solving the Problems] In order to achieve this object, the present invention provides a terminal and a connection with the terminal in an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode constitute one pixel. At least a part of the signal line is covered with an ITO film, and the edge of the silicon nitride film and the ITO film are covered with an ITO film.
An opaque conductive film is provided between the signal line covered with the film and the signal line. Further, in a method for manufacturing an active matrix type liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel, an insulating film used as a gate insulating film is provided, and the pixel is formed on the M edge film. After forming the electrodes, a source electrode and a drain electrode are formed using an opaque conductive film.

[Effect] In this liquid crystal display device, since an opaque conductive film is provided between the end of the silicon nitride film and the signal line covered with the ITO film, the ITO film covering the signal line is disposed at the end of the silicon nitride film. The membrane is never reduced. In addition, in this method of manufacturing a liquid crystal display device, after forming a pixel electrode on an insulating film, the source electrode and drain electrode are formed using an opaque conductive film, so it is possible to form the pixel electrode on a clean insulating film. Therefore, the adhesion between the insulating film and the transparent pixel electrode becomes good. 【Example】

Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to an active matrix color liquid crystal display device. In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section taken along the line ■B-IIB in FIG. 2A and the display panel. FIG. 2C is a cross-sectional view taken along the NC-NC cutting line in FIG. 2A. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged. (Pixel Arrangement) As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two adjacent video signal lines (drain signal line or vertical signal line). Signal line)
Within the intersection area with DL (within the area surrounded by four signal lines)
It is located in Each pixel includes a thin film transistor TPT, a pixel electrode ITO1, and an additional capacitor Cadd. A plurality of scanning signal lines GL extend in the column direction and are arranged in the row direction. The video signals gDL extend in the row direction, and a plurality of video signals gDL are arranged in the column direction. (Overall panel cross-sectional structure) As shown in FIG. 2B, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate 5UBI side with respect to the liquid crystal layer LC, and a color filter is formed on the upper transparent glass substrate 5UB2 side. FIL and a light-shielding black matrix pattern BM are formed. The lower transparent glass substrate 5UBI side is, for example, 1.1 [m garden]
It is made up of a certain thickness. The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates 5UBI and 5UB2 where external lead wiring is present. The right side shows a cross section of the right edge portion of the transparent glass substrates 5UBI and 5UB2 where no external lead wiring is present. The sealing material SL shown on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and is configured to seal the entire periphery of the transparent glass substrates 5UBI and 5UB2 excluding the liquid crystal sealing opening (not shown). is formed along. The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UB2 is at least at one location. The lower transparent glass substrate 5U is made of silver paste material SIL.
It is connected to the external lead wiring formed on the BI side. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SDI, and drain electrode SD2 described above. Alignment films 0RII and 0RI2, transparent pixel electrode ITO,
Common transparent pixel electrode ITO1 protective film psv1 and PSV
2. Is each insulating film GI fake? It is formed inside the sealing material SL. The polarizing plate POL includes a lower transparent glass substrate 5UBI and an upper transparent glass substrate 5UB.
2 is formed on the outer surface of each of the two. The liquid crystal LC has a lower alignment film 0R that sets the direction of the liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL. The lower alignment film 0RII is formed on the protective film PSVI on the side of the lower transparent glass substrate 5UBI. On the inside (liquid crystal side) surface of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) ITO2 and an upper alignment film 0RI2 are sequentially laminated. This liquid crystal display device has a lower transparent glass substrate 5UBl side,
Each layer on the upper transparent glass substrate 5UB2 side is formed separately, and then the upper and lower transparent glass substrates 5UJ31 and 5UB2 are stacked on top of each other, and the liquid crystal LC is sealed between them, thereby assembling. (Thin Film Transistor TFT) The thin film transistor TPT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large. The thin film transistor TPT of each pixel has three
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TPT2, and TFT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPTI to TFT3 mainly includes a gate electrode GT, a gate insulating film GI, an i-type (intrinsic, 1ntrins)
ic, a pair of source electrodes SDI and drain electrodes SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. It is expressed by fixing the source and the other as the drain. (Gate Electrode GT) As shown in detail in FIG. 4 (a plan view depicting only layers g1, g2, and AS in FIG. 2A), the gate electrode GT is connected in a vertical direction from the scanning signal line GL (FIG. 2A and It is constructed in a shape that protrudes upward (in FIG. 4) (branched into a T-shape). The gate electrode GT is connected to the thin film transistors TPT1 to TFT.
It is configured to protrude to each formation region of No. 3. The gate electrodes GT of each of the thin film transistors TPTI to TFT3 are integrated (as a common gate electrode)
The scanning signal line OL is formed continuously with the scanning signal line OL. The gate electrode GT is formed of a single-layer first conductive film g1 so as not to form a large step in the formation region of the thin film transistor TPT. The first conductive film g1 is, for example, a chromium (Cr) film formed by sputtering. It is formed to a film thickness of about 100 mm. This gate electrode GT is shown in FIGS. 2A, 2B and 4.
As shown in the figure, it is formed to be thicker than the semiconductor layer AS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is installed below the substrate 5UBI, this opaque Cr gate electrode GT
becomes a shadow, and the semiconductor layer AS is not irradiated with backlight light, making it difficult for the conductive phenomenon caused by light irradiation, that is, deterioration of the off-characteristics of TPT, to occur. Note that the original size of the gate electrode GT is the minimum required size to span between the source/drain electrodes SDI and SD2 (including the alignment margin between the gate electrode and the source/drain electrodes), and the size of the channel width The depth length that determines W is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance g. The size of the gate electrode in this embodiment is of course larger than the original size mentioned above. Considering only the gate and light shielding functions of the gate electrode GT, the gate electrode GT and the scanning signal line GL may be integrally formed in a single layer, and in this case, Si is contained as an opaque conductive material. A1. Pure A1. A1 or the like containing Pd can be selected. (Scanning Signal Line GL> The scanning signal line GL is composed of a composite film consisting of a first conductive film g1 and a second conductive film g2 provided on top of the first conductive film g1. g1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1.The second conductive film g2 is
For example, an aluminum film formed by sputtering is used to have a thickness of about 1,000 to 5 sooc. The second conductive film g2 reduces the resistance value of the scanning signal line GL,
The structure is such that it is possible to increase the signal transmission speed (improve the writing characteristics of pixel information). Further, in the scanning signal line GL, the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gradual step shape on its side wall. Further, as shown in FIGS. 1A to 1C, the end of the scanning signal line GL is connected to the gate terminal GTM, and the terminal GTM and the portion of the scanning signal line GL connected to the terminal GTM are first conductive. The first conductive film g1 is formed between an end of a protective film psvl (description will be described later) and the scanning signal line GL. An island pattern is provided with a second conductive film d2 (description will be described later) made of chrome on which the source electrode SDI and drain electrode SD2 are formed.Therefore, at the end of the protective film PSVI, the scanning signal line GL Since the first conductive film d1 covering the protective film PSVI is not reduced, the adhesion between the scanning signal line GL and the protective film PSVI is good at the end of the protective film PSVI. Since moisture does not enter between the two, even if a potential difference occurs between adjacent scanning signal lines GL, the first conductive film g1 and the first conductive film d1 will be ionized and the scanning signal line GL will corrode. (Gate insulating film GI) The insulating film GI is used as a gate insulating film for each of the thin film transistors TPTI to TFT3.
is formed in the upper layer of the gate electrode GT and the scanning signal line GL. The insulating film GI is formed by, for example, plasma CVD.
A silicon nitride film formed using the above method is used to form a film with a thickness of about 3000 [layers]. (Semiconductor Layer AS) As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel formation region for each of the thin film transistors TPTI to TFT3 divided into a plurality of parts. i-type semiconductor layer A
S is formed of an amorphous silicon film or a polycrystalline silicon film, and is formed to have a film thickness of about 1800 C. This i-type semiconductor layer AS is made of Si by changing the components of the supplied gas.
, N, are formed in the same plasma CVD apparatus following the formation of the gate insulating film GI, without being exposed to the outside from the apparatus. Also, P for ohmic contact
N+ layer d doped with . (Fig. 2B) is similarly formed continuously to a thickness of about 400 [people]. Thereafter, the lower substrate 5UBI is taken out of the CvD apparatus, and by photoprocessing techniques, the N+ layer DO and the i layer AS are patterned into independent islands as shown in FIGS. 2A, 2B, and 4. Ru. As shown in detail, it is also provided between the scanning signal line GL and the video signal line DL at an intersection (crossover section). The intersection i-type semiconductor layer AS is configured to reduce short circuits between the scanning signal #GL and the video signal IADL at the intersection. (Source/drain electrode SDI, 5D2) The source electrode SDI and drain electrode SD2 of each of the thin film transistors TPTI to TFT3 divided into a plurality of parts are shown in FIG. 2A, FIG. 2B, and FIG. Membrane d1~
As shown in detail in the plan view (plan view depicting only the third conductive film d3), they are provided separately on the i-type semiconductor layer AS. Each of the source electrode SDI and drain electrode SD2 is
The second conductive film d2 and the third conductive film d3 are sequentially stacked one on top of the other from the lower layer side in contact with the N" type semiconductor layer dO. The second conductive film d2 and the third conductive film d3 of the source electrode SDI are , and the drain electrode SD2.The second conductive film d2 is formed using a chromium film formed by sputtering, and has a film thickness of 500 to 1000 [people] (in this example,
The film thickness is approximately 600 [people]. The chromium film is
If the film thickness is made thicker, the stress will increase, so 20
The film thickness is formed within a range of about 0.00 [persons]. The chromium film has good contact with the N+ type semiconductor layer do. In the chromium film, the aluminum of the third conductive film d3 to be described later is N.
It forms a so-called barrier layer that prevents diffusion into the +-type semiconductor layer do. In addition to the chromium film, the second conductive film d2 includes a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (
MoSi,,TiSi,,TaSi,,WSi,)ji
It may be formed by After patterning the second conductive film d2 by photo processing, the N4'' type semiconductor layer do is removed using the same photo processing mask or using the second conductive film d2 as a mask. In other words, the N4'' type semiconductor layer do remains on the i type semiconductor layer AS. The portion of the N+ type semiconductor layer do other than the second conductive film d2 is removed by self-line.At this time, the N+ type semiconductor layer do is etched to remove its entire thickness, so it becomes an i-type semiconductor. The layer AS is also slightly etched on its surface, but the degree of etching can be controlled by the etching time.The third conductive film d3 is then formed by aluminum sputtering to a film thickness of 3000 to 5500 [layers] (in this embodiment). The aluminum film is formed to a film thickness of about 3,500 [people]. Compared to a chromium film, the aluminum film has less stress and can be formed to a thicker film thickness. The third conductive film d3 is formed of an aluminum film containing silicon (Si) and copper (Cu) as additives in addition to the aluminum film. The second conductive film d2 of the source electrode SDI, the drain electrode SD
2, each of the second conductive films d2 is connected to the upper third conductive film d.
Compared to No. 3, it is much more inward (into the channel area). In other words, the second conductive film d in these parts
2 is a thin film transistor T regardless of the third conductive film d3.
The configuration is such that the gate length of the PT can be defined. The source electrode SDI is made of a transparent conductive film (Indui 臘-Ti).
n-Oxide
Film thickness of 000 to 2000 [people] (in this example, 12
It is connected to a transparent pixel electrode ITOI (explanation will be given later) formed of a first conductive film d1 having a film thickness of approximately 0.00 [people]. The source electrode SDl has a step shape (
The source electrode SDI is configured along a step corresponding to the sum of the thickness of the N" type semiconductor layer dO and the thickness of the i type semiconductor layer As. Specifically, the source electrode SDI is Layer A
A second conductive film d2 is formed along the step shape of S, and a transparent pixel electrode I is formed above the second conductive film d2.
The third conductive film d3 is formed with a smaller size on the side connected to the TOI. The third source electrode SDI
The conductive film d3 is configured to overcome the step shape of the i-type semiconductor layer AS because the chromium film of the second conductive film d2 cannot be formed thickly due to increased stress and cannot overcome the step shape of the i-type semiconductor layer AS. There is. In other words, the third conductive film d3
The step coverage is improved by forming it thickly. Since the third conductive film d3 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). The transparent pixel electrode ITO1 is configured to be connected to the second conductive film d2. The first conductive film d1 and the second conductive film d2 not only have good adhesion but also have a small step shape at the connecting portion between the two, so they can be reliably connected, and the first conductive film d1 and Since there is no contact with the third conductive film d3, the third conductive film d3 is not oxidized. (Pixel electrode ITOI) The transparent pixel electrode ITOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrodes (divided transparent pixel electrodes) are divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the transparent pixel electrodes E1 to E3. Each of the transparent pixel electrodes E1 to E3 is a thin film transistor TPT.
is connected to the source electrode SDI of. Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area. In this way, by dividing the thin film transistor TPT of one pixel into a plurality of thin film transistors TPT1 to TFT8, and connecting each of the plurality of divided transparent pixel electrodes E1 to E3 to each of the plurality of divided thin film transistors TPTI to TFT3. Even if a divided portion (for example, TFT1) becomes a point defect, it is no longer a point defect when viewed from the perspective of the entire pixel (TFT2 and TFT3 are not defective), so the probability of point defects can be reduced. , it can also make defects more difficult to see. Further, by configuring each of the divided transparent pixel electrodes E1 to E3 of the pixel to have substantially the same area, each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode I
Each liquid crystal capacitor (Cpix
) can be made uniform. (Protective film PSVI) Thin film transistor TPT and transparent pixel electrode protective film p
svx is mainly formed to protect the thin film transistor TPT from moisture, etc., and a material with high transparency and good moisture resistance is used. The protective film PSVI is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and
Formed with a film thickness of about [a person]. (Light-shielding film BM> A shielding film BM is provided on the upper substrate 5UB2 side to prevent external light (light from above in FIG. 2B) from entering the i-type semiconductor layer AS used as a channel formation region. The pattern is as shown by the hatching in Fig. 6. In addition, Fig. 6 shows the ITO film layer d3, filter layer FIL, and light shielding film B in Fig. 2A.
It is a plan view depicting only M. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film that has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300 mm. Therefore, the common semiconductor layer AS pole GT of TPTI~3 forms a sandwich, and that part is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel as shown by the hatched area in FIG. There is. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM is
2. Light shielding for semiconductor layer AS and black matrix
It has two functions. In addition, the backlight is attached to the 5UB2 side, and the 5UBI
can also be set to the 1516 side (externally exposed side). (Common Electrode I To 2) The common transparent pixel electrode ITO2 is connected to the lower transparent glass substrate 5U.
Opposing the transparent pixel electrode ITO1 provided for each pixel on the BI side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode ITOI and the common electrode IrO2. This common transparent pixel electrode ITO2 has a common voltage Vco
It is configured so that the meal is applied. Common voltage Vc
om is a low-level drive voltage Vdwin and a high-level drive voltage Vdax applied to the video signal line DL.
It is the intermediate potential between (Color Filter FIL) The color filter FIL is configured by coloring a dyed base material made of a resin material such as an acrylic resin with a dye. The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (Fig. 7), and is colored differently (Fig. 7 shows the third conductive film layer d3 and the color filter layer FIL in Fig. 3). The R, G, and H filters are each 45 @ 135 degrees with a cross hatch), and the color filter FIL is connected to the pixel electrode ITO1 (E1 to E3) as shown in Figure 6. ), and the light shielding film BM is formed to be thick so as to cover all of the color filters FIL.
and is formed inside the peripheral portion of the pixel electrode ITO1 so as to overlap with the edge portion of the pixel electrode ITOI. Color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate 5UB2, and the dyed base material other than the red filter forming area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R.The same process is then performed to sequentially form a green filter G and a blue filter B. (Protective Film PSV2) The protective film PSV2 is provided to prevent the dyes that have been used to dye the color filters FIL into different colors from leaking into the liquid crystal Lc. The protective film PSV2 is, for example,
It is made of transparent resin material such as acrylic resin or epoxy resin. (Pixel Arrangement) As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line GL extends, and pixel columns Xi, X2°X3 ．． X4. ...
It consists of each of the following. Each pixel column XI, X2. X3
．． X4. . . . have thin film transistors TFT1 to TFT3 and transparent pixel electrodes E1 to E3 arranged in the same position. In other words, odd pixel row Xi
,X3. For each pixel, the thin film transistors TPTI to TFT3 are arranged on the left side, and the transparent pixel electrode E is placed on the left side.
1 to E3 are arranged on the right side. Odd pixel row Xi. X3. Each adjacent even-numbered pixel column X in the row direction
2. X4. Each pixel of ... is an odd pixel column X1
,X3. ... are connected to the video signal line DL.
It is composed of pixels that are symmetrical and upside down with respect to the direction in which it extends. That is, 1 pixel column x2° x4. ...
Each pixel includes thin film transistors TPT1 to TF.
The arrangement position of T3 is arranged on the right side, and the arrangement position of transparent pixel electrodes E1 to E3 is arranged on the left side. Then, pixel row X2. X4. Each pixel in pixel rows Xi, X3 . For each pixel of...
They are shifted (shifted) by half a pixel interval in the column direction. In other words, each pixel interval of one pixel column X is 1.0, (1,
0 pitch), the next pixel column X has a pixel interval of 1.0, and is shifted by 0.5 pixel interval (0.5 pitch) from the previous pixel column X in the column direction. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. As a result, as shown in FIG. 7, the pixels in the previous pixel row Pixels on which same-color filters are formed (for example, pixel row
4) are spaced apart by 1.5 pixel intervals (1.5 pitch), and the RGB color filters FIL are arranged in a triangle. Color filter F
The RGB triangular arrangement structure of the IL can improve the mixing of each color, and therefore can improve the resolution of a color image. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. (Equivalent circuit of the entire display panel) Both circuits of this liquid crystal display device are shown in FIG. X x G + X x + I G v... is a video signal line DL connected to the pixel in which the green filter G is formed. XiB, Xi+lB, . . . are video signal lines DL connected to the pixels in which the blue filter B is formed. Xi+IR, Xi+2R, . . . are video signal lines DL connected to pixels in which the red filter R is formed. These video signal lines DL are selected by a video signal drive circuit. Yi is a scanning signal line GL that selects the pixel column X1 shown in FIGS. 3 and 7. Similarly, Yi+l, Yi+2. . . , each of pixel rows X2 . X3. . . . is a scanning signal line GL that selects each of the following. These scanning signal lines GL. Connected to the vertical scanning circuit. (Structure of Additional Capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 overlaps the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TPT. It is bent into an L shape. As is clear from FIG. 2C, this superposition is caused by the transparent pixel electrodes E1 to E3.
A storage capacitor element (electrostatic capacitor element) Cadd is configured in which each of the two electrodes is used as one electrode PL2, and the adjacent scanning signal line OL is used as the other electrode PLI. The dielectric film of this storage capacitor element Cadd is an insulating film GI used as a gate insulating film of the thin film transistor TPT.
It is composed of the same layer. As is clear from FIG. 4, the storage capacitor Cadd is formed in the widened portion of the first layer g1 of the gate line GL. Note that the portion of the layer g1 that intersects with the drain line DL is made thin in order to reduce the probability of short circuit with the drain line. Each of the transparent pixel electrodes E1 to E3 and the capacitor electrode line (gl
), similar to the source electrode SDI,
An island region made up of the first conductive film d1 and the second conductive film d2 is provided so that the transparent pixel electrode ITO1 is not disconnected when climbing over the step shape. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITOI. (Additional capacitance Cadd circuit and its operation) The circuit of the pixel shown in FIG. 2A is shown in FIG. 9. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between the source electrode SDI. The dielectric film of the parasitic capacitance Cgs is an insulating film GI*C
pix is a liquid crystal capacitance formed between the transparent pixel electrode ITOI (FIX) and the common transparent pixel electrode TO2 (COM). The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC1 protective film PSv.
1 and alignment films 0RII and ○RI2. Vlc is a midpoint potential. The storage capacitor element Cadd works to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. This state can be expressed by the formula ΔVlc=(Cgs/(Cgs+Cadd+Cpix)
)) becomes XΔVg. Here, ΔVlc represents a change in the midpoint potential due to ΔVg. This change ΔVie causes a DC component applied to the liquid crystal, but the larger the holding capacitor Cadd is, the smaller the value can be. In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens. As mentioned above, since the gate electrode GT is enlarged to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SDI and SD2 increases, and therefore the parasitic capacitance Cgs increases, and the midpoint potential Vlc decreases. This has the opposite effect of becoming more susceptible to the influence of the gate (scanning) signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix<Cadd< 8・Cpix), 8 to 32 times the superposition capacitance Cgs (8・Cgs<Cadd<
Set to a value of about 32 Cgs). (Connection method of additional capacitance Cadd electrode line) As shown in FIG. ) Connect to IrO2. As shown in FIG. 2B, the common transparent pixel electrode ITO2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, some of the conductive layers (gl and g2) of this external lead wiring are formed in the same manufacturing process as the scanning signal line OL. As a result, the final stage capacitor electrode line OL can be easily connected to the common transparent pixel electrode TO2. Alternatively, as shown by the dotted line in FIG. 8, the final stage (first stage) capacitor electrode line OL may be connected to the first stage (final stage) scanning signal line GL. Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring. (DC component offset by additional capacitance Cadd scanning signal) This liquid crystal display device uses the DC offset method (DC
As shown in FIG. 10 (time chart), the DC component applied to the liquid crystal LC can be further reduced by controlling the drive voltage of the scanning signal line DL. In FIG. 10, Vi is the drive voltage of an arbitrary scanning signal line GL, Vi+1 is the drive voltage of the next scanning signal line OL, aVee is the low-level drive voltage Vdm1n applied to the scanning signal line GL, and Vdd is High-level drive voltage V d applied to the scanning signal line OL
rmax. Each time 1=1. Voltage change amount Δv1 to ΔV of midpoint potential Vlc (see FIG. 9) at ~1°,
becomes as follows. Δv1=-(Cgs/C)・v2 ΔV,=+(Cgs/C)(V1+V2)-(Cadd
/ C)・V 2 Δv, = −(Cgs/C)・vl + (Cadd/C)・(V 1 + V 2 ) Δ
v, =-(Cadd/C)・vl However, total capacitance of pixels: c =: Cgs+ Cp
ix ten Cadd Here, if the active voltage applied to the scanning signal line GL is sufficient (see below)

(See note), the DC voltage applied to the liquid crystal LC is ΔV, +ΔV, = (CadclV 2- Cgs-V
1)/C, so Cadd-v2=CgS-
If it is vl. The DC voltage applied to the liquid crystal LC becomes O. [Note] Time 1. ．． 1. The change in the scanning line Vi affects the midpoint potential Vlc, but during the period from t2 to t3, the midpoint potential Vlc is made the same potential as the video signal potential through the signal line Xi (sufficient writing of the video signal). . The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period).Therefore, when calculating the direct current applied to the liquid crystal, the period t1 to t3 is approximately determined by the potential applied to the liquid crystal. Can be ignored, the potential immediately after TPT is turned off,
In other words, it is sufficient to consider the influence of transient times at times t1 and t. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, the DC cancellation method uses the drive voltage applied to the storage capacitance element Cadd and the next stage scanning signal line OL (capacitance electrode line) to push up the drop caused by the pull-in of the midpoint potential v1c by the superimposed capacitance Cgs. The DC component applied to the LC can be made extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor Cadd may be increased accordingly. Next, a method for manufacturing a liquid crystal display device according to the present invention will be explained. First, a film thickness of 1100 [people] was deposited on a lower transparent glass substrate 5UBI made of 7059 glass (product name).
A first conductive film g1 made of chromium is provided by sputtering. Next, the first layer of the scanning signal line GL, the gate electrode GT, and the gate electrode GTM are selectively etched by photolithography using a ceric ammonium nitrate solution as an etching solution.
, a drain terminal, a part connected to the drain terminal of the video signal line, and an electrode PL1 of the storage capacitor element Cadd. Next, after removing the resist with stripper 5502 (trade name), 02 ashering is performed for 1 minute. Next, aluminum-silicon-palladium (or aluminum-palladium, aluminum-silicon , aluminum-silicon-titanium, aluminum-silicon-copper, etc.)
is provided by sputtering. Next, the second layer of the scanning signal line GL is formed by selectively etching the second conductive film g2 by photolithography using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etching solution. Next, SF is applied to the dry etching equipment. After gas is introduced to remove residues such as silicon, the resist is removed. Next, ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD equipment to form a silicon nitride film with a film thickness of 3500 μm, and the plasma CVD
Introducing silane gas and hydrogen gas into D equipment, the film thickness was 18.
After forming an i-type amorphous silicon film with a thickness of 00 to 2200 mm, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus to form an N+ type silicon film with a film thickness of 400 mm. Next, SF as a dry etching gas,
N+ type silicon film by photo-etching technology using CCQ4,
An i-type semiconductor layer AS is formed by selectively etching the i-type amorphous silicon film. Next, after removing the resist, the silicon nitride film is selectively etched by photolithography using SF as a dry etching gas, thereby forming an insulating film GI. Next, after removing the resist, the film thickness was 1200 [people].
A first conductive film d1 made of an ITO film is provided by sputtering. Next, the transparent pixel electrode IT01 is selectively etched by photolithography using a mixed acid of hydrochloric acid and nitric acid as an etching solution.
Then, the top layer of the gate terminal GTM and the drain terminal is formed. Next, the resist is removed and baked at 230° C. in an N gas atmosphere, and then a second conductive film made of chromium with a film thickness of 600 to 1200 [mm], for example 600 [mm] is formed.
2 is formed by sputtering. Next, by selectively etching the second conductive film d2 using photolithography, the first layer of the video signal line DL, source electrode SD1, and drain electrode SD2 is formed, and the scanning signal line GL is
, an island pattern is formed on the video signal line DL at a position that should become the end of the protective film PSVI. Next, before removing the resist, CO2, SF,
The N+ type semiconductor layer do is formed by selectively etching the N+ type silicon film. Next, after removing the resist, the film thickness is 3000 to 5500.
A third conductive film d3 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. is provided by sputtering, for example, 3,500 [people]. next,
By selectively etching the third conductive film d3 using photolithography, the second layer of the video signal line DL, source electrode SD1, and drain electrode SD2 is formed. Next, after removing the resist, ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus, and the film thickness is reduced to 1[-].
A silicon nitride film is provided. Next, by selectively etching the silicon nitride film using photolithography using SF as a dry etching gas, the protective film P
Form SVI. In this method of manufacturing a liquid crystal display device, after forming the transparent pixel electrode ITO1 on the insulating film GI, the second conductive film d
2. Source electrode SD1.2 by third conductive film d3. Since the drain electrode SD2 is formed, the transparent pixel electrode ITO1 can be formed on the clean insulating film GI. Therefore, the adhesion between the insulating film GI and the transparent pixel electrode ITO1 is good, so when forming the transparent pixel electrode ITO1, the first conductive film d1 is not peeled off together with the resist, and the transparent pixel electrode ITO1 is not damaged. Since the transparent pixel electrode ITo1 is not formed, there will be no point defects, and the amount of side etching will hardly occur when forming the transparent pixel electrode ITo1.
The area of the transparent pixel electrode ITO1 does not become smaller. As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the gist thereof. Of course there is. For example, in the above embodiment, an inverted staggered structure is shown in which gate electrode formation→gate insulating film formation→semiconductor layer formation→source/drain electrode formation, but the present invention can also be applied to a staggered structure in which the vertical relationship or the order of formation is reversed. It is valid. Further, in the above embodiment, the lower transparent glass substrate 5U
Although the case where B1 is made of 7059 glass has been described, a lower transparent glass substrate made of blue plate glass, other non-alkali glass, or the like may also be used. Furthermore, in the above embodiment, the storage capacitor element Ca is
Although the electrode PLI of the storage capacitor element Cadd is formed using an ITO film, the electrode PLI of the storage capacitor element Cadd may also be formed using an ITO film.
A film having a thickness of 700 to 1200 [human SiO] may be provided on both sides of the lower transparent glass substrate 5UBI by dip treatment. Furthermore, the second conductive film d2 and the third conductive film d3 may be formed by one photoetching. Effect of the Invention 1 As explained above, in the liquid crystal display device according to the present invention, since the opaque conductive film is provided between the end of the silicon nitride film and the signal line covered with the ITO film, Since the ITO film covering the signal line is not reduced at the edge of the silicon film, the adhesion between the signal line and the silicon nitride film is good at the edge of the silicon nitride film. Since moisture does not penetrate between the silicon film and the silicon film, even if a potential difference occurs between adjacent signal lines,
The conductive film constituting the signal line will not be ionized, and the signal line will not be corroded. Furthermore, in the method for manufacturing a liquid crystal display device according to the present invention, the pixel electrode is formed on the insulating film, and then the source electrode and the drain electrode are formed using the opaque conductive film. Therefore, the pixel electrode is formed on the clean insulating film. can do. For this reason, the adhesion between the insulating film and the pixel electrode is good, so when forming the pixel electrode, the film constituting the pixel electrode will not peel off together with the resist, so the pixel electrode will not be damaged and the pixel electrode will not be damaged. It can't be a defect. Furthermore, since almost no side etching occurs when forming the pixel electrode, the area of the pixel electrode does not become smaller. As described above, the effects of this invention are remarkable.

[Brief explanation of drawings]

1A is a schematic plan view showing the gate terminal portion of the liquid crystal display device shown in FIG. 2A etc., and FIG. 1B is the IB-
A sectional view taken along the IB cutting line, Figure 1C is I of Figure 1A.
2A is a cross-sectional view taken along the C-I C cutting line, FIG. 2A is a plan view of a main part showing one pixel of the liquid crystal display section of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is FIG. 2A. Figure 2C is a cross-sectional view of the part cut along the nB-IIB cutting line and the area around the seal part, and Figure 2C is the nc-
3 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged, and FIGS. 4 to 6 are cross-sectional views taken along the nC cutting line. The drawn plan view, FIG. 7 is a plan view of the main part in a state where only the pixel electrode layer and color filter layer shown in FIG. 3 are superimposed, and FIG. 8 is a plan view of an active matrix color liquid crystal display device. An equivalent circuit diagram showing the liquid crystal display section, Fig. 9 is the second
Fig. 10 is an equivalent circuit diagram of the pixel shown in Fig. A, and Fig. 10 is a time chart showing the drive voltage of the scanning signal line by the DC cancellation method. SUB...Transparent glass substrate GL...Scanning signal line DL...Video signal line GI...Insulating film GT...Gate electrode AS...I-type semiconductor layer SD...Source electrode or drain electrode psv...
Protective film BM...Light shielding film LC...Liquid crystal TPT...Thin film transistor ITO...Transparent pixel electrode god...Conductive film Cadd...Holding capacitor element Cgs...Superposition capacitor Cpix...Liquid crystal Capacity GTM...Gate terminal GTM---Katejikanchidl---1'r1! I ps1-・Keep it Pus GL-11 Yoi Kichigo spear 1 (d2- 2nd! tR refreshing 9th figure VLc t2 t3 t4

Claims (1)

[Claims] 1. In an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel, at least a portion of a terminal and a signal line connected to the terminal are covered with an ITO film. A liquid crystal display device characterized in that an opaque conductive film is provided between an end of the silicon nitride film and the signal line covered with the ITO film. 2. In a method for manufacturing an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel, an insulating film used as a gate insulating film is provided, and the pixel electrode is formed on the insulating film. 1. A method for manufacturing a liquid crystal display device, which comprises forming a source electrode and a drain electrode using an opaque conductive film after forming the opaque conductive film.