JPH02235350A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02235350A JPH02235350A JP1056635A JP5663589A JPH02235350A JP H02235350 A JPH02235350 A JP H02235350A JP 1056635 A JP1056635 A JP 1056635A JP 5663589 A JP5663589 A JP 5663589A JP H02235350 A JPH02235350 A JP H02235350A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- aluminum
- gold wire
- aluminum pad
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 47
- 229910052782 aluminium Inorganic materials 0.000 abstract description 47
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 23
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- 230000007774 longterm Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にワイヤボンディングバ
ッドの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a wire bonding pad.
従来の半導体装置におけるワイヤボンディング部は第２
図に示すように構成されている．第２図はワイヤボンデ
ィング部を拡大して示す断面図で、同図においてｌは半
導体集積回路素子、２は電気信号の授受を行なうための
アルミパッドで、このアルミバッド２は前記半導体集積
回路素子ｌ上に形成されている。３は外部装置（図示せ
ず）と前記半導体集積回路素子ｌとを接続するための金
線で、この金線３は前記アルミパソド２上にボンディン
グされており、ボンディングされることによって先端に
円板部分３ａが形成されている。The wire bonding part in conventional semiconductor devices is
It is configured as shown in the figure. FIG. 2 is an enlarged cross-sectional view of the wire bonding part. In the figure, l is a semiconductor integrated circuit element, 2 is an aluminum pad for transmitting and receiving electrical signals, and this aluminum pad 2 is a semiconductor integrated circuit element. It is formed on l. Reference numeral 3 denotes a gold wire for connecting an external device (not shown) and the semiconductor integrated circuit element 1. This gold wire 3 is bonded onto the aluminum pad 2, and by bonding, a circular plate is formed at the tip. A portion 3a is formed.
なお、４は半尋体集積回路素子ｌの表面を保護するため
の表面コーティングで、この表面コーティング４は窒化
膜によって形成されている。Note that 4 is a surface coating for protecting the surface of the semicircular integrated circuit element l, and this surface coating 4 is formed of a nitride film.
このように構成された半導体装置を組立てるには、先ず
、この半導体集積回路素子ｌにアルミパソド２．表面コ
ーティング４等を形成した後、アルミバソド２とリード
フレーム（図示せず）等を金線３によって接続する。し
かる後、半導体集積回路素子ｌを樹脂封止することによ
って半導体装置が組立てられることになる．
〔発明が解決しようとする課題〕
しかるに、このように構成された従来の半導体装置にお
いては、゛アルミパソド２の上面における金線３と表面
コーティング４との間に解放された部分が生じ、封止樹
脂内に水分が侵入された場合にはこの部分が腐食され易
く、このアルミの腐食が進行すると金線３とアルミパッ
ド２との導通が断たれるという問題があった。従来の半
導体装置に湿中バイアス試験等を実施すると入出力信号
が断たれる場合があった。To assemble the semiconductor device configured in this way, first, aluminum pads 2. After forming the surface coating 4, etc., the aluminum bathode 2 and a lead frame (not shown), etc. are connected with a gold wire 3. Thereafter, the semiconductor device is assembled by sealing the semiconductor integrated circuit element l with resin. [Problems to be Solved by the Invention] However, in the conventional semiconductor device configured in this way, an open portion is created between the gold wire 3 and the surface coating 4 on the upper surface of the aluminum pad 2, and the sealing When moisture enters the resin, this portion is likely to be corroded, and as the corrosion of the aluminum progresses, there is a problem in that the conduction between the gold wire 3 and the aluminum pad 2 is broken. When a humidity bias test or the like is performed on a conventional semiconductor device, input/output signals may be cut off.
本発明に係る半導体装置は、半導体素子のワイヤボンデ
ィング用パッドを、ポンディングワイヤに全面にわたり
接合される内側パッド部と、この内側バンド部の外周を
囲む外側パッド部とに二分して形成し、これらの内、外
側パッド間に窒化膜からなる隔絶体を設けたものである
。In the semiconductor device according to the present invention, a wire bonding pad of a semiconductor element is divided into two parts: an inner pad part that is bonded over the entire surface to the bonding wire, and an outer pad part that surrounds the outer periphery of the inner band part, Among these, a separator made of a nitride film is provided between the outer pads.
内側パンド部が腐食されるのを隔絶体によって阻止する
ことができ、内側パッド部とボンディングワイヤとの導
通状態を長期にわたって維持することができる。Corrosion of the inner pad portion can be prevented by the insulator, and electrical continuity between the inner pad portion and the bonding wire can be maintained over a long period of time.
以下、本発明の一実施例を第１図（ａ）および第１図（
ｂ）によって詳細に説明する．
第１図（ａ）は本発明に係る半導体装置のワイヤボンデ
ィング部を拡大して示す断面図、第１図（ｂ）は同じく
アルミパッドを示す平面図である。これらの図において
前記第２図で説明したものと同一もしくは同等部材につ
いては同一符号を付し、ここにおいて詳細な説明は省略
する。これらの図において、ｌ１は内側アルミパッドで
、この内側アルミパフドｌ１は平面視円形に形成され、
その直径は、金線３をボンディングした際に形成される
円板部分３ａの直径より小さくなるように設定されてい
る．ｌ２は外側アルミパッドで、この外側アルミパソド
１２は中央部に前記内側アルミパッド１１の直径より大
きな径をもって開口された円形開口部が形成され、この
円形開口部内に前記内側アルミバッド１ｌが配設される
ように内側アルミパッド１１の外周側に形成されている
。すなわち、前記内側アルミバソド１１と外側アルミパ
ッドｌ２との間には僅かな間隙ｌ３が形成されることに
なる。ｌ４は前記内側アルミパッド１ｌが腐食されるの
を阻止するための隔絶体で、この隔絶体ｌ４は窒化膜か
らなり、半導体集積回路素子ｌ上であって前記内側アル
ミバッド１ｌと外側アルミバンド１２との間の間隙内に
形成されている。また、この隔絶体１４はその厚み寸法
が内側，外側アルミバッドＩｔ，１２の厚み寸法より僅
かに小さく設定され、かつ内側．外側アルミパッド１１
．１２との間に僅かな間隙が形成されるように幅寸法
が設定されている。なお、１５は拡散リードである。An embodiment of the present invention will be described below with reference to FIGS. 1(a) and 1(a).
b) will be explained in detail. FIG. 1(a) is an enlarged sectional view showing a wire bonding portion of a semiconductor device according to the present invention, and FIG. 1(b) is a plan view showing an aluminum pad. In these figures, the same or equivalent members as those explained in FIG. In these figures, l1 is an inner aluminum pad, and this inner aluminum pad l1 is circular in plan view.
Its diameter is set to be smaller than the diameter of the disc portion 3a formed when the gold wire 3 is bonded. Reference numeral 12 denotes an outer aluminum pad, and the outer aluminum pad 12 has a circular opening in the center thereof having a diameter larger than the diameter of the inner aluminum pad 11, and the inner aluminum pad 1l is disposed within this circular opening. It is formed on the outer circumferential side of the inner aluminum pad 11 so as to be similar to the inner aluminum pad 11. That is, a slight gap l3 is formed between the inner aluminum base 11 and the outer aluminum pad l2. Reference numeral 14 denotes an insulator for preventing the inner aluminum pad 1l from being corroded. This insulator l4 is made of a nitride film and is located on the semiconductor integrated circuit element l and is connected to the inner aluminum pad 1l and the outer aluminum band 12. It is formed in the gap between the Further, the thickness of this insulator 14 is set to be slightly smaller than that of the inner and outer aluminum pads It, 12, and the thickness of the inner and outer aluminum pads It, 12 is set to be slightly smaller than that of the inner and outer aluminum pads It. Outer aluminum pad 11
．． The width dimension is set so that a slight gap is formed between the two and 12. Note that 15 is a diffusion lead.
このように構成されたアルミパッドに金線３をボンディ
ングするには、先ず、金線３の円板部分３ａによって内
側アルミパッドｌｌの上面が全面にわたり覆われるよう
に金線３と内側アルミパッド１１との位置決めが行われ
る。金線３をアルミパッド上にボンディングすると、第
１図（ｂ）に示すように内側アルミバッド１ｌの上面は
金線３と接合され、金線３の円板部分３ａにおける外周
部は外側アルミバフドｌ２に接合されることになる。こ
の際、同図に示すように隔絶体ｌ４の上端部は、金線３
に対して接触されることなく僅かの間隙をおいて離間さ
れている。In order to bond the gold wire 3 to the aluminum pad configured in this way, first, the gold wire 3 and the inner aluminum pad 11 are bonded so that the upper surface of the inner aluminum pad ll is entirely covered by the disk portion 3a of the gold wire 3. Positioning is performed. When the gold wire 3 is bonded onto the aluminum pad, the upper surface of the inner aluminum pad 1l is bonded to the gold wire 3 as shown in FIG. It will be joined to. At this time, as shown in the figure, the upper end of the separator l4 is connected to the gold wire 3.
They are separated from each other by a slight gap without being in contact with each other.
したがって、このようにして金Ｎｓ３がボンディングさ
れたアルミバンドにおいては、外側アルミバソド１２上
における金ｗＡ３と表面コーティング４との間から外側
アルミパ７ドｌ２が腐食されたとしても、内側アルミパ
ッド１１は隔絶体１４によって外側アルミバッド１２に
対して隔絶されているから、外側アルミパッ白２が腐食
されるだけに留まり、内側アルミパッドｌ１が腐食され
るようなことはない。このため、内側アルミパッド１１
と金線３との導通を長朋にわたって維持することができ
る。Therefore, in the aluminum band to which gold Ns3 is bonded in this way, even if the outer aluminum pad 7 is corroded from between the gold wA3 and the surface coating 4 on the outer aluminum bath 12, the inner aluminum pad 11 is isolated. Since it is isolated from the outer aluminum pad 12 by the body 14, only the outer aluminum pad 2 is corroded, and the inner aluminum pad l1 is not corroded. For this reason, the inner aluminum pad 11
It is possible to maintain conduction between the gold wire 3 and the gold wire 3 throughout the length.
〔発明の効果〕
以上説明したように本発明に係る半導体装置は、半導体
素子のワイヤボンディング用バンドを、ボンディングワ
イヤに全面にわたり接合される内側パッド部と、この内
側パッド部の外周を囲む外側パッド部とに二分して形成
し、これらの内、外側パッド間に窒化膜からなる隔絶体
を設けたため、内側パッド部が腐食されるのを隔絶体に
よって阻止することができ、内側バンド部とボンディン
グワイヤとの導通状態を長期にわたって維持することが
できる。したがって、信鎖性の高い高品質な半導体装置
を得ることができるという効果がある．[Effects of the Invention] As explained above, the semiconductor device according to the present invention includes a wire bonding band for a semiconductor element that includes an inner pad portion that is bonded over the entire surface to the bonding wire, and an outer pad that surrounds the outer periphery of the inner pad portion. Since the insulation material made of nitride film is provided between the inner and outer pad parts, the insulation material can prevent the inner pad part from being corroded, and the bonding between the inner band part and the bonding part can be prevented. The state of conduction with the wire can be maintained for a long period of time. Therefore, there is an effect that a high quality semiconductor device with high reliability can be obtained.
第１図（ａ）は本発明に係る半導体装置のワイヤボンデ
ィング部を拡大して示す断面図、第１図（ｂ）は同じく
アルミパッドを示す平面図、第２図は従来の半導体装置
におけるワイヤボンディング部を拡大して示す断面図で
ある。
１・・・・半導体集積回路素子、３・・・・金線、４・
・・・表面コーティング、Ｉ１・・・・内側アルミパッ
ド、１２・・・・外側アルミパソド、ｌ４・・・・隔絶
体。FIG. 1(a) is an enlarged cross-sectional view showing a wire bonding part of a semiconductor device according to the present invention, FIG. 1(b) is a plan view showing an aluminum pad, and FIG. 2 is a wire bonding portion of a conventional semiconductor device. FIG. 3 is an enlarged cross-sectional view showing a bonding part. 1... Semiconductor integrated circuit element, 3... Gold wire, 4...
...Surface coating, I1...Inner aluminum pad, 12...Outer aluminum pad, l4...Insulator.
Claims (1)
ィングワイヤに全面にわたり接合される内側パッド部と
、この内側パッド部の外周を囲む外側パッド部とに二分
して形成し、これらの内、外側パッド間に窒化膜からな
る隔絶体を設けたことを特徴とする半導体装置。A wire bonding pad for a semiconductor device is formed by dividing it into two parts: an inner pad part that is bonded over the entire surface to the bonding wire, and an outer pad part that surrounds the outer periphery of this inner pad part. A semiconductor device characterized by being provided with a separator made of a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1056635A JPH02235350A (en) | 1989-03-08 | 1989-03-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1056635A JPH02235350A (en) | 1989-03-08 | 1989-03-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02235350A true JPH02235350A (en) | 1990-09-18 |
Family
ID=13032782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1056635A Pending JPH02235350A (en) | 1989-03-08 | 1989-03-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02235350A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
| US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
| US6362528B2 (en) * | 1996-08-21 | 2002-03-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN107785343A (en) * | 2016-08-25 | 2018-03-09 | 英飞凌科技股份有限公司 | Semiconductor device and the method for forming semiconductor device |
-
1989
- 1989-03-08 JP JP1056635A patent/JPH02235350A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
| US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
| US6362528B2 (en) * | 1996-08-21 | 2002-03-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6500748B2 (en) | 1996-08-21 | 2002-12-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6720658B2 (en) | 1996-08-21 | 2004-04-13 | Kabushiki Kaisha Toshiba | Semiconductor device having a plurality of conductive layers |
| CN107785343A (en) * | 2016-08-25 | 2018-03-09 | 英飞凌科技股份有限公司 | Semiconductor device and the method for forming semiconductor device |
| US10867893B2 (en) | 2016-08-25 | 2020-12-15 | Infineon Technologies Ag | Semiconductor devices and methods for forming a semiconductor device |
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