JPH11150144A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH11150144A JPH11150144A JP9313652A JP31365297A JPH11150144A JP H11150144 A JPH11150144 A JP H11150144A JP 9313652 A JP9313652 A JP 9313652A JP 31365297 A JP31365297 A JP 31365297A JP H11150144 A JPH11150144 A JP H11150144A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor device
- bonding pad
- insulator
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000012212 insulator Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 21
- 239000007769 metal material Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000001125 extrusion Methods 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、半導体装置の高機能化に伴い、半
導体チップの多ピン化、半導体チップの高速化等が要求
されている。また、例えば、携帯電話等の携帯機器の小
型化や高密度実装のために、半導体チップの小型化、狭
ピッチ化も要求されている。狭ピッチ化された半導体チ
ップのボンディングパッドと半導体チップの電極を外部
に引き出すためのリードが形成されたリードフレームと
の電気的接続は、ワイヤーボンド方式やＴＡＢ（テープ
ボンディング）方式などによって行なっている。2. Description of the Related Art In recent years, as semiconductor devices have become more sophisticated, it has been required to increase the number of pins in the semiconductor chip, increase the speed of the semiconductor chip, and the like. Further, for example, for miniaturization and high-density mounting of mobile devices such as mobile phones, miniaturization and narrow pitch of semiconductor chips are also required. The electrical connection between the bonding pads of the semiconductor chip having a reduced pitch and the lead frame on which leads for leading the electrodes of the semiconductor chip to the outside are formed is performed by a wire bonding method, a TAB (tape bonding) method, or the like. .
【０００３】[0003]
【発明が解決しようとする課題】狭ピッチ化された半導
体デバイスを、例えばワイヤーボンド方式やＴＡＢ方式
にて電気的接続を行った場合、電気的に接続をする役割
を果たす材料がボンディング後にショートして、半導体
装置としての役割が果たせなくなるといった問題があ
る。When a semiconductor device having a reduced pitch is electrically connected by, for example, a wire bonding method or a TAB method, a material that plays a role of electrical connection short-circuits after bonding. Therefore, there is a problem that the role as a semiconductor device cannot be fulfilled.
【０００４】例えば、図７に示すように、通常、半導体
装置の製造工程においては、半導体チップ５１上に半導
体チップ５１とリードフレームとを電気的に接続するた
めのボンディングパッド５２を形成する。その後に、半
導体チップ５１上に絶縁膜からなる保護膜５３を形成す
る。このとき、保護膜５３の厚さＨはボンディングパッ
ド５２の厚さｈと略同様とする。次いで、ボンディング
パッド５２上の保護膜５３を除去する。これにより、図
７（ｂ）に示すように、開口部５４が形成される。そし
て、図７に示す状態から、各ボンディングパッド５２と
図示しないリードフレームとを電気的に接続する。たと
えば、ワイヤボンディング方式による場合には、図８に
示すように、例えば金線等のワイヤの端部に形成したボ
ールをキャピラリで各ボンディングパッド５２に順次圧
着する。このとき、各ボンディングパッド５２間のピッ
チが狭くなると、押し潰されたボール部５５ａは、図８
に示すように、開口部５４からはみ出し、保護膜５３上
に乗り上げ、隣り合うボール部５５ａが互いに接触する
ことがある。For example, as shown in FIG. 7, in a manufacturing process of a semiconductor device, a bonding pad 52 for electrically connecting the semiconductor chip 51 to a lead frame is usually formed on the semiconductor chip 51. After that, a protective film 53 made of an insulating film is formed on the semiconductor chip 51. At this time, the thickness H of the protective film 53 is substantially the same as the thickness h of the bonding pad 52. Next, the protective film 53 on the bonding pad 52 is removed. As a result, as shown in FIG. 7B, an opening 54 is formed. Then, from the state shown in FIG. 7, each of the bonding pads 52 is electrically connected to a lead frame (not shown). For example, in the case of the wire bonding method, as shown in FIG. 8, a ball formed at the end of a wire, such as a gold wire, is sequentially pressure-bonded to each bonding pad 52 by a capillary. At this time, when the pitch between the bonding pads 52 becomes narrow, the crushed ball portion 55a is
As shown in FIG. 7, the ball portions 55a may protrude from the opening portion 54, ride on the protective film 53, and come into contact with each other.
【０００５】ＴＡＢ方式による場合には、図７、図９に
示すように、開口部５４内に金属材料からなるバンプ２
５を形成し、これにリード３１を押し付けることによっ
て、リード３１とボンディングパッド４とを電気的に接
続する。しかしながら、ＴＡＢ方式による場合にも、図
９に示すように、押し潰された各バンプ５７は開口部か
らはみ出し、保護膜５３上に乗り上げ、隣り合うバンプ
５７は互いに接触することがあり、半導体装置の不良の
原因となる。[0005] In the case of the TAB method, as shown in FIGS.
5 is formed, and the lead 31 is pressed against this, thereby electrically connecting the lead 31 and the bonding pad 4. However, even in the case of the TAB method, as shown in FIG. 9, each of the crushed bumps 57 protrudes from the opening, runs on the protective film 53, and the adjacent bumps 57 may come into contact with each other. Cause failure.
【０００６】本発明は、ボンディングパッドの間隔が狭
ピッチ化された半導体チップを用いても、各ボンディン
グパッド間の短絡を防止することが可能で、信頼性の高
い半導体装置およびその製造方法を提供することを目的
とする。The present invention provides a highly reliable semiconductor device capable of preventing a short circuit between bonding pads even when a semiconductor chip having a narrow pitch between bonding pads is used, and a method for manufacturing the same. The purpose is to do.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置は、
半導体チップの各ボンディングパッド間を絶縁し、当該
各ボンディングパッドの高さより高く当該半導体チップ
上に形成された絶縁体を有する。According to the present invention, there is provided a semiconductor device comprising:
Insulating between bonding pads of the semiconductor chip and having an insulator formed on the semiconductor chip higher than the height of each bonding pad.
【０００８】本発明の半導体装置では、半導体チップの
ボンディングパッドの周囲に形成された絶縁体の高さが
高いため、絶縁体が一種のダム（堰）的な役割を果た
し、ワイヤボンディングやテープボンディングを行った
後でも、ボンディングパッド間の短絡が防止され、信頼
性の高い半導体装置となる。In the semiconductor device of the present invention, since the height of the insulator formed around the bonding pad of the semiconductor chip is high, the insulator acts as a kind of dam, and is used for wire bonding or tape bonding. Even after performing the above, a short circuit between the bonding pads is prevented, and a highly reliable semiconductor device is obtained.
【０００９】前記絶縁体は、前記各ボンディングパッド
の周囲を囲んでいる。The insulator surrounds the periphery of each of the bonding pads.
【００１０】前記絶縁体によって形成された前記各ボン
ディングパッド上の凹部内に、前記ボンディングパッド
と前記半導体チップの電極を外部に引き出すためのリー
ドとを接続する接続部材が収容されている。[0010] A connection member for connecting the bonding pad and a lead for extracting an electrode of the semiconductor chip to the outside is accommodated in a concave portion on each of the bonding pads formed by the insulator.
【００１１】また、本発明の製造方法は、半導体チップ
の各ボンディングパッド間を絶縁する絶縁体を各ボンデ
ィングパッドの高さよりも高く前記半導体チップ上に形
成する絶縁体形成工程と、前記各ボンディングパッドと
リードとを接続部材で電気的に接続するボンディング工
程とを有する。The manufacturing method of the present invention also includes an insulator forming step of forming an insulator for insulating between bonding pads of the semiconductor chip on the semiconductor chip higher than the height of each bonding pad; And a bonding step of electrically connecting the lead and the lead with a connecting member.
【００１２】前記絶縁体形成工程において、前記絶縁体
のボンディングパッドとリードとの接続後の前記接続部
材の高さ程度に形成する。In the step of forming the insulator, the insulator is formed at a height of about the height of the connection member after the connection between the bonding pad of the insulator and the lead.
【００１３】前記絶縁体形成工程は、ボンディングパッ
ドが形成された半導体チップ上に当該ボンディングパッ
ドを覆い、かつ膜厚が前記ボンディングパッドの厚さよ
りも十分に厚くなるように絶縁膜を形成する絶縁膜形成
工程と、前記ボンディングパッド上の前記絶縁膜を除去
して開口する開口工程とを有する。In the step of forming an insulator, the insulating film covers the bonding pad on the semiconductor chip on which the bonding pad is formed, and forms an insulating film such that the film thickness is sufficiently larger than the thickness of the bonding pad. A forming step and an opening step of removing and opening the insulating film on the bonding pad.
【００１４】[0014]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。第１実施形態 図１は、本発明に係る半導体装置の第１の実施形態を示
す断面図である。なお、図１に示す半導体装置は、ワイ
ヤボンディング工程が完了したものであって、この後に
パッケージング工程などを経て最終的に完成する。図１
において、半導体チップ２上には、所定の間隔（ピッ
チ）で厚さｈの矩形状のボンディングパッド４が形成さ
れている。さらに、半導体チップ２上には、例えば、Ｓ
ｉＮからなる絶縁膜６が厚さＨで形成されている。絶縁
膜６は、ボンディングパッド４上では開口されており、
ボンディングパッド４は外部と接している。したがっ
て、各ボンディングパッド４は、絶縁膜６によって形成
される高さ（Ｈ−ｈ）の壁で周囲を囲まれた状態となっ
ている。Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. Note that the semiconductor device shown in FIG. 1 is one in which the wire bonding step has been completed, and is finally completed through a packaging step and the like. FIG.
2, rectangular bonding pads 4 having a thickness h are formed on the semiconductor chip 2 at predetermined intervals (pitch). Further, on the semiconductor chip 2, for example, S
An insulating film 6 made of iN is formed with a thickness H. The insulating film 6 is opened on the bonding pad 4,
The bonding pad 4 is in contact with the outside. Therefore, each bonding pad 4 is surrounded by a wall having a height (Hh) formed by the insulating film 6.
【００１５】また、各ボンディングパッド４には、例え
ば、金線からなるボンディングワイヤ８のボール状に形
成された端部が押し潰されて圧着された接続部８ａが接
合されている。絶縁膜６によって形成される壁の高さ
（Ｈ−ｈ）は、押し潰されて圧着されているボンディン
グワイヤ８の接続部８ａの高さと同じ程度となってい
る。これらの接続部８ａは、上述した絶縁膜６によって
形成される壁で形成される凹部内にほぼ収容された状態
となっており、絶縁膜６上に乗り上げる状態となってい
ない。したがって、隣合う各接続部８ａは、互いに確実
に離間された状態となっている。Further, to each of the bonding pads 4, a connection portion 8a is formed in which a ball-shaped end of a bonding wire 8 made of, for example, a gold wire is crushed and pressed. The height (Hh) of the wall formed by the insulating film 6 is substantially the same as the height of the connection portion 8a of the bonding wire 8 that is crushed and pressed. These connecting portions 8a are substantially housed in the recesses formed by the walls formed by the insulating film 6 described above, and do not run over the insulating film 6. Therefore, the adjacent connecting portions 8a are in a state of being surely separated from each other.
【００１６】上記の半導体チップ２は、たとえば、シリ
コン基板などの半導体基板に集積回路が作りつけられて
いる。ボンディングパッド４は、半導体チップ２の各信
号線を外部に引き出すためのリードが形成されたリード
フレームとボンディングワイヤ８によって接続される金
属被膜による電極であり、例えば、アルミニウムから形
成されている。絶縁膜６は、半導体チップ２を保護する
とともに、各ボンディングパッド４間が電気的に短絡す
るのを防ぐ役割を果たしている。In the semiconductor chip 2, an integrated circuit is formed on a semiconductor substrate such as a silicon substrate. The bonding pad 4 is an electrode made of a metal film and connected by a bonding wire 8 to a lead frame on which leads for leading each signal line of the semiconductor chip 2 to the outside are formed, and is formed of, for example, aluminum. The insulating film 6 plays a role of protecting the semiconductor chip 2 and preventing an electrical short circuit between the bonding pads 4.
【００１７】次に、上記構成の本実施形態に係る半導体
装置の製造方法について説明する。まず、半導体チップ
２は、たとえば、シリコンウェハ内に各種製造工程を経
て複数形成され、各半導体チップ２上には所定のピッチ
でボンディングパッド４が形成される。なお、これらの
製造工程は一般的なものであり詳細な説明を省略する。Next, a method of manufacturing the semiconductor device according to the present embodiment having the above configuration will be described. First, a plurality of semiconductor chips 2 are formed in a silicon wafer through various manufacturing processes, for example, and bonding pads 4 are formed on each semiconductor chip 2 at a predetermined pitch. Note that these manufacturing steps are general, and a detailed description thereof will be omitted.
【００１８】次いで、図２に示すように、半導体チップ
２上に、各ボンディングパッド４を覆うように、厚さＨ
の絶縁膜６を形成する。絶縁膜６は、例えば、ＣＶＤ
（Chemical Vapor deposition)法によってＳｉＮ膜を形
成することで得られる。このとき、絶縁膜６の厚さＨ
は、絶縁膜６によって形成される壁の高さ（Ｈ−ｈ）が
上述したボンディングワイヤ８の圧潰後の接続部８ａを
略収容する程度になるように形成する。Next, as shown in FIG. 2, a thickness H is formed on the semiconductor chip 2 so as to cover each bonding pad 4.
Is formed. The insulating film 6 is formed, for example, by CVD.
It is obtained by forming a SiN film by a (Chemical Vapor deposition) method. At this time, the thickness H of the insulating film 6
Is formed such that the height (Hh) of the wall formed by the insulating film 6 is substantially equal to the connection portion 8a of the bonding wire 8 after the crushing.
【００１９】次いで、図２に示す状態から、所定のパタ
ーンのマスクを形成し、例えば、ＲＩＥ（リアクティブ
・イオン・エッチング）法によって、図３に示すよう
に、各ボンディングパッド４上の絶縁膜６を除去してボ
ンディングパッド４の上方を開口する。これによって、
図３に示すように、ボンディングパッド４上には絶縁膜
６の壁状部６ａによって凹部１０が形成されることにな
る。Next, a mask having a predetermined pattern is formed from the state shown in FIG. 2, and the insulating film on each bonding pad 4 is formed by, for example, RIE (reactive ion etching) as shown in FIG. 6 is removed to open an upper portion of the bonding pad 4. by this,
As shown in FIG. 3, a recess 10 is formed on the bonding pad 4 by the wall-shaped portion 6 a of the insulating film 6.
【００２０】次いで、図３に示す状態の半導体チップ２
が複数形成された状態のウェハを、ダイシング工程にお
いてダイシングし、個々の半導体チップ２に分離する。
そして、ダイボンディング工程において、個々に分離さ
れた半導体チップ２を所定のパターンに形成されたリー
ドフレームのダイパッドに接合する。なお、これらのダ
イシング工程およびダイボンディング工程は、一般的な
工程であり、詳細については省略する。Next, the semiconductor chip 2 in the state shown in FIG.
Is diced in the dicing step to separate the wafer into individual semiconductor chips 2.
Then, in the die bonding step, the individually separated semiconductor chips 2 are bonded to die pads of a lead frame formed in a predetermined pattern. Note that these dicing step and die bonding step are general steps, and a detailed description thereof will be omitted.
【００２１】次いで、リードフレームに接合された半導
体チップ２の各ボンディングパッド４と対応するリード
フレームのインナーリードとをワイヤボンディング法に
よって電気的に接続する。具体的には、図４に示すよう
に、例えば、図示しない電気トーチによりボンディング
ワイヤ８の先端を溶融してボール８ａを形成する。この
ボール８ａをキャピラリ２１でボンディングパッド４に
押し付けて接合する。次いで、ボンディングワイヤ８を
繰り出しながら、キャピラリ２１を対応するリードフレ
ームのインナーリード上に移動し、再度キャピラリ２１
をインナーリードに押し付けてボンディングワイヤ８を
接合し、クランパでボンディングワイヤ８をクランプし
てボンディングワイヤ８を切断する。このような動作を
繰り返しおこなって、各ボンディングパッド４と対応す
るリードフレームのインナーリードとを順次ボンディン
グワイヤ８で接続する。これにより、図１に示したよう
な状態となる。Next, each bonding pad 4 of the semiconductor chip 2 joined to the lead frame is electrically connected to the corresponding inner lead of the lead frame by a wire bonding method. Specifically, as shown in FIG. 4, for example, the tip of the bonding wire 8 is melted by an electric torch (not shown) to form the ball 8a. The ball 8a is pressed against the bonding pad 4 by the capillary 21 and joined. Next, the capillary 21 is moved onto the inner lead of the corresponding lead frame while the bonding wire 8 is being extended, and the capillary 21 is again moved.
Is pressed against the inner lead to bond the bonding wire 8, and the bonding wire 8 is clamped by a clamper to cut the bonding wire 8. By repeating such an operation, each bonding pad 4 and the corresponding inner lead of the lead frame are sequentially connected by the bonding wire 8. As a result, the state as shown in FIG. 1 is obtained.
【００２２】図４に示したように、ボール８ａをキャピ
ラリ２１でボンディングパッド４に押し付けたとき、押
し潰されたボール８ａはボンディングパッド４の周囲を
囲む絶縁膜６で形成された凹部１０内に収まり、絶縁膜
６（壁状部６ａ）上に乗り上げて、はみ出すことがな
い。このため、隣合う各ボンディングパッド４の間で、
押し潰されたボール８ａが互いに接触して短絡すること
が確実に防止される。したがって、ボンディングパッド
４間の間隔（ピッチ）が狭小化されても、押し潰された
ボール８ａが互いに接触することが防止される。As shown in FIG. 4, when the ball 8a is pressed against the bonding pad 4 by the capillary 21, the crushed ball 8a is placed in the recess 10 formed by the insulating film 6 surrounding the periphery of the bonding pad 4. It fits and rides on the insulating film 6 (wall-like portion 6a) and does not protrude. Therefore, between adjacent bonding pads 4,
The crushed balls 8a are reliably prevented from contacting each other and causing a short circuit. Therefore, even if the interval (pitch) between the bonding pads 4 is narrowed, the crushed balls 8a are prevented from coming into contact with each other.
【００２３】ワイヤボンディング工程が完了すると、封
止工程や検査工程等を経て半導体装置が完成する。When the wire bonding step is completed, the semiconductor device is completed through a sealing step, an inspection step, and the like.
【００２４】以上のように本実施形態によれば、半導体
チップ２上においてボンディングパッド４の周囲を囲む
絶縁膜６で形成された壁が形成され、各ボンディングパ
ッド４に押し潰された状態で接合されたボンディングワ
イヤ８のボール８ａが絶縁膜６で形成された壁に囲まれ
た状態にある。このため、隣合うボンディングパッド４
の押し潰された状態のボール８ａが互いに接触すること
が確実に防止され、信頼性の高い半導体装置となる。As described above, according to the present embodiment, the wall formed of the insulating film 6 surrounding the periphery of the bonding pad 4 is formed on the semiconductor chip 2, and is bonded to each bonding pad 4 in a crushed state. The ball 8a of the bonding wire 8 is surrounded by a wall formed of the insulating film 6. For this reason, adjacent bonding pads 4
The crushed balls 8a are reliably prevented from coming into contact with each other, resulting in a highly reliable semiconductor device.
【００２５】また、本実施形態によれば、その製造工程
において、ボンディングパッド４の周囲に一種のダムと
なる凹部１０を形成し、この凹部１０がボンディングワ
イヤ８のボール８ａが押しつぶされた際に凹部１０の壁
がボール８ａを構成する金属の流れを堰止め、周囲には
み出すのを防ぐ。このため、ボンディングパッド４間の
間隔が狭小化されても、ボンディングパッド４間の短絡
を確実に防止でき、信頼性の高い半導体装置を製造する
ことが可能となる。According to the present embodiment, in the manufacturing process, a concave portion 10 serving as a kind of dam is formed around the bonding pad 4, and the concave portion 10 is formed when the ball 8 a of the bonding wire 8 is crushed. The wall of the concave portion 10 blocks the flow of the metal constituting the ball 8a and prevents the metal from flowing out to the periphery. For this reason, even if the interval between the bonding pads 4 is narrowed, a short circuit between the bonding pads 4 can be reliably prevented, and a highly reliable semiconductor device can be manufactured.
【００２６】第２実施形態 図５は、本発明に係る半導体装置の第１の実施形態を示
す断面図である。なお、図５に示す半導体装置は、テー
プボンディング工程が完了したものであって、この後に
パッケージング工程などを経て最終的に完成する。ま
た、図５に示す半導体装置は、半導体チップ２の各信号
線を外部に引き出すためのリードフレームと半導体チッ
プ２の各ボンディングパッド４との接続がテープボンデ
ィング（ＴＡＢ）法によってなされたものである。 Second Embodiment FIG. 5 is a sectional view showing a first embodiment of a semiconductor device according to the present invention. Note that the semiconductor device shown in FIG. 5 is one in which the tape bonding step has been completed, and is finally completed through a packaging step and the like. In the semiconductor device shown in FIG. 5, the connection between the lead frame for leading each signal line of the semiconductor chip 2 to the outside and each bonding pad 4 of the semiconductor chip 2 is made by a tape bonding (TAB) method. .
【００２７】図５において、第１実施形態の場合と同様
に、半導体チップ２上には、所定のピッチでボンディン
グパッド４が形成されているとともに、絶縁膜６がボン
ディングパッド４上では開口されるように形成されてい
る。したがって、各ボンディングパッド４は、絶縁膜６
によって形成された壁で周囲を囲まれた状態となってい
る。各ボンディングパッド４には、例えば、Ａｕなどの
金属材料からなるバンプ２５を介して半導体チップ２の
電極を外部に引き出すためのリード３１が接合されてい
る。In FIG. 5, as in the first embodiment, bonding pads 4 are formed at a predetermined pitch on the semiconductor chip 2 and an insulating film 6 is opened on the bonding pads 4. It is formed as follows. Therefore, each bonding pad 4 is
Is surrounded by the wall formed by the above. For example, a lead 31 for extracting an electrode of the semiconductor chip 2 to the outside is bonded to each bonding pad 4 via a bump 25 made of a metal material such as Au.
【００２８】バンプ２５は、ボンディングパッド４とリ
ード３１との間で押し潰された状態にあり、これによっ
てボンディングパッド４とリード３１とが接合されてい
る。押し潰されたバンプ２５は、バンプ２５を構成する
金属が絶縁膜６によって形成された壁流れ出すことな
く、内側に収容された状態となっている。また、各リー
ド３１の中途には、凹部３１ｂが形成されており（図６
（ｂ）参照）、ボンディングパッド４の表面から突き出
た絶縁膜６を跨いだ状態となっている。The bump 25 is in a crushed state between the bonding pad 4 and the lead 31, and the bonding pad 4 and the lead 31 are joined. The crushed bump 25 is in a state in which the metal constituting the bump 25 is accommodated inside without flowing out to the wall formed by the insulating film 6. A recess 31b is formed in the middle of each lead 31 (FIG. 6).
(Refer to (b)), it is in a state of straddling the insulating film 6 protruding from the surface of the bonding pad 4.
【００２９】以下、上記構成の半導体装置の製造方法に
ついて説明する。半導体チップ２をシリコンウェハ内に
複数形成し、各半導体チップ２上に所定のピッチでボン
ディングパッド４を形成し、ボンディングパッド４を覆
うように絶縁膜６を形成し、各ボンディングパッド４上
の絶縁膜６を除去してボンディングパッド４の上方を開
口し、半導体チップ２が複数形成された状態のウェハか
ら個々の半導体チップ２に分離する工程までは第１実施
形態の場合と全く同様である。Hereinafter, a method of manufacturing the semiconductor device having the above configuration will be described. A plurality of semiconductor chips 2 are formed in a silicon wafer, bonding pads 4 are formed on each semiconductor chip 2 at a predetermined pitch, and an insulating film 6 is formed so as to cover the bonding pads 4. The steps up to the step of removing the film 6, opening the upper part of the bonding pad 4 and separating the semiconductor chips 2 from the wafer on which a plurality of semiconductor chips 2 are formed into individual semiconductor chips 2 are exactly the same as those in the first embodiment.
【００３０】次いで、図６に示すように、各ボンディン
グパッド４上にバンプ２５を設ける。バンプ２５を各ボ
ンディングパッド４上に設けるには、例えば、ガラス基
板上に所定のピッチで各バンプ２５を形成し、このガラ
ス基板と半導体チップ２とを重ね合わせることにより、
ボンディングパッド４上にバンプ２５を転写することが
できる。ボンディングパッド４上に転写されたバンプ２
５は、図６に示すように、ボンディングパッド４を囲む
絶縁膜６によって形成される凹部１０内に収容された状
態となる。Next, as shown in FIG. 6, a bump 25 is provided on each bonding pad 4. In order to provide the bumps 25 on the bonding pads 4, for example, the bumps 25 are formed at a predetermined pitch on a glass substrate, and the glass substrate and the semiconductor chip 2 are overlapped with each other.
The bump 25 can be transferred onto the bonding pad 4. Bump 2 transferred onto bonding pad 4
As shown in FIG. 6, 5 is housed in a concave portion 10 formed by the insulating film 6 surrounding the bonding pad 4.
【００３１】次いで、所定のパターンでリード３１が形
成されたＴＡＢテープを用意し、このＴＡＢテープを半
導体チップ２に対して位置決めし、図６に示すように、
各リード３１を対応するボンディングパッド４の上のバ
ンプ２５に押し付ける。図６（ｂ）に示すように、リー
ド３１の中途には凹部３１ｂが形成され、リード３１の
先端部３１ａは突き出た状態となっている。リード３１
の形状を上記のようにすることにより、凹部３１ｂがボ
ンディングパッド４よりも突き出た状態にある絶縁膜６
を跨ぐ状態となる。このため、ボンディングパッド４よ
りも突き出た状態にある絶縁膜６によって、ボンディン
グパッド４とリード３１とのバンプ２５を介した接合が
妨げられることがない。Next, a TAB tape on which leads 31 are formed in a predetermined pattern is prepared, and this TAB tape is positioned with respect to the semiconductor chip 2, and as shown in FIG.
Each lead 31 is pressed against the bump 25 on the corresponding bonding pad 4. As shown in FIG. 6B, a recess 31 b is formed in the middle of the lead 31, and the tip 31 a of the lead 31 is in a protruding state. Lead 31
Of the insulating film 6 in a state where the concave portion 31b protrudes from the bonding pad 4
Is straddled. Therefore, the bonding of the bonding pad 4 and the lead 31 via the bump 25 is not hindered by the insulating film 6 protruding from the bonding pad 4.
【００３２】リード３１の先端部３１ａがバンプ２５に
押し付けられることにより、バンプ２５を構成する金属
は、押し潰されて流動するが、ボンディングパッド４の
周囲には絶縁膜６によって形成された壁があるため、こ
の壁によって当該金属の流動が堰とめられ、凹部１０か
ら外部にはみ出すことがない。このため、ボンディング
パッド４間の短絡を防ぐことができる。When the tip 31 a of the lead 31 is pressed against the bump 25, the metal forming the bump 25 is crushed and flows, but a wall formed by the insulating film 6 is formed around the bonding pad 4. Therefore, the flow of the metal is stopped by the wall and does not protrude from the recess 10 to the outside. Therefore, a short circuit between the bonding pads 4 can be prevented.
【００３３】以上のように、本実施形態の場合も、上述
した第１実施形態の場合と同様な効果が得られる。な
お、本実施形態では、バンプ２５をボンディングパッド
４側に設ける構成としたが、これに限らず、リード３１
の先端部３１ａに形成することも可能である。As described above, also in the case of the present embodiment, the same effects as in the case of the above-described first embodiment can be obtained. In this embodiment, the bump 25 is provided on the bonding pad 4 side. However, the present invention is not limited to this.
It is also possible to form it at the tip portion 31a of the first member.
【００３４】[0034]
【発明の効果】本発明の半導体装置によれば、壁状の絶
縁体によってボンディングパッド間が確実に隔離されて
いるため、半導体チップのボンディングパッド間の短絡
が確実に防止され、信頼性の高い半導体装置となる。ま
た、本発明の半導体装置の製造方法によれば、予め絶縁
体によって半導体チップのボンディングパッドの周囲に
壁を形成することによって、ワイヤーボンディング方式
やＴＡＢ方式等による半導体チップのボンディングの際
に、ボンディングパッド部から接続部材がはみ出すこと
がなく、ボンディングパッド間の短絡を確実に防止する
ことができ、信頼正の高い半導体装置を製造可能とな
る。According to the semiconductor device of the present invention, since the bonding pads are reliably isolated by the wall-shaped insulator, a short circuit between the bonding pads of the semiconductor chip is reliably prevented, and high reliability is achieved. It becomes a semiconductor device. According to the method of manufacturing a semiconductor device of the present invention, a wall is formed in advance around a bonding pad of a semiconductor chip with an insulator, so that bonding is performed when bonding a semiconductor chip by a wire bonding method, a TAB method, or the like. The connection member does not protrude from the pad portion, a short circuit between the bonding pads can be reliably prevented, and a highly reliable semiconductor device can be manufactured.
【図１】本発明に係る半導体装置の第１の実施形態を示
す断面図である。FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention.
【図２】図１の半導体装置の製造工程を示す断面図であ
る。FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device of FIG. 1;
【図３】図２に続く製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing step following FIG. 2;
【図４】図３に続く製造工程を示す断面図である。FIG. 4 is a sectional view showing a manufacturing step following FIG. 3;
【図５】本発明に係る半導体装置の第２の実施形態を示
す断面図である。FIG. 5 is a sectional view showing a second embodiment of the semiconductor device according to the present invention.
【図６】図５の半導体装置の製造工程を示す断面図であ
る。FIG. 6 is a sectional view showing a manufacturing step of the semiconductor device of FIG. 5;
【図７】従来の半導体装置の製造工程の一例を示す断面
図である。FIG. 7 is a cross-sectional view illustrating an example of a manufacturing process of a conventional semiconductor device.
【図８】ワイヤボンディング方式によってボンディング
パッドにボンディングした状態の一例を示す断面図であ
る。FIG. 8 is a cross-sectional view showing an example of a state of bonding to a bonding pad by a wire bonding method.
【図９】テープボンディング方式によってボンディング
パッドにボンディングした状態の一例を示す断面図であ
る。FIG. 9 is a cross-sectional view showing an example of a state of bonding to a bonding pad by a tape bonding method.
２…半導体装置チップ、４…ボンディングパッド、６…
絶縁膜、８…ボンディングワイヤ、１０…凹部、２５…
バンプ、３１…リード。2 semiconductor chip, 4 bonding pad, 6
Insulating film, 8 ... bonding wire, 10 ... recess, 25 ...
Bump, 31 ... lead.
Claims (12)
絶縁し、当該各ボンディングパッドの高さより高く当該
半導体チップ上に形成された絶縁体を有する半導体装
置。1. A semiconductor device comprising: an insulating member formed on a semiconductor chip to insulate between bonding pads of the semiconductor chip and to be higher than the height of each bonding pad.
の周囲を囲んでいる請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein said insulator surrounds each of said bonding pads.
ディングパッド上の凹部内に、前記ボンディングパッド
と前記半導体チップの電極を外部に引き出すためのリー
ドとを接続する接続部材が収容されている請求項２に記
載の半導体装置。3. A connection member for connecting the bonding pad and a lead for leading out an electrode of the semiconductor chip to the outside is accommodated in a recess on each of the bonding pads formed by the insulator. Item 3. The semiconductor device according to item 2.
してボール状に形成し、これを前記ボンディングパッド
に圧着したものである請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein the connection member is formed by melting an end of a metal wire to form a ball and pressing the metal wire to the bonding pad.
であって、前記リードの端部と前記ボンディングパッド
の間で押しつぶされたものである請求項３に記載の半導
体装置。5. The semiconductor device according to claim 3, wherein said connection member is a bump made of a metal material, and is crushed between an end of said lead and said bonding pad.
触部が凸状に形成されている請求項５に記載の半導体装
置。6. The semiconductor device according to claim 5, wherein a contact portion of said lead end with said connecting member is formed in a convex shape.
項１に記載の半導体装置。7. The semiconductor device according to claim 1, wherein said insulator is made of silicon nitride.
絶縁する絶縁体を各ボンディングパッドの高さよりも高
く前記半導体チップ上に形成する絶縁体形成工程と、 前記各ボンディングパッドと前記半導体チップの電極を
外部に引き出すためのリードとを接続部材で電気的に接
続するボンディング工程とを有する半導体装置の製造方
法。8. An insulator forming step of forming an insulator on the semiconductor chip higher than the height of each bonding pad to insulate between the respective bonding pads of the semiconductor chip; and forming the insulator on each of the bonding pads and the electrodes of the semiconductor chip. A method for manufacturing a semiconductor device, comprising: a bonding step of electrically connecting a lead for leading out to the outside with a connection member.
のボンディングパッドと前記リードとの接続後の前記接
続部材の高さ程度に形成する請求項８に記載の半導体装
置の製造方法。9. The method of manufacturing a semiconductor device according to claim 8, wherein, in said insulator forming step, said insulator is formed to a height of said connection member after connection between said bonding pad of said insulator and said lead.
ィング法によって行なう請求項８に記載の半導体装置の
製造方法。10. The method according to claim 8, wherein said bonding step is performed by a wire bonding method.
ィング法によって行なう請求項８に記載の半導体装置の
製造方法。11. The method according to claim 8, wherein said bonding step is performed by a tape bonding method.
ッドが形成された半導体チップ上に当該ボンディングパ
ッドを覆い、かつ膜厚が前記ボンディングパッドの厚さ
よりも十分に厚くなるように絶縁膜を形成する絶縁膜形
成工程と、 前記ボンディングパッド上の前記絶縁膜を除去して開口
する開口工程とを有する請求項８に記載の半導体装置の
製造方法。12. The insulator forming step covers the bonding pad on the semiconductor chip on which the bonding pad is formed, and forms an insulating film such that the film thickness is sufficiently larger than the thickness of the bonding pad. The method of manufacturing a semiconductor device according to claim 8, further comprising: an insulating film forming step; and an opening step of removing and opening the insulating film on the bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9313652A JPH11150144A (en) | 1997-11-14 | 1997-11-14 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9313652A JPH11150144A (en) | 1997-11-14 | 1997-11-14 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11150144A true JPH11150144A (en) | 1999-06-02 |
Family
ID=18043894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9313652A Pending JPH11150144A (en) | 1997-11-14 | 1997-11-14 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11150144A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034472A (en) * | 2006-07-26 | 2008-02-14 | Sony Corp | Semiconductor device and method for manufacturing same |
| JP2017132139A (en) * | 2016-01-28 | 2017-08-03 | 株式会社沖データ | Optical head, image forming apparatus, and image reading apparatus |
| WO2022113813A1 (en) * | 2020-11-30 | 2022-06-02 | ソニーセミコンダクタソリューションズ株式会社 | Imaging element package, manufacturing method, and electronic apparatus |
-
1997
- 1997-11-14 JP JP9313652A patent/JPH11150144A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008034472A (en) * | 2006-07-26 | 2008-02-14 | Sony Corp | Semiconductor device and method for manufacturing same |
| JP2017132139A (en) * | 2016-01-28 | 2017-08-03 | 株式会社沖データ | Optical head, image forming apparatus, and image reading apparatus |
| WO2022113813A1 (en) * | 2020-11-30 | 2022-06-02 | ソニーセミコンダクタソリューションズ株式会社 | Imaging element package, manufacturing method, and electronic apparatus |
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