JP2004281980A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device which does not need to bury a through electrode for connecting stacked semiconductor chips in a deep hole, and a method of manufacturing the same.
A semiconductor device according to the present invention includes a wiring pattern formed on a front surface of an interposer substrate, mounting external terminals formed on a back surface, and a first semiconductor chip formed on a first semiconductor chip. An electrode extraction pad 7, a first metal post 8 formed on this pad and connected to the wiring pattern 2, and a position formed on the back surface of the first semiconductor chip and opposed to the first metal post 8 And a second electrode extraction pad 7 formed in the second semiconductor chip 9, and formed on this pad, exposed from the surface of the second semiconductor chip and inserted into the hole. A second metal post 8 connected to the first electrode extraction pad, and a resin 11 on the surface of the substrate 1 in which the first and second semiconductor chips are sealed.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device reduced to a CSP (Chip Size Package) level and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, with the miniaturization of mobile phones and information terminal devices, the size and weight of components mounted on printed circuit boards and the like have been required to be reduced. Required. Conventionally, for example, Japanese Patent Application Laid-Open No. H11-204720 discloses that element formation of first and second semiconductor chips 51 and 52 diced on an insulating substrate 55 having mounting external terminals 53 as shown in FIG. The electrodes are overlapped with the insulating adhesive layers 57 and 59 with the surface facing upward, and connected from each electrode pad to the wiring portion 58 on the insulating substrate 55 using a wire 54 of Au, Al or the like, and then sealed with a resin 56. A stacked-level CSP type semiconductor device that stops is disclosed.
[0003]
However, in the above-described semiconductor device, since wires are used, it is difficult to increase the density of the semiconductor chip by multi-layering due to swelling of the wires and the like. It is difficult to control the shape, and it is also difficult to reduce the thickness of the package.
[0004]
Therefore, recently, a through-electrode type three-dimensional stacked CSP type semiconductor device has been proposed. This semiconductor device is manufactured as follows. Vertical thin and deep holes (depth 70 to 100 μm / thickness about 30 μm) reaching the silicon substrate from the surface of the semiconductor chip are formed by etching, and an insulating layer, a metal adhesion layer, a seed layer, and a By embedding a Cu layer or the like by plating, a through electrode is formed in the deep hole, and further, the through electrode is caught from the back surface by grinding or etching to manufacture a semiconductor chip. The semiconductor chips manufactured as described above are three-dimensionally stacked, and the semiconductor chips thus stacked are connected to each other by through electrodes, thereby achieving conduction of each semiconductor chip. Then, these stacked semiconductor chips are arranged on an interposer substrate, and sealed with a resin together with the upper surface of the interposer substrate, whereby a three-dimensional stacked CSP type semiconductor device of a through-electrode type is manufactured.
[0005]
[Problems to be solved by the invention]
However, in such a semiconductor device, a vertical thin and deep hole reaching from the surface of the semiconductor chip to the silicon substrate is formed, and when forming a metal adhesion layer and a seed layer on the bottom surface and the inner side surface of the deep hole, a deep hole is formed. Since the holes are very deep, it is difficult to secure the coverage required for filling the Cu layer. If the metal adhesion layer and the seed layer are not sufficiently adhered, the through electrode may be disconnected. As described above, since there is a technical problem in forming a through electrode, there are problems in that yield and reliability are low, there are many problems in terms of cost, and it is difficult to provide a stable supply.
[0006]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device which does not need to bury a through electrode for connecting stacked semiconductor chips in a deep hole and a method of manufacturing the same. Is to provide.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, in a semiconductor device according to the present invention, a first semiconductor chip is arranged face down on a front surface of a substrate, and a second semiconductor chip is arranged face down on a back surface of the first semiconductor chip. A semiconductor device arranged,
A wiring pattern formed on the surface of the substrate,
Mounting external terminals formed on the back surface of the substrate and electrically connected to the wiring pattern;
A first electrode extraction pad formed on the first semiconductor chip;
A first conductive post formed on the first electrode extraction pad, exposed from the surface of the first semiconductor chip, and connected to the wiring pattern;
A hole formed on a back surface of the first semiconductor chip, formed at a position facing the first conductive post, and formed under the first electrode extraction pad;
A second electrode extraction pad formed on the second semiconductor chip;
A second conductive post formed on the second electrode extraction pad, exposed from the surface of the second semiconductor chip, inserted into the hole, and connected to the first electrode extraction pad;
A resin in which first and second semiconductor chips are sealed on the surface of the substrate;
Is provided.
[0008]
According to the above-described semiconductor device, conductive posts are arranged on the front surfaces of the first and second semiconductor chips, and holes are provided at positions on the back surface of the first semiconductor chip that face the conductive posts. Expose. Thus, the conductive post of the second semiconductor chip can be inserted into the electrode take-out pad in the hole of the first semiconductor chip, and this conductive post can be directly connected to the electrode take-out pad in the hole. Accordingly, it is possible to form a stacked three-dimensional CSP in which the semiconductor chips are stacked in the same direction while maintaining conduction between the first and second semiconductor chips. Therefore, unlike the conventional semiconductor device, it is not necessary to embed a through electrode for connecting the stacked semiconductor chips to each other in the deep hole, so that the metal adhesion layer and the seed layer are sufficiently provided on the bottom surface and the inner side surface of the deep hole. The problem of disconnection of the penetrating electrode due to non-attachment does not occur.
[0009]
A semiconductor device according to the present invention is a semiconductor device in which a second semiconductor chip is arranged face-down on a back surface of a first semiconductor chip,
A first electrode extraction pad formed on the first semiconductor chip;
A first conductive post formed on the first electrode extraction pad and exposed from a surface of the first semiconductor chip;
An external mounting terminal formed on the first conductive post;
A hole formed on a back surface of the first semiconductor chip, formed at a position facing the first conductive post, and formed under the first electrode extraction pad;
A second electrode extraction pad formed on the second semiconductor chip;
A second conductive post formed on the second electrode extraction pad, exposed from the surface of the second semiconductor chip, inserted into the hole, and connected to the first electrode extraction pad;
Is provided.
[0010]
According to the above-described semiconductor device, it is not necessary to embed a through electrode for connecting the stacked semiconductor chips to each other in a deep hole unlike the conventional semiconductor device. Further, since the mounting external terminals are formed on the conductive posts of the first semiconductor chip, the semiconductor device can be directly mounted on a circuit board or the like without using an interposer substrate.
[0011]
A semiconductor device according to the present invention is a semiconductor device in which a second semiconductor chip is arranged face-down on a back surface of a first semiconductor chip,
A first electrode extraction pad formed on the first semiconductor chip;
A first conductive post formed on the first electrode extraction pad and exposed from a surface of the first semiconductor chip;
An external mounting terminal formed on the first conductive post;
A hole formed on a back surface of the first semiconductor chip, formed at a position facing the first conductive post, and formed under the first electrode extraction pad;
A second electrode extraction pad formed on the second semiconductor chip;
A second conductive post formed on the second electrode extraction pad and exposed from a surface of the second semiconductor chip;
An external terminal formed on the second conductive post, inserted into the hole, and connected to the first electrode extraction pad;
Is provided.
[0012]
In addition, the semiconductor device according to the present invention may further include a reinforcing material that covers side surfaces of the first and second semiconductor chips and a back surface of the second semiconductor chip.
Further, in the semiconductor device according to the present invention, it is possible to further include an insulating film covering an inner side surface of the hole. Thereby, it is possible to prevent the contact leak from occurring due to the contact between the second conductive post and the inner side surface of the hole.
[0013]
Further, the semiconductor device according to the present invention may further include an insulating film covered on a side surface of the conductive post. Thereby, it is possible to prevent the contact leak from occurring due to the contact between the second conductive post and the inner side surface of the hole.
[0014]
A method of manufacturing a semiconductor device according to the present invention includes a substrate having a wiring pattern formed on a front surface, and mounting external terminals formed on a back surface and electrically connected to the wiring pattern, and a front surface of the substrate. A method for manufacturing a semiconductor device, comprising: a first semiconductor chip arranged face-down above; and a second semiconductor chip arranged face-down on the back surface of the first semiconductor chip,
Forming a first electrode take-out pad in the first semiconductor chip region; forming a first conductive post exposed from the surface of the first semiconductor chip region on the first electrode take-out pad; Forming a hole on the back surface of the first semiconductor chip region at a position facing the first conductive post by etching or laser processing to expose the first electrode extraction pad and thereby form a first semiconductor; A step of manufacturing a chip;
Forming a second electrode take-out pad in the second semiconductor chip region, and forming a second conductive post exposed from the surface of the second semiconductor chip region on the second electrode take-out pad; Producing a second semiconductor chip by
The second semiconductor chip is disposed face-down on the back surface of the first semiconductor chip, the second conductive post is inserted into the hole, and the second conductive post is removed from the first electrode. Connecting the first conductive chip to the wiring pattern, and placing the first semiconductor chip face-down on the surface of the substrate;
Sealing the first and second semiconductor chips with resin on the surface of the substrate;
Is provided.
[0015]
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising: a first semiconductor chip; and a second semiconductor chip arranged face-down on a back surface of the first semiconductor chip. So,
Forming a first electrode take-out pad in the first semiconductor chip region; forming a first conductive post exposed from the surface of the first semiconductor chip region on the first electrode take-out pad; A hole is formed on the back surface of the first semiconductor chip region at a position facing the first conductive post by etching or laser processing, and an external terminal is formed on the first conductive post to form a first terminal. Manufacturing a semiconductor chip,
Forming a second electrode take-out pad in the second semiconductor chip region, and forming a second conductive post exposed from the surface of the second semiconductor chip region on the second electrode take-out pad; Producing a second semiconductor chip by
The second semiconductor chip is disposed face-down on the back surface of the first semiconductor chip, the second conductive post is inserted into the hole, and the second conductive post is removed from the first electrode. Connecting to the pad for
Is provided.
[0016]
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising: a first semiconductor chip; and a second semiconductor chip arranged face-down on a back surface of the first semiconductor chip. So,
Forming a first electrode take-out pad in the first semiconductor chip region; forming a first conductive post exposed from the surface of the first semiconductor chip region on the first electrode take-out pad; By forming a hole at a position facing the first conductive post on the back surface of the first semiconductor chip region by etching or laser processing, and forming mounting external terminals on the first conductive post. Manufacturing a first semiconductor chip;
Forming a second electrode take-out pad in the second semiconductor chip region, and forming a second conductive post exposed from the surface of the second semiconductor chip region on the second electrode take-out pad; Forming a second semiconductor chip by forming external terminals on the second conductive post;
Disposing the second semiconductor chip face-down on the back surface of the first semiconductor chip, inserting the external terminal into the hole, and connecting the external terminal to the first electrode extraction pad When,
Is provided.
[0017]
In the method of manufacturing a semiconductor device according to the present invention, in the etching, a mask pattern is formed on a back surface of the first semiconductor chip, and a single crystal Si portion of the first semiconductor chip is formed using the mask pattern as a mask. Preferably, the hole is formed by wet etching using an alkaline aqueous solution and dry etching of the insulating film portion of the first semiconductor chip.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view schematically showing a semiconductor device according to a first embodiment of the present invention.
This semiconductor device has an interposer substrate 1, and a wiring pattern 2 is formed on an upper surface of the interposer substrate 1. Pads 4 are formed on the lower surface of the interposer substrate 1, and solder bumps 3 as external terminals for mounting are arranged below the pads 4. The solder bump 3 is connected to a pad 4, and the pad 4 is electrically connected to the wiring pattern 2 via a connection member 5.
[0019]
A first semiconductor chip 6 is arranged on the upper surface of the interposer substrate 1 by face-down bonding. Below the active surface (lower surface) of the first semiconductor chip 6, an electrode take-out pad 7 is arranged. Below the electrode take-out pad 7, a metal post (conductive post) 8 as an external terminal is formed. I have. This metal post 8 is connected to the wiring pattern 2 of the interposer substrate 1. Holes (deep holes) 6 a are formed on the back surface (the surface opposite to the active surface) of the first semiconductor chip 6 at a position facing the metal posts 8. The electrode extraction pad 7 is exposed by the hole 6a.
[0020]
A second semiconductor chip 9 is arranged on the back surface of the first semiconductor chip 6 by face-down bonding. The second semiconductor chip 9 is configured similarly to the first semiconductor chip 6. That is, an electrode take-out pad 7 is arranged below the active surface (lower surface) of the second semiconductor chip 9, and a metal post (conductive post) 8 as an external terminal is formed below the electrode take-out pad 7. Have been. The metal post 8 is connected to the electrode extraction pad 7 exposed through the hole (deep hole) 6a of the first semiconductor chip 6. A hole 6 a is formed on the back surface of the second semiconductor chip 9 at a position facing the metal post 8. The electrode extraction pad 7 is exposed by the hole 6a.
[0021]
A third semiconductor chip 10 is arranged on the back surface of the second semiconductor chip 9 by face-down bonding. The third semiconductor chip 10 has the same configuration as the first semiconductor chip 6. That is, an electrode take-out pad 7 is arranged below the active surface (lower surface) of the third semiconductor chip 10, and a metal post (conductive post) 8 as an external terminal is formed below the electrode take-out pad 7. Have been. The metal post 8 is connected to the electrode take-out pad 7 exposed by the hole (deep hole) 6a of the second semiconductor chip 9. A hole 6 a is formed on the back surface of the third semiconductor chip 10 at a position facing the metal post 8. The electrode extraction pad 7 is exposed by the hole 6a. On the upper surface of the interposer substrate 1, the first to third semiconductor chips 6, 9, 10 and the metal posts 8 are molded with a sealing resin 11.
[0022]
In this embodiment, the holes 6a are also formed in the third semiconductor chip 10 stacked on the uppermost layer. However, the holes are not necessarily required in the uppermost semiconductor chip, and the third semiconductor chip having no holes is formed. It is also possible to use chips.
Further, in the present embodiment, the metal post 8 is used, but it is also possible to use a conductive post made of a conductive material other than metal.
[0023]
Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a cross-sectional view in which the vicinity of a metal post and an electrode extraction pad of the first semiconductor chip shown in FIG. 1 is partially enlarged. FIG. 3 is a cross-sectional view showing a step subsequent to FIG.
First, as shown in FIG. 2, a semiconductor substrate (semiconductor wafer) 12 is prepared. Inside the semiconductor substrate 12, a semiconductor element such as a MOS transistor, various metal wirings electrically connected to the semiconductor element, an interlayer insulating film, and the like are formed.
[0024]
Next, a first etching stopper film 13 made of, for example, a silicon nitride film is formed on the semiconductor substrate 12 by a CVD (Chemical Vapor Deposition) method. Next, a first interlayer insulating film 14 made of a silicon oxide film is deposited on the first etching stopper film 13 by CVD, and a second interlayer insulating film 14 made of a silicon nitride film is deposited on the first interlayer insulating film 14 by CVD. An etching stopper film 15 is formed. Thereafter, a second interlayer insulating film 16 made of a silicon oxide film is deposited on the second etching stopper film 15. Next, a photoresist film (not shown) is applied on the second interlayer insulating film 16 and the photoresist film is exposed and developed, so that a connection hole is formed on the second interlayer insulating film 16. A resist pattern having an opening is formed.
[0025]
Next, the second interlayer insulating film 16, the second etching stopper film 15, and the first interlayer insulating film 14 are etched using the resist pattern as a mask. As a result, via holes (connection holes) 14 a are formed in the first and second interlayer insulating films 14 and 16 and the etching stopper film 15.
[0026]
Thereafter, after the resist pattern is stripped, a photoresist film (not shown) is applied on the second interlayer insulating film 16, and the photoresist film is exposed and developed. As a result, a resist pattern having an opening for forming a wiring groove is provided on the second interlayer insulating film 16. Next, the second interlayer insulating film 16 is etched using the resist pattern as a mask and the first and second etching stopper films 13 and 15 as stoppers. As a result, a wiring groove 16a is formed in the second interlayer insulating film 16, and the wiring groove 16a is connected to the via hole 14a.
[0027]
Next, after the first and second etching stopper films 13 and 15 are etched using the resist pattern as a mask, the resist pattern is removed.
Thereafter, an adhesion layer (barrier layer) 17 made of TaN, TiW or TiN is formed by sputtering in the via hole 14a, the wiring groove 16a and the second interlayer insulating film 16. Next, a Cu seed layer (not shown) for electrolytic plating is formed on the adhesion layer 17 by sputtering. Next, a Cu layer is formed on the Cu seed layer in the wiring groove 16a and the connection hole 14a by an electrolytic plating method.
[0028]
Thereafter, the Cu layer, the Cu seed layer, and the adhesion layer 17 existing on the second interlayer insulating film 16 are polished and removed by a CMP (chemical mechanical polishing) method. As a result, the Cu layer is buried in the via hole 14a of the first interlayer insulating film 14 and the wiring groove 16a of the second interlayer insulating film 16, and the Cu wiring 18 is formed in the wiring groove 16a. The Cu wiring 18 is electrically connected to a lower wiring (not shown) via a Cu layer embedded in the via hole 14a.
[0029]
Next, a third interlayer insulating film 19 made of a silicon nitride film is formed on the entire surface including the Cu wiring 18 by a plasma CVD method. Next, a fourth interlayer insulating film 20 made of a silicon oxide film is formed on the third interlayer insulating film 19 by a CVD method. Next, a photoresist film (not shown) is applied on the fourth interlayer insulating film 20, and the photoresist film is exposed and developed to form a resist pattern on the fourth interlayer insulating film 20. Is done.
[0030]
Thereafter, the fourth interlayer insulating film 20 and the third interlayer insulating film 19 are etched using the resist pattern as a mask, so that a via hole (connection hole) 19a is formed in the third interlayer insulating film 19. Next, after removing the resist pattern, a photoresist film (not shown) is applied on the fourth interlayer insulating film 20, and this photoresist film is exposed and developed. As a result, a resist pattern having an opening for forming a pad groove is provided on the fourth interlayer insulating film 20. Next, the fourth interlayer insulating film 20 is etched using the resist pattern as a mask and the third interlayer insulating film 19 as an etching stopper. Thus, a pad groove 20a is formed in the fourth interlayer insulating film 20, and the pad groove 20a is connected to the via hole 19a.
[0031]
Next, after the resist pattern is removed, an adhesion layer 21 made of a high melting point metal is formed by sputtering in the via hole 19a, the pad groove 20a, and the fourth interlayer insulating film 20. Next, a Cu seed layer (not shown) is formed on the adhesion layer 21 by sputtering. Next, a Cu layer is formed on the Cu seed layer by a plating method. Subsequently, the Cu layer and the adhesion layer 21 existing on the fourth interlayer insulating film 20 are polished and removed by CMP, so that the electrode extracting pad 7 is embedded in the pad groove 20a. Are electrically connected to the Cu wiring 18 by the Cu layer embedded in the via hole 19a.
[0032]
Next, a passivation film 22 made of a silicon nitride film is formed on the entire surface including the electrode extraction pad 7 by a CVD method. Next, a photoresist film (not shown) is applied on the passivation film 22, and the photoresist film is exposed and developed, whereby a resist pattern is formed on the passivation film 22. Next, the passivation film 22 is etched using the resist pattern as a mask, so that an opening portion located on the electrode extraction pad 7 is formed in the passivation film 22.
[0033]
Next, an adhesion layer 23 made of a refractory metal such as Ti, Ta, W, or the like, an alloy thereof, or a nitride film thereof is formed in the opening and on the passivation film 22 by sputtering. Next, a Cu seed layer 24 is sputtered continuously on the adhesion layer 23.
[0034]
Thereafter, a photoresist film (not shown) is applied or a photo film (not shown) is applied on the Cu seed layer 24 and the adhesion layer 23, and these are exposed and developed, so that the Cu seed layer 24 is exposed. Is formed with a resist pattern in which a post region is opened. Next, using this resist pattern as a mask, a Cu layer is formed on the Cu seed layer 24 in the opening by a selective plating method. Thereby, the metal post 8 made of the Cu layer is formed on the Cu seed layer. The thickness and size of the metal post made of a Cu plating film can be controlled relatively easily. Next, a dissimilar metal cap 25 made of Ni or Au is formed on the metal post 8 by a plating method. Next, after removing the resist pattern, the adhesion layer 23 is etched using the metal post 8 and the Cu seed layer 24 as a mask.
[0035]
Next, the entire surface including the metal post 8 is covered with a protective tape (not shown), and the back surface of the semiconductor wafer 12 is ground to a predetermined thickness. Next, a photosensitive polyimide film 26 is applied on the back surface of the semiconductor wafer 12, and the polyimide film 26 is exposed and developed to have an opening at a position facing the metal post 8 on the back surface side of the wafer 12. A polyimide pattern 26 is formed.
[0036]
Then, using the polyimide pattern 26 as a mask, the single-crystal Si portion is wet-etched or ₂ Gas, HBr gas, SF ₆ Dry etching using a gas or a mixed gas of these gases, and ₄ Gas, CHF ₃ Gas, SF ₆ Dry etching with gas. As a result, a deep hole 6a is formed on the back surface of the wafer 12, and the adhesive layer 21 below the electrode extraction pad 7 is exposed by the deep hole 6a. After the metal posts 8 are formed on the chip surface at the wafer level and the deep holes 6a are formed on the chip back surface, the electrical characteristics are checked. Thereafter, the wafer is divided into chips in a dicing process.
[0037]
As described above, when the single-crystal Si portion is wet-etched, a tapered hole is formed. Therefore, the arrangement margin of the metal post can be increased, and the show of Si and the metal post can be prevented. Further, when dry etching is performed on the portion of the interlayer insulating film, side etching and the occurrence of unevenness can be suppressed, and corrosion of the metal of the electrode extraction pad can be suppressed. Therefore, the yield can be improved.
[0038]
In the present embodiment, when forming the deep hole 6a, the polyimide film 26 is used as an etching mask. However, the present invention is not limited to this, and other etching masks, for example, a thick photomask using a double-sided aligner may be used. A sheet may be used as a mask, a hard mask such as an oxide film may be used, or deep holes may be formed by another processing method, for example, using a laser. However, when a hard mask such as an oxide film is used, the number of steps is increased by a photolithography step and an etching step for patterning the hard mask. When a deep hole is formed by using a laser, it is possible to perform processing without using a mask.
[0039]
Then, the divided good chips are stacked and stacked. That is, as shown in FIG. 1, the first to third semiconductor chips 6, 9, and 10 are overlapped, and the metal post 8 of the second semiconductor chip 9 is inserted into the hole 6 a of the first semiconductor chip 6. This metal post 8 is connected to the electrode extraction pad 7 of the first semiconductor chip, the metal post 8 of the third semiconductor chip 10 is inserted into the hole 6a of the second semiconductor chip 9, and this metal post 8 is It is connected to the electrode extraction pad 7 of the second semiconductor chip. FIG. 3 shows a state in which the electrode extraction pad 7 and the metal post 8 are connected. If an insulating adhesive or an adhesive sheet (not shown) is arranged between the semiconductor chips 6, 9, 10, stress buffering between the chips, reinforcement or prevention of intrusion of moisture can be prevented, and reliability can be improved.
[0040]
Next, the interposer substrate 1 is prepared, and the metal posts 8 of the first semiconductor chip 6 are connected to the wiring patterns 2 of the interposer substrate 1. Next, the upper surfaces of the first to third semiconductor chips and the interposer substrate 1 are molded with a sealing resin 11. Next, the solder bumps 3 are attached to the pads 4 on the lower surface of the interposer substrate 1. Thus, a semiconductor device is formed.
[0041]
According to the first embodiment, in the first and second semiconductor chips 6 and 9, the metal posts 8 are arranged as external terminals on the front surface, and the deep holes 6 a are provided at positions on the rear surface facing the metal posts 8. Then, the electrode extracting pad 7 is exposed by the deep hole 6a. As a result, the metal post 8 of the second semiconductor chip 9 can be directly connected to the electrode extraction pad 7 in the deep hole 6a of the first semiconductor chip 6, and the inside of the deep hole 6a of the second semiconductor chip 9 can be connected. The metal post 8 of the third semiconductor chip 10 can be directly connected to the electrode extraction pad 7. That is, a deep hole 6a reaching the electrode take-out pad 7 from the back surface of the semiconductor chip can be formed, and the metal posts 8 on the other semiconductor chip surface can be stacked so as to contact the electrode take-out pad 7. Therefore, it is possible to form a stacked three-dimensional CSP in which the semiconductor chips are stacked in the same direction while maintaining conduction between the first to third semiconductor chips. Therefore, in the present embodiment, it is not necessary to embed a through electrode for connecting the stacked semiconductor chips to each other in a deep hole unlike a conventional semiconductor device, so that a metal adhesion layer is formed on the bottom surface and the inner side surface of the deep hole. In addition, the problem of disconnection of the through electrode due to insufficient attachment of the seed layer does not occur.
[0042]
Further, since it is not necessary to embed the through-electrode in the deep hole, there is no possibility that Cu is diffused by heat treatment in the molding or assembling process to cause deterioration of the semiconductor element and leakage between terminals.
[0043]
In the first embodiment, the metal posts are formed by plating on the first to third semiconductor chips 6, 9, and 10. However, the present invention is not limited to this. It is also possible to form metal posts on the third semiconductor chip by solder balls.
Further, in the present embodiment, a semiconductor device in which three semiconductor chips are stacked on the interposer substrate 1 is described. However, a semiconductor device in which two or four or more semiconductor chips are stacked on the interposer substrate may be used. It is possible.
[0044]
FIG. 4 is a cross-sectional view showing a modified example of the metal post, the electrode extraction pad, and the hole in FIG. 2. The same parts as those in FIG. 2 are denoted by the same reference numerals, and only different parts will be described.
After the hole 6a is formed as shown in FIG. 2, the polyimide pattern is removed, a photosensitive polyimide film 27 is applied on the back surface of the semiconductor wafer 12, and the polyimide film 27 is exposed and developed to form the hole 6a. An opening is formed below the electrode take-out pad 7 in the inside, and the electrode take-out pad 7 is exposed by this opening to secure a contact area with the metal post. Next, the polyimide film is heat-treated at a temperature of 200 to 300C.
[0045]
According to the above modification, since the inner side surface of the hole 6a is covered with the polyimide film, a metal post is inserted into the hole 6a, and when the metal post is connected to the electrode extraction pad 7, the metal post is displaced. Thus, even if the metal post contacts the inner side surface of the hole 6a, it is possible to prevent the occurrence of contact leakage. Therefore, it is possible to increase a margin when the semiconductor chips are stacked face-down and assembled. For this reason, yield and reliability can be improved.
[0046]
In the above modification, the inner surface of the hole 6a is covered with a polyimide film. However, the inner surface of the hole 6a may be covered with another insulating film. For example, a silicon oxide film or a silicon oxide film formed by a CVD method may be used. It is also possible to cover the inner surface of the hole with a nitride film.
[0047]
Further, in the above modification, the inner surface of the hole is covered with an insulating film in order to prevent the occurrence of contact leak between the metal post and the inner surface of the hole, but the inner surface of the hole is not covered with the insulating film. By covering the side surfaces of the metal posts with an insulating film (eg, resin, polyimide, silicon oxide film, silicon nitride film, etc.), it is possible to prevent the occurrence of contact leak.
[0048]
FIG. 5 is a sectional view schematically showing a semiconductor device according to the second embodiment of the present invention.
This semiconductor device has a first semiconductor chip 28, and an electrode extraction pad 7 is arranged on the active surface side (lower surface side) of the first semiconductor chip 28. A metal post (conductive post) 8 is formed below the electrode take-out pad 7. A sealing resin 29 such as epoxy is formed on the side surface of the metal post 8 and the lower surface of the first semiconductor chip 28, and the upper surface of the metal post 8 is exposed from the sealing resin 29. External terminals 30 such as solder balls are formed on the exposed upper surfaces of the metal posts 8. A hole (deep hole) 6 a is formed on the back surface (the surface opposite to the active surface) of the first semiconductor chip 28 at a position facing the metal post 8. The electrode extraction pad 7 is exposed by the hole 6a.
[0049]
On the back surface of the first semiconductor chip 28, a second semiconductor chip 31 is arranged by face-down bonding. The second semiconductor chip 31 is configured similarly to the first semiconductor chip 28. That is, the electrode extraction pad 7 is arranged on the active surface side (lower surface side) of the second semiconductor chip 31. A metal post (conductive post) 8 is formed below the electrode take-out pad 7. A sealing resin 29 such as epoxy is formed on the side surface of the metal post 8 and the lower surface of the second semiconductor chip 31, and the upper surface of the metal post 8 is exposed from the sealing resin 29. External terminals 30 such as solder balls are formed on the exposed upper surfaces of the metal posts 8. The external terminal 30 is inserted into the hole 6a of the first semiconductor chip, and the external terminal 30 is directly connected to the electrode extraction pad 7 in the hole 6a. A hole (deep hole) 6 a is formed on the back surface (the surface opposite to the active surface) of the second semiconductor chip 31 at a position facing the metal post 8. The electrode extraction pad 7 is exposed by the hole 6a.
[0050]
On the back surface of the second semiconductor chip 31, a third semiconductor chip 32 is arranged by face-down bonding. The third semiconductor chip 32 has the same configuration as the first semiconductor chip 6. That is, the electrode extraction pad 7 is arranged on the active surface side (lower surface side) of the third semiconductor chip 32. A metal post (conductive post) 8 is formed below the electrode take-out pad 7. A sealing resin 29 such as epoxy is formed on the side surface of the metal post 8 and the lower surface of the third semiconductor chip 32, and the upper surface of the metal post 8 is exposed from the sealing resin 29. External terminals 30 such as solder balls are formed on the exposed upper surfaces of the metal posts 8. The external terminal 30 is inserted into the hole 6a of the second semiconductor chip, and the external terminal 30 is directly connected to the electrode extraction pad 7 in the hole 6a. Holes (deep holes) 6 a are formed on the back surface of the third semiconductor chip 32 (the surface opposite to the active surface) at a position facing the metal posts 8. The electrode extraction pad 7 is exposed by the hole 6a.
[0051]
In the present embodiment, the holes 6a are also formed in the third semiconductor chip 32 stacked on the uppermost layer. However, the holes are not necessarily required in the uppermost semiconductor chip, and the third semiconductor without the holes is formed. It is also possible to use chips.
Further, in the present embodiment, the metal post 8 is used, but it is also possible to use a conductive post made of a conductive material other than metal.
[0052]
Next, a method of manufacturing the semiconductor device shown in FIG. 5 will be described with reference to FIG. FIG. 6 is a partially enlarged cross-sectional view showing the vicinity of the metal posts and the electrode extraction pads of the first and second semiconductor chips shown in FIG.
The process of forming the metal post 8 on the semiconductor substrate (semiconductor wafer) 12 shown in FIG. 6 and forming the dissimilar metal cap 25 on the metal post 8 is the same as that of the first embodiment shown in FIG. Therefore, the description is omitted.
[0053]
Next, a sealing resin 46 such as epoxy is molded by a molding device so as to cover the passivation film 44 and the metal posts 8. Next, the sealing resin 46 is ground to a desired amount by a grinder (not shown). Here, the desired amount is a grinding amount such that the head (upper part) of the metal post is exposed.
[0054]
Next, the entire surface including the metal post 8 is covered with a protective tape (not shown), and the back surface of the semiconductor wafer 14 is ground to a predetermined thickness. Next, a deep hole 6a is formed on the back surface of the wafer 14 by the same method as in the first embodiment, and the adhesive layer 31 below the electrode extraction pad 7 is exposed by the deep hole 6a. After the metal posts 8 are formed on the chip surface at the wafer level and the deep holes 6a are formed on the chip back surface, the electrical characteristics are checked.
[0055]
Thereafter, a flux (not shown) is applied to the exposed portions of the metal posts 8, and then the solder balls 30 are mounted on the required metal posts by an automatic mounting machine. Next, heat treatment is performed on the metal post and the solder ball 30 at about 170 to 200 ° C. Thus, the solder balls 30 are fused on the metal posts 19 as shown in FIG.
[0056]
In addition, it is preferable to use a solder ball 30 for a ball grid array (BGA) made of a material having a diameter of 150 to 300 μm and Pb / Sn of 60 to 70 wt%. Further, the size of the solder ball can be appropriately selected according to the application. For the solder composition, an Ag / Sn-based material or a Pb-less material containing Cu or Bi can be used.
[0057]
Thereafter, the first semiconductor chip 28 can be manufactured by cutting the resin 29 and the semiconductor wafer along a scribe line using a dicing saw or a laser.
Next, the first to third semiconductor chips, which are divided good chips, are stacked and stacked. That is, as shown in FIG. 5, the first to third semiconductor chips 28, 31, and 32 are stacked, and the external terminals 30 of the second semiconductor chip 31 are inserted into the holes 6a of the first semiconductor chip 28, This external terminal 30 is connected to the electrode take-out pad 7 of the first semiconductor chip, and the external terminal 30 of the third semiconductor chip 32 is inserted into the hole 6a of the second semiconductor chip 31. It is connected to the electrode extraction pad 7 of the second semiconductor chip. FIG. 6 shows a state in which the electrode extraction pad 7 and the external terminal 30 are connected.
[0058]
Thus, the semiconductor device shown by 77 is manufactured, and this semiconductor device can be directly mounted on a circuit board or the like.
The second embodiment can be modified as follows. In the present embodiment, the second and third semiconductor chips 9 and 10 shown in FIG. 1 can be used instead of the second and third semiconductor chips 31 and 32 shown in FIG. That is, the solder balls 30 of the second and third semiconductor chips 31 and 32 may be replaced with metal posts.
[0059]
In addition, an adhesive is disposed between the back surface of the first semiconductor chip 29 and the surface of the sealing resin 29 of the second semiconductor chip 31, and the first semiconductor chip and the second semiconductor chip are separated by the adhesive. Can be securely fixed. Further, an adhesive is disposed between the back surface of the second semiconductor chip 31 and the surface of the sealing resin 29 of the third semiconductor chip 32, and the second semiconductor chip and the third semiconductor chip are separated by this adhesive. Can be securely fixed. In addition to reinforcement between chips, these adhesives can also reduce stress buffering or prevent intrusion of moisture and improve reliability.
[0060]
Further, the inner side surface of the hole 6a can be covered with an insulating film such as a polyimide film, a silicon oxide film or a silicon nitride film. Accordingly, when the external terminal 30 is inserted into the hole 6a and the external terminal 30 is connected to the electrode extraction pad 7, even if the external terminal is displaced and comes into contact with the inner side surface of the hole 6a, The occurrence of contact leak can be prevented. Therefore, it is possible to increase a margin when the semiconductor chips are stacked face-down and assembled. For this reason, yield and reliability can be improved.
[0061]
In the second embodiment, the same effects as in the first embodiment can be obtained.
Further, in this embodiment, the external terminals 30 such as solder balls are formed on the metal posts 8 of the first semiconductor chip 29, and the semiconductor device can be directly mounted on a circuit board or the like without using an interposer substrate. . Therefore, the size can be further reduced as compared with the first embodiment.
[0062]
FIG. 7 is a sectional view schematically showing a semiconductor device according to a third embodiment of the present invention. The same parts as those in FIG. 5 are denoted by the same reference numerals, and only different parts will be described.
In the semiconductor device according to the present embodiment, the first to third semiconductor chips 28, 31, 32 are securely fixed by covering the side surface and the back surface of the semiconductor device shown in FIG. Is to reinforce.
[0063]
Also in the third embodiment, the same effects as in the second embodiment can be obtained.
The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example, the above-described semiconductor device can be applied to various LSIs such as a memory and a logic. An example of mounting the semiconductor device is a printed circuit board of an electronic device. Wiring is patterned on the printed circuit board in accordance with a circuit of the semiconductor device. Mounted on
[Brief description of the drawings]
FIG. 1 is a sectional view schematically showing a semiconductor device according to a first embodiment.
FIG. 2 is an enlarged sectional view of a part of the first semiconductor chip shown in FIG. 1;
FIG. 3 is an enlarged cross-sectional view of a part of the first and second semiconductor chips shown in FIG. 1;
FIG. 4 is a sectional view showing a modification of the semiconductor device shown in FIG. 2;
FIG. 5 is a sectional view schematically showing a semiconductor device according to a second embodiment;
FIG. 6 is an enlarged sectional view of a part of the first and second semiconductor chips shown in FIG. 5;
FIG. 7 is a sectional view schematically showing a semiconductor device according to a third embodiment;
FIG. 8 is a sectional view schematically showing an example of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Interposer board, 2 ... Wiring pattern, 3 ... Solder bump, 4 ... Pad, 5 ... Connection member, 6 ... First semiconductor chip, 6a ... Deep hole (hole), 7 ... Pad for electrode extraction, 8 ... Metal post , 9: second semiconductor chip, 10: third semiconductor chip, 11: sealing resin, 12: semiconductor substrate (semiconductor wafer), 13: first etching stopper film, 14: first interlayer insulating film, 14a: Connection hole, 15: Second etching stopper film, 16: Second interlayer insulating film, 16a: Wiring groove, 17: Adhesion layer (barrier layer), 18: Cu wiring, 19: Third interlayer insulation Film, 19a: via hole (connection hole), 20: fourth interlayer insulating film, 20a: pad groove, 21: adhesion layer (barrier layer), 22: passivation film, 23: adhesion layer, 24: Cu seed layer, 25 ... different Metal cap, 26: polyimide pattern (polyimide film), 27: polyimide film, 28: first semiconductor chip, 29: sealing resin, 30: external terminal (solder ball), 31: second semiconductor chip, 32 ... Third semiconductor chip, 33 ... reinforcing material

Claims (10)

A semiconductor device in which a first semiconductor chip is arranged face down on a front surface of a substrate, and a second semiconductor chip is arranged face down on a back surface of the first semiconductor chip,
A wiring pattern formed on the surface of the substrate,
Mounting external terminals formed on the back surface of the substrate and electrically connected to the wiring pattern;
A first electrode extraction pad formed on the first semiconductor chip;
A first conductive post formed on the first electrode extraction pad, exposed from the surface of the first semiconductor chip, and connected to the wiring pattern;
A hole formed on a back surface of the first semiconductor chip, formed at a position facing the first conductive post, and formed under the first electrode extraction pad;
A second electrode extraction pad formed on the second semiconductor chip;
A second conductive post formed on the second electrode extraction pad, exposed from the surface of the second semiconductor chip, inserted into the hole, and connected to the first electrode extraction pad;
A resin in which first and second semiconductor chips are sealed on the surface of the substrate;
A semiconductor device comprising: A semiconductor device in which a second semiconductor chip is disposed face-down on a back surface of a first semiconductor chip,
A first electrode extraction pad formed on the first semiconductor chip;
A first conductive post formed on the first electrode extraction pad and exposed from a surface of the first semiconductor chip;
An external mounting terminal formed on the first conductive post;
A hole formed on a back surface of the first semiconductor chip, formed at a position facing the first conductive post, and formed under the first electrode extraction pad;
A second electrode extraction pad formed on the second semiconductor chip;
A second conductive post formed on the second electrode extraction pad, exposed from the surface of the second semiconductor chip, inserted into the hole, and connected to the first electrode extraction pad;
A semiconductor device comprising: A semiconductor device in which a second semiconductor chip is disposed face-down on a back surface of a first semiconductor chip,
A first electrode extraction pad formed on the first semiconductor chip;
A first conductive post formed on the first electrode extraction pad and exposed from a surface of the first semiconductor chip;
An external mounting terminal formed on the first conductive post;
A hole formed on a back surface of the first semiconductor chip, formed at a position facing the first conductive post, and formed under the first electrode extraction pad;
A second electrode extraction pad formed on the second semiconductor chip;
A second conductive post formed on the second electrode extraction pad and exposed from a surface of the second semiconductor chip;
An external terminal formed on the second conductive post, inserted into the hole, and connected to the first electrode extraction pad;
A semiconductor device comprising: 4. The semiconductor device according to claim 2, further comprising a reinforcing member that covers side surfaces of the first and second semiconductor chips and a back surface of the second semiconductor chip. 5. The semiconductor device according to claim 1, further comprising an insulating film covering an inner side surface of the hole. The semiconductor device according to claim 1, further comprising an insulating film covered on a side surface of the conductive post. A substrate having a wiring pattern formed on the front surface, and mounting external terminals formed on the back surface and electrically connected to the wiring pattern; and a first substrate arranged face-down on the front surface of the substrate. A method for manufacturing a semiconductor device, comprising: a semiconductor chip; and a second semiconductor chip disposed face-down on a back surface of the first semiconductor chip,
Forming a first electrode take-out pad in the first semiconductor chip region; forming a first conductive post exposed from the surface of the first semiconductor chip region on the first electrode take-out pad; Forming a hole on the back surface of the first semiconductor chip region at a position facing the first conductive post by etching or laser processing to expose the first electrode extraction pad and thereby form a first semiconductor; A step of manufacturing a chip;
Forming a second electrode take-out pad in the second semiconductor chip region, and forming a second conductive post exposed from the surface of the second semiconductor chip region on the second electrode take-out pad; Producing a second semiconductor chip by
The second semiconductor chip is disposed face-down on the back surface of the first semiconductor chip, the second conductive post is inserted into the hole, and the second conductive post is removed from the first electrode. Connecting the first conductive chip to the wiring pattern, and placing the first semiconductor chip face-down on the surface of the substrate;
Sealing the first and second semiconductor chips with resin on the surface of the substrate;
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device, comprising: a first semiconductor chip; and a second semiconductor chip arranged face-down on a back surface of the first semiconductor chip,
Forming a first electrode take-out pad in the first semiconductor chip region; forming a first conductive post exposed from the surface of the first semiconductor chip region on the first electrode take-out pad; A hole is formed on the back surface of the first semiconductor chip region at a position facing the first conductive post by etching or laser processing, and an external terminal is formed on the first conductive post to form a first terminal. Manufacturing a semiconductor chip,
Forming a second electrode take-out pad in the second semiconductor chip region, and forming a second conductive post exposed from the surface of the second semiconductor chip region on the second electrode take-out pad; Producing a second semiconductor chip by
The second semiconductor chip is disposed face-down on the back surface of the first semiconductor chip, the second conductive post is inserted into the hole, and the second conductive post is removed from the first electrode. Connecting to the pad for
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device, comprising: a first semiconductor chip; and a second semiconductor chip arranged face-down on a back surface of the first semiconductor chip,
Forming a first electrode take-out pad in the first semiconductor chip region; forming a first conductive post exposed from the surface of the first semiconductor chip region on the first electrode take-out pad; By forming a hole at a position facing the first conductive post on the back surface of the first semiconductor chip region by etching or laser processing, and forming mounting external terminals on the first conductive post. Manufacturing a first semiconductor chip;
Forming a second electrode take-out pad in the second semiconductor chip region, and forming a second conductive post exposed from the surface of the second semiconductor chip region on the second electrode take-out pad; Forming a second semiconductor chip by forming external terminals on the second conductive post;
Disposing the second semiconductor chip face-down on the back surface of the first semiconductor chip, inserting the external terminal into the hole, and connecting the external terminal to the first electrode extraction pad When,
A method for manufacturing a semiconductor device comprising: In the etching, a mask pattern is formed on the back surface of the first semiconductor chip, and the single crystal Si portion of the first semiconductor chip is wet-etched using an alkaline aqueous solution using the mask pattern as a mask. 10. The method of manufacturing a semiconductor device according to claim 7, wherein the holes are formed by dry-etching an insulating film portion of the semiconductor chip.

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