JPH02199936A - Digital radio transmitter - Google Patents

Abstract

PURPOSE:To improve the line utilizing efficiency by stopping the operation of an error correction function depending on the quality of line and using the function as the transmission of a sub signal. CONSTITUTION:A parity signal, switching control signal, synchronizing signal inserting device 13, a switch 16, a parity signal, switching control signal, synchronous signal detector 17, a line quality detector 30 and a switching control signal detector 31 constitute a means operating an error correction function at the deterioration of line quality and stopping the error correction function with the excellent line quality. The line quality detector 30 receives a parity signal 214 to detect the quality of line and to discriminate the presence of the necessity of error correction and sends a switching control signal 209 to an error correction device 26, a speed converter 25 and a switching control signal insertion device of a reverse line transmission section.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digital wireless transmission device having an error correction function, and more particularly to a digital wireless transmission device that uses the error correction function as a sub-signal. .

[Conventional technology]

In digital wireless transmission equipment, an error correction function is added to improve the quality of the wireless section.The error correction function in conventional digital wireless transmission equipment involves speed conversion of the main signal to be transmitted in the transmitter. Then, redundant bits necessary for error 9 correction are provided for a certain block length, and the calculation result of data within the certain block length is inserted into the redundant bits and transmitted. Furthermore, in the receiving section, data within a certain block length is calculated in the same manner as in the transmitting section, and errors are detected and corrected by comparing the result of the calculation with the received redundant bits.

[Problem to be solved by the invention]

In the digital wireless transmission equipment that uses the conventional error correction function described above, calculations are always performed regardless of the line quality, so the error correction function is meaningless when the line quality is good. However, there was a problem in that the efficiency of line usage decreased.

[Means to solve the problem]

The digital wireless transmission device of the present invention is! la! A digital wireless transmission device having a correction function, comprising means for operating the error correction function when line quality deteriorates, and means for stopping the error correction function when line quality is good,
This signal is designed to transmit information as a sub-signal.

[Effect]

In the present invention, the operation of the error correction function is stopped depending on the line quality and is used for sub-signal transmission.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of a transmitting section showing an embodiment of the present invention.

In the figure, 11 is a speed converter which inputs the main signal 101, and 12 is a timing signal 103 to this speed converter 11.
13 is a parity signal, switching control signal, and synchronization signal inserter which inputs the high-speed signal 102 from the speed converter 11 and the timing signal 104 from the timing generator 12; 14 is a timing generator 12
15 is a timing generator 12, which receives a timing signal 108, a parity signal, a switching control signal, a synchronization signal inserter 13, and a high-speed signal 105;
16 is a switch that switches between the calculation result 108 from the error correction calculator 14 and the sub signal 109 from the speed converter 15, and 1T is a parity signal. .

High-speed signal 10 from switching control signal and synchronization signal inserter 13
5, a multiplexer which inputs either the signal 110 of the calculation result 108 from the switch 16 or the sub-signal 109 from the speed converter 15, and 18 inputs the multiplexed signal 111 from the multiplexer 17. This is a modulator that 112 is a transmission signal, 113 is a switching signal for the receiving section, and 115 is a switching control signal for the receiving section.

FIG. 2 is a block diagram of a receiving section showing an embodiment of the present invention.

In the figure, 21 is a demodulator that demodulates the received signal 201;
22 is a delay device which receives the demodulated signal 202 from the demodulator 21, 23 is an error correction calculator which receives the demodulated signal 202 from the demodulator 21, and 24 receives the demodulated signal 202 from the demodulator 21. 25 is a speed converter which inputs the sub signal 20B from the sub signal separator 24, and 26 is a delayed demodulated signal 203 from the delay device 22.
and an error corrector which receives as input a calculation result 204 from the error correction calculator 23 and a switching control signal 209 from a line quality detector to be described later, and 27 is a demodulated signal 211 from the error corrector 26 and a timing to be described later. A parity signal, a switching control signal, and a synchronization signal detector 28 receive a synchronization signal 212 from the detector as input, and a timing detection unit 28 includes the parity signal, the switching control signal, a high-speed signal 216 from the synchronization signal detector 21, and timing detection described later. 29 is a timing detector; 30 is an expanded parity signal;

A line quality detector which receives the switching control signal and the parity signal 214 from the synchronization signal detector 2T; 31 is a parity detector;
It is a switching control signal detector that receives signals, switching control signals, and switching control signals 215 from the synchronization signal detector 2T.
210 is a sub signal sent from the speed converter 25, 21T
is a main signal sent from the speed converter 28, and 218 is a switching signal sent to the transmitter.

Then, the parity signal and switching control signal shown in FIG.
The synchronization signal inserter 13, the switch 16, the parity signal, the switching control signal, the synchronization signal detector 2T, the line quality detector 30, and the switching control signal detector 31 shown in FIG.
It constitutes means for operating the error correction function when the line quality is degraded and means for stopping the error correction function when the line quality is good.

In addition, the transmitting section shown in Fig. 1 and the receiving section shown in Fig. 2 operate the *#) correction function when the line quality deteriorates, and when the line quality is good! It is configured to stop the @shi correction function and transmit information as a sub signal.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the main signal 101 is processed by the speed converter 11, including redundant bits for inserting error correction calculation results, synchronization bits, parity bits for line quality monitoring, and switching control signals for stopping the error correction function and inserting subsignals. The data bit is converted into a high-speed signal 102 by a timing signal 103 generated by a timing generator INC.

In the parity signal, switching control signal, and synchronization signal inserter 13, a synchronization bit for synchronization in the receiving section,
A parity pit is used to monitor line quality, and a bit for a switching control signal is used to control a switch in the transmitter using the transmitter on the opposite line, which uses the result of determining that the line quality is good in the receiver. It is inserted by the timing signal 104. Further, a high-speed signal 105 containing a parity signal and a switching control signal is supplied to a multiplexer 17 and an error correction calculator 14.

Next, the error correction calculator 14 calculates the main signal, parity signal, and switching control signal included in the high-speed signal 105 using the timing signal 106, and sends the calculation result 108 to the switch 16.

The speed converter 15 converts the sub-signal 114 to the same timing as the redundant bit using the timing signal 107, and sends it to the switch 16 as the sub-signal 109.

In the switching device 16, a switching signal detector (not shown) detects a switching control signal sent from the transmitting section of the reverse line, and switches between the calculation result 108 and the sub-signal 109.

Then, in the multiplexer 1T, the main signal, parity signal,
Multiplexing the switching control signal and the calculation result or sub-signal,
The multiplexed signal 111 is adjusted by a modulator 18 and sent out as a transmission signal 112.

Note that 110 is either the calculation result 108 or the sub signal 109 switched by the switch 16.

Next, the operation of the embodiment shown in FIG. 2 will be explained. First, a received signal 201 is demodulated by a demodulator 21. The demodulated signal 202 is input to a delay device 22, an error correction calculator 23, and a sub-signal separator 24.

The delay unit 22 has a delay corresponding to the calculation time in order to hold the error correction calculation time. The xb correction calculator 23 performs a calculation similar to that of the transmitter based on the timing signal 205, and sends out the calculation result 204. Sub signal separator 24
Then, the sub-signal 208 is separated by the timing signal 206 and sent to the speed converter 25.

The speed converter 25 uses the timing pulse 207 to convert the sub-signal having the same timing as the calculation result converted by the transmitter to the timing of the input sub-signal. Further, a sub-signal 210 is sent out in response to a switching control signal 209 from the line quality detector 30.

Next, the error υ corrector 26 corrects the demodulated signal 203 delayed by the calculation result 204K. Further, the υ correction function is stopped by the switching control signal 209 from the line quality detector 30, and the demodulated signal 211 is directly sent to the parity signal, switching control signal, and synchronization signal detector 27.

The timing signal detector 29 establishes synchronization using the parity signal, the switching control signal, and the synchronization signal 212 sent from the synchronization signal detector 27, and the line quality detector 30 sends it out as a timing pulse. , detects the line quality using the parity signal 214, determines whether error correction is necessary, and sends the switching control signal 209 to the error corrector 26.
and is sent to the speed converter 25 and a switching control signal inserter (not shown) of the reverse line transmitter. Switching control signal detector 31
Then, the switching control signal 215 is used to confirm whether or not the error correction function is necessary depending on the line quality of the reverse line receiving section, and a switching signal 218 is sent to the switch (not shown) of the reverse line transmitting section.
Switch the reverse line to the calculation result or sub signal.

The speed converter 28 uses the timing pulse 213 from the timing signal detector 29 to remove the parity signal bit, switching control signal bit, synchronization signal bit, and redundant bit added by the transmitter, and sends out the main signal 217. .

〔Effect of the invention〕

As described above, the present invention has the effect of improving the efficiency of line use by stopping the operation of the error correction function depending on the line quality and using it for sub-signal transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmitting section showing an embodiment of the present invention, and FIG. 2 is a block diagram of a receiving section showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Speed converter, 1211... Timing generator, 13... Parity signal, switching control signal, synchronous signal inserter, 14... Error correction calculator, 15.e
・・Speed converter, 164・φ・switcher, 1T・・Multiplexer, 18・・Fist modulator, 21・・・Demodulator, 2
2...Delay unit, 23...Error correction calculator, 24
... Sub signal separator, 25 ... Speed converter, 26
...Error corrector, 27...Parity signal. Switching control signal, synchronization signal detector, 28... Speed converter, 29... Φ timing detector, 30... Line quality detector, 31. Fist - Switching control signal detector.

Claims (1)

[Claims] In digital wireless transmission equipment with error correction function,
Digital wireless transmission characterized by comprising means for operating the error correction function when line quality deteriorates and means for stopping the error correction function when line quality is good, and for transmitting information as a sub signal. Device.