JPH0583012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device fault signal transmission circuit, and in particular, to a device fault signal transmission circuit that transmits a device fault signal when a device fault occurs in a transmitting end side interface conversion circuit in wireless digital transmission. The present invention relates to an equipment failure signal transmission circuit suitable for transmission.

[Conventional technology]

In conventional wireless digital transmission, if a device failure occurs in the interface conversion circuit on the transmitting side,
As a method of transmitting the equipment failure to the receiving side, a method has been adopted in which the transmitting side stops transmitting a frame synchronization signal and the receiving side detects the frame synchronization loss.

FIG. 2 is a block diagram of a conventional equipment failure signal transmission circuit. The figure omits modulation/demodulation and transmission/reception functions.

On the sending end side of the figure, 1 is a sending end interface conversion circuit, and 2 is a fault detection circuit, both of which are input with the device interface input signal 101. This sending end interface conversion circuit 1
converts the interface code format of the device interface input signal 101 to NRZ (Non Return to
Zero) signal so that it can be processed by the sending-end synchronous conversion circuit 3 and the sending-end multiplex conversion circuit 4.

On the other hand, the fault detection circuit 2 inputs the equipment interface input signal 101, the output signal 102 of the sending-end interface conversion circuit 1, and the monitor signal 103 inside the sending-end interface conversion circuit 1, and detects the sending-end interface. A fault in the conversion circuit 1 is detected.

The sending end synchronous conversion circuit 3 performs synchronous conversion in order to multiplex an auxiliary signal and the like onto the output signal 102 of the sending end interface conversion circuit 1. Synchronous conversion is
Based on the conventionally well-known pulse stuffing method. The synchronous conversion signal 105 that has been subjected to synchronous conversion is input to the sending end multiplex conversion circuit 4, where it multiplexes the auxiliary signal 107 and a frame synchronization signal necessary for position determination for multiplexing, and outputs it as a multiplexed signal 106. .

On the other hand, on the receiving end side, 5 is a frame synchronization circuit, and 6 is a frame synchronization circuit.
is a receiving end separation/conversion circuit, into which a wirelessly transmitted multiplexed signal 106 is input. This frame synchronization circuit 5 detects the signal position required when separating the signal multiplexed on the sending end side on the receiving end side, establishes frame synchronization, and controls the receiving end separation conversion circuit 6. A control signal 112 is sent out. Also,
The receiving end separation and conversion circuit 6 separates the multiplexed signal 106 multiplexed at the sending end according to the control signal 112.
Auxiliary signal 113 and output signal 109 are output.

As mentioned above, the frame synchronization bits that are multiplexed into the signal to operate the frame synchronization circuit 5 are multiplexed by the sending end multiplex conversion circuit 4.
Therefore, even if the pulse stuffing operation is prohibited, frame synchronization will not be affected and frame synchronization will not be lost.

Reference numeral 7 denotes a receiving end synchronization conversion circuit, which input smoothes the output signal 109 of the receiving end separation conversion circuit 6 having a phase gap. Reference numeral 8 denotes a receiving end interface conversion circuit, which inputs the output signal 110 of the receiving end synchronous conversion circuit 7 and outputs an equipment interface output signal 111.

In the above configuration, the fault detection circuit 4 detects that an output signal or a clock signal is present but the transmission signal content is lost due to an output cutoff of the sending end interface conversion circuit 1, especially a fault accompanied by a clock signal cutoff, or an internal logic fault. When an abnormal failure occurs, a failure detection signal 104 is generated. This fault detection signal 104 controls the sending end multiplex conversion circuit 4 and prohibits multiplexing of frame synchronization signals generated within the multiplex conversion circuit 4. As a result,
Multiplexed signal 106 without multiplexing frame synchronization signals
will be sent to the receiving end.

On the other hand, on the receiving end side, the frame synchronization circuit 5 inputs this multiplexed signal 106 to establish frame synchronization, but when a failure occurs, frame synchronization is not established. As a result, the frame synchronization circuit 5 outputs a frame synchronization signal 108.

In other words, in the conventional equipment failure signal transmission circuit,
Equipment failure on the transmitting side was detected using the fact that frame synchronization was not established on the receiving end.

[Problems to be solved]

The conventional device failure signal transmission circuit described above uses frame synchronization, so it is possible to detect device failures unrelated to DSC (Digital Service Channel) signal transmission on the sending side, such as in the sending end interface conversion circuit. There was a problem in that when a failure occurred, auxiliary signals such as DSC signals could not be transmitted.

The present invention was made in view of the above-mentioned problems, and the DSC
The purpose of the present invention is to provide a device failure signal transmission circuit that does not cause any interference to auxiliary signals such as signals.

[Means for solving problems]

In order to achieve the above object, the equipment failure signal transmission circuit of the present invention includes, on the sending end side, a sending end interface conversion circuit that converts the interface format of an input signal, and synchronization of the output of this sending end interface conversion circuit. a synchronous conversion circuit that takes the synchronous conversion circuit, a sending-end multiplex conversion circuit that multiplexes the output of the synchronous conversion circuit, and a fault detection circuit that monitors the sending-end interface conversion circuit and prohibits pulse stuffing in the synchronous conversion circuit when a fault is detected. and a circuit;
On the receiving end side, there is a frame synchronization circuit that performs frame synchronization of multiplexed signals, a receiving end separation/conversion circuit that separates the transmission signal from the multiplexed signal according to the output of this frame synchronization circuit, and a clock for the output of this receiving end separation/conversion circuit. A synchronous conversion circuit that establishes synchronization, a receiving end interface conversion circuit that converts the interface format of the output of this synchronous conversion circuit, and a synchronous conversion circuit that outputs an alarm signal when clock synchronization is not established in the receiving end synchronous conversion circuit. The configuration includes an asynchronous monitoring circuit.

With this configuration, when transmitting a device failure in the transmitting end interface conversion circuit on the transmitting side to the receiving end, it is possible to remove the clock synchronization in the receiving end synchronization conversion circuit on the receiving end without losing frame synchronization. It will be communicated.

Therefore, frame synchronization in the wireless section is always established, and the transmission of auxiliary signals such as DSC signals is not affected in any way.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of an equipment failure signal transmission circuit according to an embodiment of the present invention. Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.

On the sending end side of the figure, the fault detection circuit 2 detects whether an output signal exists but the contents of the transmitted signal become abnormal due to a fault similar to the one described above, especially a fault accompanied by a clock signal disconnection, or an internal fault. Detect failures when Then, the pulse stuffing synchronous conversion operation being performed in the sending end synchronous conversion circuit 3 is prohibited by the fault detection signal 104.

Further, 9 is a synchronous/asynchronous monitoring circuit which serves as a means for detecting this device failure transmission on the receiving end side, and detects the clock synchronization state of the receiving end synchronous conversion circuit 7.

In the above configuration, when a failure similar to that described above occurs, the stuff rate of the sending end synchronous conversion circuit 3 is fixed at "1" or "0" under the control of the failure detection signal 104. As a result, the stuffing information transmission operation of the pulse stuffing synchronous conversion operation being performed within the sending end synchronous conversion circuit 3 is prohibited.

Then, the output signal 1 of this sending end synchronous conversion circuit 3
05 is input to the sending end multiplex conversion circuit 4, where it is multiplexed with an auxiliary signal 107 and a frame synchronization signal necessary for establishing frame synchronization in the radio section, and sent out as a multiplexed signal 106.

On the other hand, on the receiving end side, this multiplexed signal 106 is input to the receiving end separation conversion circuit 6 and frame synchronization circuit 5,
Establish frame synchronization. Next, the receiving end separation conversion circuit 6 extracts the auxiliary signal 113 from the multiplexed signal 106 and outputs the output signal 10 to the receiving end synchronization conversion circuit 7.
Send 9.

However, although this receiving end synchronization conversion circuit 7 normally establishes synchronization (clock synchronization) on the receiving end side using stuffing information transmitted from the sending end,
In this case, stuffing operation is prohibited on the sending end side. That is, since the stuff rate is fixed at "1" or "0", clock synchronization cannot be established. As a result, an asynchronous signal 114 is sent to the synchronous/asynchronous monitoring circuit 9, and a synchronous/asynchronous signal 114 is sent to the synchronous/asynchronous monitoring circuit 9.
The asynchronous monitoring circuit 9 sends out an alarm signal 115.

Note that when detecting a device failure on the transmitting end using the clock being out of synchronization in this way, the frame synchronization in the wireless section remains established, so the transmission of the auxiliary signal is possible.

Further, the present invention is not limited to the above embodiments, but includes various modifications within the scope of the gist. For example, in the above embodiment, the synchronous/asynchronous monitoring circuit receives the asynchronous signal generated by the receiving end synchronous conversion circuit and monitors the synchronization state, but it also monitors the presence or absence of stuffing information transmitted from the sending end. A configuration for direct monitoring is also possible.

〔Effect of the invention〕

As explained above, the present invention prohibits the transmission of stuff information of the stuffing operation in the synchronous conversion circuit on the sending side in order to transmit the equipment failure signal of the sending end interface conversion circuit that is not related to the auxiliary signal transmission. Since the stuff rate is fixed at "1" or "0", auxiliary signal transmission is possible without losing the frame synchronization of wireless digital transmission, and equipment failures in the interface conversion circuit on the sending end are transmitted to the receiving end. This has the advantage that it is possible to provide an equipment failure signal transmission circuit that can perform

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a device failure signal transmission circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional device failure signal transmission circuit. 1: Sending end interface conversion circuit, 2: Failure detection circuit, 3: Sending end synchronous conversion circuit, 6: Receiving end separation conversion circuit, 5: Frame synchronous circuit, 9: Synchronous/asynchronous monitoring circuit.

Claims (1)

[Claims] 1. On the sending end side, a sending end interface conversion circuit that converts the interface format of the input signal;
A synchronous conversion circuit that synchronizes the output of this sending-end interface conversion circuit, a sending-end multiplex conversion circuit that multiplexes the output of this synchronous conversion circuit, and the above-mentioned sending-end interface conversion circuit, and when a failure is detected, the above-mentioned synchronization is performed. It is equipped with a fault detection circuit that prohibits pulse stuffing in the conversion circuit, and on the receiving end side, a frame synchronization circuit that synchronizes the frame of multiplexed signals, and a transmission signal that is separated from the multiplexed signal according to the output of this frame synchronization circuit. a synchronous conversion circuit that establishes clock synchronization of the output of this synchronous conversion circuit; a synchronous conversion circuit that converts the interface format of the output of this synchronous conversion circuit; An equipment failure signal transmission circuit comprising: a synchronous/asynchronous monitoring circuit that outputs an alarm signal when clock synchronization in a conversion circuit is not established.